JP2557343B2 - Driving method for non-volatile semiconductor memory - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a method for driving a memory cell array of a nonvolatile semiconductor memory, in particular, an electrically erasable / rewritable read-only memory (hereinafter abbreviated as E ² PROM). The present invention relates to a method of write driving and erasing driving of a memory cell array in which a large number of memory cells each including one transistor are arranged in a matrix.

[Technical background of the invention]

As shown in FIG. 2, the memory cell in the conventional E ² PROM has a selection transistor Q _a composed of a MOS FET (insulated gate type field effect transistor) and a floating gate type
A storage transistor Q _b consisting FET are connected in series,
The bit line BL is connected to the drain of the selection transistor Q _a , the word line WL is connected to the gate thereof, and the control gate line CG is connected to the control gate of the memory transistor Q _b .

To perform write drive to the memory cell,
The word line with the control gate line CG normally kept at zero potential
Apply high voltage to both WL and bit line BL. Thus, the high voltage writing is applied is performed to the drain D of the memory transistor Q _b. On the other hand, in order to perform the erase drive, the word line WL is held with the bit line BL kept at zero potential.
And a high voltage is applied to both the control gate line CG. Thereby, erasure is performed drain D of the memory transistor Q _b becomes zero potential. Incidentally, in the memory transistor Q _b of the floating gate type, injection of charge for the floating gate FG through the ultrathin insulating film on the drain D side, but is intended for extracting, MNOS-type (Metal Nitride Oxide Semicond
Abbreviation of uctor, the gate insulating layer is an oxide film and a nitride film.
When a layered type FET is used as a storage transistor, it is driven in the same manner as described above.

[Problems of background technology]

However, as described above, one memory cell has two FEs.
Being composed of T increases the cell occupying area on the memory chip, which hinders high integration of the memory cell array.

[Object of the Invention]

The present invention has been made in view of the above circumstances, and provides a method for driving a nonvolatile semiconductor memory in which the area per memory cell is small and the memory cell array can be highly integrated.

[Outline of Invention]

That is, the method for driving the nonvolatile semiconductor memory according to the present invention is
Memory cells composed of floating gate type FETs that store data by accumulating electrons in the floating gates are arranged in a matrix, and the control gates of the MOS transistors belonging to the same row are connected to the same word line. When driving a nonvolatile semiconductor memory having a memory cell array in which the drains of the MOS transistors belonging to the column are connected to the same bit line, electrons move between the floating gate of the selected memory cell and the bit line. First, the word line connected to this memory cell is set to the first potential, and secondly, the bit line connected to this memory cell is set to the second potential, Thirdly, the bit line not connected to this memory cell is set to a potential between the first potential and the second potential.

When electrons are transferred between the floating gate and the bit line of the selected memory cell, first, the word line connected to this memory cell is set to the first potential, and the second Then, the bit line connected to this memory cell is set to the second potential, and the word line not connected to this memory cell is set to the potential between the first potential and the second potential. That is.

Furthermore, when electrons are transferred between the floating gate and the bit line of the selected memory cell, first, the word line connected to this memory cell is set to the first potential, The bit line connected to this memory cell is set to the second potential, and the bit line not connected to this memory cell and the word line not connected to this memory cell are set to the first potential. The electric potential is set between the electric potential and the second electric potential.

Therefore, writing and erasing can be easily performed without impairing the characteristics of the memory cell as described above.

Example of Invention

An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a part of the memory cell array of the E ² PROM. Memory cells M ₁₁ , M ₁₂ , ..., M ₂₁ , M ₂₂ , ... Are arranged in a matrix, and each cell is one. Of the floating gate type FET described above, only one word line WL ₁ , WL ₂ , ... Of each row is commonly connected to each control gate 1 of the memory transistors belonging to the same row. The bit lines BL ₁ , BL ₂ , ... Of each column are commonly connected to each drain D of the memory transistors belonging to the same column. In the memory transistor, 2 is a floating gate and 3 is a thin insulating film (oxide film) on the drain side.

Next, a method of driving the memory cell array will be described.

(1) Write drive As an initial state, the stored contents of all memory cells are erased, and all word lines WL ₁ , WL ₂ , ... Are set to a predetermined potential α (for example, 5
V) and all bit lines BL ₁ , BL ₂ , ...
V) and then the word line WL ₁ and bit line BL ₁ connected to the memory cell (for example, M ₁₁ ) to be written are correspondingly at approximately −α potential (= −5V) and approximately 2α potential. Set to (= 10V). As a result, the drain D of the memory cell (selected cell) M ₁₁ becomes higher by approximately 3α potential (= 15V) than the control gate 1, and the electrons of the floating gate 2 are extracted to the drain D. On the other hand, of the remaining memory cells M ₁₂ , ..., M ₂₁ , M ₂₂ ,.
The drain M of the cell M _{12 in} the non-selected column of the selected row is higher than the control gate 1 by approximately α potential (5 V), and the cell M ₂₁ of the non-selected column in the non-selected row is drained to the control gate 1. D is almost α potential (5V) high, cells in non-selected row
M ₂₂ ... Has a drain D of approximately α with respect to its control gate 1.
Since the potential (5V) is low and the voltage between the drain and the control gate is low, injection and extraction of electrons to the floating gate 2 do not occur, and the memory state does not change. Note that the potential of the source S of each storage transistor may be set to zero potential or α potential in the above write driving, but if it is left floating, power consumption during the write operation can be reduced. .

(2) Erase drive When a memory cell is selected and erased, the voltage relationship with respect to the word line and the bit line is reversed from that of the write drive described in (1) above. That is, first, all the word lines WL ₁ , WL ₂ ... Are set to the reference potential (for example, OV), all the bit lines BL.
₁ , BL ₂ , ... After being set to a predetermined potential α, the word line WL ₁ and the bit line BL ₁ connected to the memory cell (for example, M ₁₁ ) to be erased respectively have a potential of approximately 2α and −. It may be set to the α potential. This allows the selected cell
The drain D of M ₁₁ is approximately 3α with respect to its control gate 1.
The potential is lowered and electrons are injected into the floating gate 2.
On the other hand, the remaining memory cells M ₁₂ , ..., M ₂₁ , M ₂₂ ,
The potential difference between the drain potential and the control gate potential is α potential, the electrons are not injected into or extracted from the floating gate, and the storage state does not change.

When erasing all memory cells at once, all word lines are set to the reference potential as in the erase drive for the selected cells described above.
From the beginning, all word lines WL ₁ , WL ₂ , ... Are set to almost 2α potential, and all bit lines BL ₁ , B are set without setting all bit lines to α potential.
It is sufficient to set L ₂ , ... To almost -α potential.

Note that the source potential of each storage transistor may be set to a zero potential or an α potential during the above-described erasing drive, but if it is left in a floating state, no current flows in any of the non-selected transistors and power consumption is reduced. It can be reduced.

Further, the magnitudes of the reference potential and the α potential in the erasing drive may be different from those in the writing drive. For example, the reference potential in the erasing drive is approximately α in comparison with the reference potential in the writing drive. The potentials may be different. That is, the substrate potential is −α potential, the reference potential at the time of writing is −α potential equal to the substrate potential,
If the reference potential at the time of erasing is zero potential higher than the substrate potential,
If an N-channel FET is used as a memory transistor (that is, its drain is an N ^{+ -type} region on a P-type substrate), it is assumed that −α potential is applied to the bit line connected to the drain during erase driving. Also can suppress the forward current of the N ⁺ / P type substrate junction.

(3) Read drive A reference potential (for example, OV) is applied to the word line of the non-selected row, and a predetermined potential (for example, 5 V higher than the source potential of the storage transistor) is applied to the word line of the selected row including the selected cell. Is applied. As a result, a current flows through the cell transistor according to the stored contents of each cell in the selected row, and the difference in the current flowing through each bit line connected corresponding to each cell is detected.

The 2α potential is twice the α potential when the reference potential is zero, but is generally expressed as a potential higher than the α potential by the potential difference between the α potential and the reference potential.
Similarly, when the reference potential is zero potential, the −α potential has the same absolute value as the α potential and has a polarity opposite to that of the α potential. However, in general terms, the α potential and the reference potential are higher than the reference potential. It is a potential lower by the potential difference between and.

Although the floating gate type is used as the memory cell transistor in the above-described embodiment, the MNOS type can be used in the same manner as in the above embodiment.

〔The invention's effect〕

As described above, according to the method for driving the nonvolatile semiconductor memory of the present invention, one memory cell can be formed by one electrically erasable / rewritable memory transistor.
The area per memory cell is about 1/2 to 1/3 smaller than that of the conventional one, so that the memory cell array can be highly integrated and a large-capacity E ² PROM can be realized.

Further, according to the present invention, by applying a voltage having a predetermined potential relationship to a word line and a bit line in a memory cell array having the above-described features, writing and erasing to selected cells and simultaneous erasing to all cells are selectively performed. It is possible to provide a method for driving a nonvolatile semiconductor memory that can be easily performed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a part of a memory cell array in an E ² PROM according to an embodiment of the present invention, and FIG. 2 is a conventional E ² PROM.
3 is a circuit diagram showing a memory cell in FIG. _{M 11, M 12, ...,} M 21, M 22, ... memory cell, WL _1, WL _2, ...
... word lines, BL _1, BL _2, ...... bit line, 1 ... control gate, 2 ... floating gate, D ... drain, S ... source.

Claims (6)

(57) [Claims] 1. Memory cells composed of floating gate type MOS transistors for storing data by accumulating electrons in the floating gates are arranged in a matrix, and control gates of the memory cells belonging to the same row are the same. In a method for driving a non-volatile semiconductor memory having a memory cell array connected to a word line and having the drains of the memory cells belonging to the same column connected to the same bit line, the selected one is selected from the floating gates of the selected memory cells. When moving electrons to the bit lines connected to the memory cells, as an initial state, all word lines are set to α potential and all bit lines are set to reference potential. The word line connected to the cell is set to -α potential, and the bit line connected to the selected memory cell is set to 2α potential. Method for driving the nonvolatile semiconductor memory. 2. Memory cells composed of floating gate type MOS transistors that store data by accumulating electrons in the floating gates are arranged in a matrix, and control gates of the memory cells belonging to the same row are the same. In a method of driving a non-volatile semiconductor memory having a memory cell array connected to a word line and having the drains of the memory cells belonging to the same column connected to the same bit line, the bit line connected to the selected memory cell When moving electrons to the floating gate of the selected memory cell, all the word lines are set to the reference potential and all the bit lines are set to the α potential as an initial state. The word line connected to the cell is set to 2α potential, and the bit line connected to the selected memory cell is set to −α potential. Method for driving the nonvolatile semiconductor memory. 3. A floating gate type N-channel MOS transistor for storing data by accumulating electrons in the floating gate is arranged in a matrix, and the control gates of the memory cells belonging to the same row are respectively arranged. In a method of driving a nonvolatile semiconductor memory having a memory cell array connected to the same word line and having the drains of the memory cells belonging to the same column connected to the same bit line, the bit connected to the selected memory cell When moving electrons from a line to the floating gate of the selected memory cell, all the word lines are set to the reference potential, all the bit lines are set to the α potential, and the substrate on which the memory cell is formed is initially set. Is set to -α potential, and then the word line connected to the selected memory cell is set to 2α potential to select the selected memory cell. Method for driving the nonvolatile semiconductor memory characterized by a bit line connected to Moriseru to -α potential. 4. The nonvolatile semiconductor memory according to claim 1, 2, or 3, wherein the sources of all the memory cells are set to a fixed potential or a floating state. Driving method. 5. The method of driving a nonvolatile semiconductor memory according to claim 1, 2, or 3, wherein the reference potential is zero potential. 6. When reading data from the memory cells, the sources of all the memory cells are set to a predetermined potential, and the word lines connected to the selected memory cells are set to a potential higher than the predetermined potential. The method for driving a nonvolatile semiconductor memory according to claim 1, claim 2, or claim 3.