JPH0823873B2 - Image forming device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printer such as a laser printer, an ink jet printer, a thermal transfer printer, etc., that is, the structure of an image forming apparatus. More specifically, the jaggies of the image, that is, jaggedness is reduced to improve the image quality of an input image. The present invention relates to an image forming apparatus to improve.

[0002]

2. Description of the Related Art Currently, printers used as image forming apparatuses are mainly 300 dpi. Therefore, many of the signals output from electronic computers are compatible with 300 dpi. However, the 300dpi printer has the drawback that jaggies are noticeable. In order to eliminate this defect, the pixel density should be increased. However, if the pixel density is increased extremely simply, in addition to the increase in page buffer and the printer cost due to the high accuracy of the engine, (1) The bitmap font for 300 dpi, which has been disseminated in the streets, is also added. Not available. (2) There is a disadvantage that widely distributed 300 dpi input devices (scanners, etc.) cannot be used. By the way, in the laser printer, it is difficult to increase the pixel density in the sub-scanning direction, that is, to increase the pitch of paper feed / drum feed, and even if it is possible, the cost will be high. On the other hand, in order to increase the pixel density in the main scanning direction, it suffices to increase the frequency for modulating the laser light, which can be realized relatively easily and at low cost. Therefore, there has been proposed a method of improving the image quality by doubling the pixel positioning accuracy in the main scanning direction and changing the pixel size in 12 steps (USP 4,847,641). This method cuts the pixels of the input image with a mask of a predetermined size and compares it with a pattern written in ROM in advance,
This is a method of correcting the position and size of the corresponding pixel when the pattern matches.

FIG. 34 is an explanatory diagram of this correction method. In the figure, the input data 1 is cut out by the sampling window 2, and compared with the template 3 on the right, and when the data match, the position and size of the corresponding pixel are changed.

FIG. 35 shows an example of a pattern to be modified and a pattern after modification stored in the template 3.
In the figure, the upper part of the arrow is the data to be corrected in the template, and the lower part is the pattern after the correction for that data. The upper pattern shows a corrected pattern for a vertical diagonal line. For example, the leftmost pattern shows that the dots for the central pixel of the window are shifted to the left by ⅓. In this pattern, light black circles indicate pixels that are not currently targeted for correction.

The correction pattern in the middle part of FIG. 35 shows a jaggy reduction process for a horizontal diagonal line, and indicates that the size of the dot to be corrected is 60% of the maximum dot diameter. In addition, the two correction patterns on the right side of the lower row indicate that the size of the dot to be corrected is set to 30% of the maximum dot diameter in the correction of the jaggies with respect to the horizontal diagonal line. That is, by striking a dot having a size of 60% to the white circle on the right one as shown in the correction pattern in the middle row, the jaggies of the diagonal line in the horizontal direction can be made inconspicuous.

[0006]

However, as shown in FIG.
With the method described in the above, it is necessary to have many template patterns, so the processing speed is slow, the amount of memory for storing template patterns is large, and only the pixel arrangement that completely matches the template pattern is corrected. There was a problem that I was not denied.

Further, since the pattern of black to white to black cannot be generated within one pixel in order to correct the position and size in pixel units, it is effective for pixel arrangements such as black, white and black. There was also a problem that the correction could not be performed. Further, as an object of image quality improvement, there is smoothing of density change in addition to jaggies, but there is a problem that density change cannot be smoothed because there are many pixel patterns that give the same intermediate density. there were.

The present invention is to improve the image quality of an input image by using a neural network to reduce jaggies contained in the input image data, that is, jaggedness, and smooth the density change in a halftone image. By using a network that can represent the weight of the input coupling to each neuron in the intermediate layer with a small number of bits after learning the modified pattern as the neural network, the capacity of the buffer that stores the weight is reduced and the circuit scale is reduced. It is to reduce.

[0009]

FIG. 1 is a block diagram showing the principle of the present invention. In the figure, by controlling the correction of the input dot image data according to the arrangement of the input dot image data, jaggies of the image, that is, jaggedness can be reduced, or the density change in the halftone image can be smoothed. FIG. 3 is a principle block diagram of an image forming apparatus for improving the quality of an input dot image.

In FIG. 1, the smoothing means 10 is composed of, for example, three layers of an input layer, an intermediate layer, and an output layer, and after learning, the weight of the input connection to each neuron of the intermediate layer is + n,-.
n and 0 (n is a constant), for example, composed of a three-valued neural network of +1, -1, and 0, and outputs a dot correction instruction for the input image data according to the array of input dot image data To do.

Further, the smoothing means 10 is constituted by a neural network in which the weight of the input coupling to each neuron in the intermediate layer becomes binary of +1 and 0 after learning, and the neural network is provided with an upright signal of pixel data. It is also possible to input both the inverted signal.

[0012]

FIG. 2 shows an example of a pattern to be corrected in the present invention. First, the operation of the present invention will be described with reference to FIGS.

In the present invention, as in FIGS. 34 and 35, the dot size and position of the pixel in the center of the window are corrected and output so as to reduce the jaggies. The relevant dots are limited to some of their surrounding dots, including the central dot, and are often not all the dots in the window. In FIG. 2, after the correction, the central dot moves to the position left shifted by 1/3 dot with the size unchanged, but the data required for this correction is 2 from the left of the upper line. Th black, 3rd, 4th white, 3rd black from the left in the middle row, 4th white, 3 from the left in the bottom row
The second black and the fourth white, and the other dots can be either black or white, that is, they can be considered as don't cares.

Therefore, to the neural network as a part of the smoothing means 10 in FIG. 1, either 0 or 1 is given as the data of the don't care part to repeat the education, and the learning is advanced by increasing the number of patterns. It turned out that the weight of the input coupling to the neurons in the hidden layer converges to any one of +1, -1, and 0. In the present invention, by performing such learning, the processing for reducing jaggies of an image is performed by using a neural network in which the weight of the input coupling to the neurons of the intermediate layer converges to one of three types of 1, −1 and 0. Done.

In FIG. 1, the neural network forming the smoothing means 10 inputs pixel data in a rectangular window corresponding to, for example, five pixels on three lines in the input image data. In accordance with, the converted data of the size and position of the pixel at the center of the window is output.

For example, the size of a dot as a pixel is four values including 60%, 30%, and 0% (no dot is applied) with the maximum diameter being 100%, or 100%, 75%, 50.
%, 25%, and 0%, and in addition to the original input position for the position of the pixel, that is, the dot, there are three positions that are the front and rear positions in the horizontal direction centered on that position. Take one of them.

In the neural network, a plurality of neurons (units) in the output layer output conversion data of pixel size, and a plurality of other units output conversion data of pixel positions. The size and its position are output from independent units. As a result, the number of units in the intermediate layer can be reduced, and the processing speed of the neural network can be improved, as compared with the case where the units in the output layer output the output code in which the pixel size and the position are mixed. be able to.

That is, according to the present invention, since the neural network for instructing dot correction according to the arrangement of the input dot image data is used, it is not necessary to have a large number of template patterns, the processing speed is high, and the memory capacity is large. Is also small, and optimal correction can be instructed even for unlearned patterns.

Next, in FIG. 1, a neural network forming a part of the smoothing means 10 has a rectangular shape corresponding to, for example, nine pixels on seven lines in the input dot image data. A case will be described in which on / off information of a plurality of subdots forming a pixel is output in order to correct the pixel at the center of the window according to the array of pixel data in the window.

For example, when one pixel is expressed by eight subdots, if the resolution in the main scanning direction is 300 dpi, it is always
Higher quality is achieved by performing conversion equivalent to 2,400 dpi and replacing the pixel with an 8-divided pattern that makes jaggies less noticeable and smoothes density changes.

The most noticeable pattern for jaggies is a straight line. Even on a straight line, the inclination of jaggies changes depending on the inclination. FIG. 3 is a diagram showing the relationship between the angle and the conspicuousness. The subjective evaluation value on the vertical axis corresponds to how the jaggies are conspicuous. At 5 points, the jaggies are not known, and as the score decreases, the jaggies become more conspicuous. This figure means that the jaggies are very noticeable at angles slightly deviated from 0 °, 45 ° and 90 °. As a result of examining a correction pattern with 8 subdots at these angles, it was found that the combination of 28 patterns shown in FIG. 4 can be made inconspicuous. There are 256 patterns that can be expressed by 8 sub-dots, but only 28 of them can correct jaggies. In other words, the number of consecutive ON (black) sub-dots corresponds to the dot size, and one input dot is not represented by two or more small dots and is not corrected. The sub-dot pattern representing one dot is black, black-white, black-white-black, white-
There are only six patterns, black to white, white to black, and white, and the pattern shown in FIG. 4 represents all of them. Then, by using these patterns, it is possible to make a correction equivalent to controlling the dot size and the dot position.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 5 is an explanatory diagram of the operation of neurons forming a neural network. A neuron is also called a unit. Generally, a plurality of inputs are multiplied by appropriate coefficients (weights), all the multiplication values are added, and the addition result is converted and output using an appropriate function. . The output y ⁿ of the n-th neuron is given by the following equation.

[0023] _{^{y n = f (k 0 n}} + k 1 n x 1 n + ··· k m n x m n) ········ (1) where x _i ⁿ is the n-th neuron The i-th input of
k _i ⁿ is a coefficient (weight) for the input, k ₀ ⁿ is a constant term, and FIG. 6 is a model of the neural network. In the figure, each circle represents a neuron. Also, units in the input layer (provided input to the network) only distributes input to units in the middle layer,
Omitted. There are three units in the middle layer and two units in the output layer.

In FIG. 5, a sigmoid function or a step function is used as a function for conversion. FIG. 7 shows a sigmoid function, and FIG. 8 shows a step function. The conversion function is not limited to these functions, and other functions can be used.

Generally, the better the number of pixels input to the neural network, the better the image can be corrected. However, the number of patterns to be corrected also increases. For example, input image 5
When it is set to × 5, the number of combinations of all pixels is 25 ^{× 5} , that is, 33554432, and it becomes difficult to hold all the correction patterns. Therefore, the patterns to be modified and the patterns not to be modified are appropriately selected, and the neural network is trained. The pixel is corrected by a neural network using the coefficient obtained by the education, and if the inconvenient conversion is performed, the re-education is performed. With this method, pixels can be corrected without enumerating all patterns, and good pixel conversion can be performed even for patterns that are not previously trained.

FIG. 9 is a diagram showing an example of pixel allocation to each unit in the input layer of the neural network. In the figure (a), an example is shown in which five pixels on each of the three lines are output as one window.
FIG. 7B shows an example in which nine pixels on each of seven lines are output as one window. The window may have a predetermined shape. Then, when the assigned pixel is a black pixel for each of the 15 units (63 units in the same figure (b)) of the input layer, the data for that pixel is set to 1. If the pixel is a white pixel, 0 is given. Note that "1" and "0" may be set in reverse.

FIG. 10 shows an example of the pixel size after conversion. In the figure, the maximum dot diameter is 100%,
Any of four values of diameter 60%, 30%, and 0% (no dot is printed) is designated (level control of 4 gradations).

FIG. 11 shows an example of the positions of pixels, that is, dots, designated by the conversion data. In the figure, the dot position is either the center position as the original input position, the position shifted to the left by 1/3 dot, or the position shifted to the right on the same line as the input position by 1/3 dot. It is specified (equivalent to 900dpi).

FIG. 12 shows an embodiment in which the value of the output of the unit of the output layer of the neural network and the position and size of the pixel correspond to each other. In the figure, the upper 3 bits of the 5-bit data representing the output values of the 5 output units of the neural network represent the dot size, and 000
Is 0% in FIG. 10, 001 is 30%, 010 is 60%, 100
Represents 100%. The lower 2 bits represent the dot position, 00 is the center, 01 is the position shifted to the right by 1/3 dot, and 10 is the position shifted to the left by 1/3 dot.

As described above, in this embodiment, 3 units out of 5 units in the output layer have the dot size of 2 units.
Each unit outputs the data indicating the position, and the output code has a total of 5 bits. The size and position of the dot are represented by a total of 10 states, and it is possible to represent these states by 4 bits. In that case, the size and position of the dot are independent of the unit of the output layer. It became impossible to assign to the output, and the experimental results revealed that the number of units in the intermediate layer increased and the processing speed of the neural network slowed down.

FIG. 13 is a system configuration diagram of an embodiment of the image forming apparatus of the present invention. In the figure, the neurons forming the neural network are configured by hardware.

FIG. 14 is a timing chart of the operation of the system shown in FIG. Processing of input image data will be described with reference to FIGS. 13 and 14. In FIG.
Input data for three lines from a bitmap memory (not shown) is given to the data cutout unit 20. This 3 la
The current line that is the center line of the window in
The processing line is stored in, for example, the central line buffer 21b.
Line above (in general, no
However, the unprocessed data is remapped to the bitmap.
Input from memory. ) Is stored in the line buffer 21a,
The line below it is input to the line buffer 21c.
It As a result, the required three lines of data are taken into the line buffers 21a to 21c.

The data stored in each of the line buffers 21a to 21c is a 5-bit shift register (SR).
22a to 22c, respectively. These three shift registers are connected, and the loaded data is serially output bit by bit from the data cutout unit 20. The outputs from these shift registers may be, for example, in the order in which they were loaded, ie first in, first out, or first in, last out.

Prior to a series of jaggie reduction operations, coefficients are set in the coefficient buffers 25 and 33 in both the intermediate layer and the output layer. Then, the jaggy reduction operation is started. In FIG. 13, the data cutout unit 20 cuts out a 5 × 3 bitmap image using the data input from a bitmap memory (not shown) as described above.

The input image data output from the data slicing section 20 is simultaneously given to the 24 neurons 24a to 24x in the intermediate layer via a unit in the input layer (not shown). Each of the neurons 24a to 24x in the intermediate layer has exactly the same configuration, and all of them operate in parallel.

The operation performed in the intermediate layer is shown in the equation (1), and this operation is performed by the 24 neurons 24a in the intermediate layer.
~ 24x each in parallel. To each neuron in the intermediate layer, 1-bit data representing black or white, that is, either 1 or 0 is input from the data cutout unit 20 as data for each pixel in the window. This input data and coefficient buffer 2
The AND gate 26 in which the coefficient within 5, that is, the weight, is two
a, 26b. Here, the content of the coefficient buffer 25 is one of +1, -1, and 0 as described above, but +1 is 01, -1 is 11, and 0 is 00.
It is expressed in bits. AND gate 26a, 26b
The reason why the two are required is that the coefficient is represented by 2 bits in this way. Further, as the coefficient, when the data which should be black, for example, the data of the second dot from the left in the upper row in FIG. 2 is input, the coefficient is +1, that is, 0.
The value is 1, 11 when the data that should be white is input, and 00 when the don't care data is input.

Since the output of the AND gate 26a is a sign bit, it is commonly given to the adder 27 as the upper 4 bits. Here, it should be black, that is, when black is input to the dot corresponding to the coefficient 01, the contents of the adder 27 are added, and it should be white, that is, the coefficient is 1.
When black is input to the dot of 1, the content of the adder 27 is subtracted. Therefore, for 15 inputs, the output of the adder 27 is in the range of -15 to +15, and the number of output bits of the adder 27 is 5 bits including the sign bit. Adder 2
7 performs addition every time 1-bit data is input from the data cutout unit 20, and outputs the result to the register 28. When the next data is input, the register 28
Is added to the contents of the adder 27 together with the outputs of the AND gates 26a and 26b, and stored in the register 28 again.

This operation is repeated 15 times for 15 pieces of input data, and the final product-sum operation result is held in the register 28. This value is fetched in the register 29, converted, that is, scaled by a function stored in the ROM 30 in the next stage, for example, a step function, and the conversion result is stored in the three-state register 31.

The above corresponds to one cycle of the operation of the hidden layer neuron with respect to the input data for one window. The contents of each three-state register 31 are fixed at the same time because the 24 middle-layer neurons perform a complete parallel operation.

The input to the output layer is scanned by sequentially setting the output enable (OE) of the three-state register 31. The output layer multiplies the selected intermediate layer output by the coefficient and sets it in the register 36 through the adder 35. After scanning all the outputs of the intermediate layer, the value of the register 36 is loaded into the register 37. Register 37
The value set in should pass through the sigmoid function, but the output of the output layer is a binary value of "1" or "0" as well as the input to the intermediate layer, and the sigmoid function is 0.5 with respect to 0.
Is returned, the most significant bit (sign bit) may be output. When the processing for one line is completed, the data for three lines including the next new one line is transferred to the line buffer 21a.
The same operation is performed by loading the data in the files 21 to 21c. With the above operation, the pixel correction can be performed over one page.

FIG. 15 shows an example of the weight of the input connection, that is, the coefficient, for the neurons in the intermediate layer after learning. In the figure, the numbers 1 to 24 in the leftmost column indicate the numbers of the 24 neurons in the middle layer, and the numbers 1 to 15 in the uppermost row represent 15 inputs, that is, for each dot in FIG. The input number (same as the number in FIG. 9) is shown, and the constant term is the constant term k ₀ ⁿ in the equation (1).

In the present invention, each of the 24 neurons in the intermediate layer will detect a specific correction pattern. For example, in FIG. 15, the second neuron detects the pattern of FIG. Therefore, in the second neuron, the coefficient for the black input is 1, the coefficient for the white input is -1, and the coefficient for the don't care input is 0. When the pattern of FIG. 2 is input, the product-sum calculation result obtained by the second neuron is +3 because it is equal to the number of dots that should be black,
The sum of this and the constant term-3, that is, "0" is stored in the ROM 30
The output of the second neuron becomes 1 by detecting by a comparator, for example, instead of scaling by.

Since the pattern of FIG. 2 contains eight don't care dots, one neuron in the middle layer, that is, the second neuron, can modify 256 patterns. It is not necessary to learn all these 256 patterns when learning a neural network. For example, by learning 9 patterns in which 8 dots of don't care are all white, or only one of them is a combination of black, education is possible. It is possible to correct even patterns that have not been done. However, for the dots other than the don't care dots, the correction pattern is limited to the pattern designated as either black or white.

FIG. 16 is a block diagram showing the structure of an intermediate layer neuron in the second embodiment of the image forming apparatus. In the second embodiment, the configurations of the data cutout unit 20 and the output layer neurons 32a to 32e are the same as those in the first embodiment of FIG.

In the second embodiment shown in FIG. 16, the product-sum operation is performed by the up / down counter 43 instead of the adder 27. The content of the coefficient buffer 40 is the same as the content of the coefficient buffer 25 in the first embodiment. The up / down counter 43 is controlled by the decoder 42.

The decoder 42 has two AND gates 41.
The up / down counter 43 is controlled so that when the outputs of a and 41b are 01, they are up-counted, when they are 11, they are down-counted, and when they are 00, they are held. Therefore, as in the first embodiment, when black is input to a dot that should be black, that is, a dot whose coefficient is 01, the content of the up / down counter 43 is up, and a dot that should be white is black. It will be down when entered.

The up / down counter 43 is counted for 15 inputs, and then the contents are registered in the register 4
4 and scaling is performed by the ROM 45, and the conversion result is output to the neuron in the output layer via the three-state register 46.

FIG. 17 is a block diagram showing the configuration of the intermediate layer neuron according to the third embodiment. Also in the third embodiment, the configurations of the data cutout unit and the output layer neuron are the same as those in the first embodiment. However, in the third embodiment, unlike the first and second embodiments, the input from the data cutout unit is left unchanged, that is, the result of using the erect input A and the inverter 49. The two inputs are given. Two inputs A and 2 are given to the selector 50

[0049]

[Outside 1]

[0050]

[Outside 2]

Any one of them is selected in accordance with a control signal from the selection control unit 51, the selection result is input to the AND gate 53 together with the contents of the coefficient buffer 52, and the output of the AND gate 53 is given to the adder 54. . The input to the adder 54 is added to the contents of the register 55 as in the first embodiment, and stored in the register 55 again. This operation is repeated 15 times for 15 inputs, and the final product-sum operation result is stored in the register 56 and stored in the ROM.
The scaling is performed by 57, and the conversion result is given to the neuron in the output layer via the three-state register 58.

FIG. 18 shows a selection control unit 51 in FIG.
2 is an example of the selection control signal given to the selection unit 50 from the above and the coefficient stored in the coefficient buffer 52. As a selection control signal from the selection control unit 51, 0 is set as a signal value for selecting the upright input A for a dot which should be black, and an inverted input 3 is set for a dot position which should be white.
The signal 1 for selecting is output.

[0053]

[Outside 3]

On the other hand, in the coefficient buffer 52, the upright input A
Is 1, that is, the dot position that should be black and the inverted input outside 4 is 1, that is, the dot position that should be white,

[0055]

[Outside 4]

Both are 1, and other than that, that is, the coefficient for the dot position of don't care is 0. The values of the coefficient and the selection control signal shown in FIG. 18 are for the correction pattern of FIG. 2, and the dot number indicates the input number, but the coefficient is 0, that is, the value of the selection control signal is for the don't care dot. The value is 0, that is, a value for selecting the erect signal.

In the above, an example in which a neural network is used for the conversion for shifting the dot position by 1/3 dot before and after the original input position, that is, for the conversion from substantially 300 dpi to 900 dpi has been described. It can be used for conversion of a combination of pixel densities, and can be used not only for pixel conversion in the main scanning direction but also for pixel conversion in the sub scanning direction.

Next, the overall configuration of a printer as an image forming apparatus in the present invention will be shown, and another embodiment will be described in detail in relation to the overall configuration. FIG. 19 is a block diagram of the overall configuration of the printer. In the figure, the printer comprises a controller 60, an image quality correction circuit 61, and a printing mechanism 62. Of these, the contents of the image quality correction circuit 61 will be described later.

The controller 60 includes a processor MPU 63 for overall control, a ROM 64 for storing programs, a ROM 65 for character fonts, a work RAM 66, a page expansion RAM 67, a host computer interface 68 for receiving print data and the like from a host computer, print data and the like. First-in, first-out memory (FIFO) to store
69, a shift register 70, a control panel 71, and an input interface circuit 72.

The printing mechanism 62 includes a power source 74, a mechanical controller 75,
Optical unit 76 for image printing, process unit 7
The mechanical controller 75 includes a motor drive circuit 79 and a sensor interface circuit 80. Then, the optical unit 76 sends a beam detect signal (BD) indicating that the edge of the printer paper has been detected to the image quality correction circuit 61 and the controller 60, and the image quality correction circuit 61 emits light to the optical unit 76. A pulse correction signal is provided.

FIG. 20 is a detailed block diagram of the image quality correction circuit 61 of FIG. In the figure, the image quality correction circuit includes a latch circuit 81 to which a video signal from the controller 60, that is, an input image signal is input, and a two-port random access memory (RA located at a stage subsequent to the latch circuit 81.
M) 82, shift registers 83a to 8 for performing serial / parallel conversion of data output from RAM 82
3n, the outputs from these shift registers are respectively input to the units of the input layer, the neural network (neuro) 84 for outputting the correction data for the pixel in the center of the window, and the two-port for storing the output of the neural network 84 The RAM 85, the latch 86 to which the outputs of the two-port RAM 85 are input, the pulse width correction circuit 87 that outputs a light emission pulse correction signal to the optical unit 76 in the printing mechanism 62 by the outputs of the two-port RAM 85 and the latch 86, and the latch 81 side of the two-port RAM 82 , And a counter 88 for controlling the read / write address on the latch 86 side of the RAM 85, the RAM 8
2, a counter 89 for controlling write / read addresses on the shift register side of the RAM 85 and on the neural network side of the RAM 85, and an overall control unit 90.

FIG. 21 shows the RAM from the controller 60 side.
It is an explanatory view of data input for one line to 82. This data input is applied to the latch 81 and two-port RA shown in FIG.
This will be described with reference to the connection diagram with M82. In the following description, the size of the window for outputting the correction data for the central pixel is 5 × 4.

In FIG. 21, the contents of the RAM 82 shown at the top indicate the present stored contents. For example, data "a, b, c, d, e" is stored in bits 0 to 4 of the address n-1. Bits 0 to 4 correspond to data of one line on the image, and the data of bit 0 is assumed to be most recently stored in the RAM 82. When data of a new line is input, the contents of RAM 82 are sequentially read from address 0 and input to latch 81. At this time, since the RAM 82 and the latch 81 are connected in a format that shifts by one bit as shown in FIG. 22, for example, "e" overflows from the data at the address n-1 and "a, b, c,". d ”is stored.

At this time, the data “v” at the address n−1 from the controller 60 side is input to the input D _{0 of the} latch 81, and these data are again read through the latch 81.
It is stored in the AM 82. Data for one line input by repeating this operation for one line is RA
It is stored in the position of bit 0 on M82. Bits 1-4
The data stored in indicates the data on the line newly stored in the order of bit numbers. Further, according to the address of the RAM 82, the data is stored in order from the left side in order from the data closer to the print start position of each line. The data on the RAM 82 is cleared by continuously writing "0" while scanning outside the area before printing.

When data for one line is newly input to the RAM 82 in FIG. 20, the neural network 84 processes the window composed of four pixels on five lines, for example. Data is input from the RAM 82 to the shift registers 83a to 83n.

FIG. 23 is an explanatory diagram of data input to the shift register. Assuming that the window to be currently processed on the RAM 82 starts from the address n−1, first, the data “A, B,
C, D, and E ″ are input to five shift registers respectively. Next, the data of address n is input to each of five shift registers, but the data at address n−1 at that time is shifted in the shift register. To be done.

FIG. 24 shows a RAM 82 and a shift register 83.
It is a connection diagram with a-83n. In the figure, RAM8
Data serially output bit by bit according to the address from 2 is input to the shift register corresponding to each bit position, and stored in each shift register bit by bit, being shifted downward in the figure.

When the data on one window is stored in each shift register, the output from each shift register 83a to 83n is performed to the neural network in FIG. This output is done in parallel. Therefore, each shift register performs serial / parallel conversion.

Data input / output to / from the shift register is performed according to the processing speed of the neural network, and is controlled by the count value generated by the counter 89 in FIG. Generally, since the processing speed of the neural network is not so fast, for example, the data to the neural network 84 is input at a timing unrelated to the image data input to the RAM 82, that is, the data input performed at the timing of the count value generated by the counter 88. Input is made. Each shift register 83a-8
The data in 3n are all cleared at the beginning of each line.

The processing result of the neural network 84,
That is, the correction data for the size and position (shift) of the dot as the central pixel is output to the latch 86 and the pulse width correction circuit 87 via the RAM 85. RA
M85 is used for adjusting the timing between the neural network 84 and the light emission pulse correction signal output, as in the input side. Note that here, the correction data for the central pixel output from the neuro 84 is 4 bits for size and 2 bits for position (shift), which is a total of 6 bits.

FIG. 25 is a block diagram showing the configuration of the pulse width correction circuit 87 shown in FIG. In the figure, the pulse width correction circuit 87 outputs the 6-bit output from the latch 86 and the latch 86.
6 bits directly output from RAM 85 and a total of 12 bits as an address are input as an address, and a read-only memory (ROM) 88 and an output of ROM 88 are input, and parallel / serial conversion is performed to perform a light emission pulse correction signal. Is composed of a shift register 89 which outputs

FIG. 26 shows an example of a light emission pulse corresponding to designation of dot size and shift. The size of the figure (a) is 8
At / 8, the shift is at the center, that is, a light emission pulse for designating a dot of maximum size at the original input position,
At this time, all the 8 bits of the light emission signal are 1.
On the other hand, when the size is set to 2/8 and the shift is set to the center, as shown in Fig. 6 (b), the emission pulse correction signal is 1 for the central 4th and 5th bits and 0 for all other bits. is there.

FIG. 26C shows the case where the size is 8/8 and the shift right is designated. The correction signal is 0 for the 1st to 3rd bits and 1 for the 4th to 8th bits. Is a correction signal for the window of
When 8 is specified, the signal value becomes "1" for 8 bits as shown in Fig. (A). Therefore, "1" for the remaining 3 bits is output when the emission pulse correction signal for the next window is output. Should be output. Also, the same figure
As shown in (d), in order to specify size 4/8 and shift right, a 1-bit '1' protruding to the right rule must be output when the correction signal is output to the next window.

FIG. 27 shows an example in which the remaining data for the dots in the previous window and the data for the current dot are combined to form a light emission pulse correction signal. As shown in FIG. 25, the read address of the ROM 88 is the size and shift designation data for the central dot of the previous window stored in the latch 86, and the size for the central dot of the current window directly input from the RAM 85. And a shift designation data. The ROM 88 stores a light emission pulse correction signal to be combined with this address and output. The data is optically transmitted as a serial signal via the shift register 89. Unit 7
6 is output.

FIG. 28 is an operation timing chart of the image quality correction circuit. In the figure, the optical unit 7 of FIG.
When a beam detect signal (BD) indicating that the edge of the printer paper has been detected is input from 6,
The counters 88 and 89 are reset and data is input from the controller 60 of FIG. 19 to the RAM 82 of FIG. 20 in accordance with the video data clock (VDCLK). The write address at this time is designated by the counter 88. When the data for one line is written, the writing is prohibited until the next BD signal is input. This is because data outside the area is not written. The addresses 0 to 2047 indicate write addresses for one line.

On the other hand, the data output from the RAM 82 to the neuro 84 is started at the same time as the BD signal is input, but the input is performed at a timing later than the timing of the data input to the RAM 82. Then, each time the processing for one window on the neuro 84 is completed, the dot size and shift data are output to the RAM 85. This output is performed by the count value of the counter 89. At this time, the RAM 85 stores the size and shift data as the dot correction data for the previous line, and this data is the same timing as the data input timing from the controller to the RAM 82, that is, the output of the counter 88. Output to the latch 86 and the pulse width correction circuit 87 according to the count value.

FIG. 29 shows a system configuration diagram of still another embodiment of the image forming apparatus of the present invention. In the figure, the neurons that make up the neural network are made up of hardware and output a sub-dot pattern in response to the input of dot image data.

FIG. 30 is a timing chart of the operation of the system shown in FIG. Processing of input dot image data will be described with reference to FIGS. 29 and 30. In FIG. 29, the dot image data from the bit map memory (not shown) includes a line buffer for 7 lines and a data cutting section configured by a register for holding rectangular dot image data for 7 lines × 9 pixels through a neural network. Given to. The dot image data for 63 pixels, which is a 7 × 9 bitmap image cut out by the data cutout unit, is assigned with pixels as shown in FIG. 9B. Then, this dot image data is input to the 9-bit shift registers 102a to 102g forming the unit of the input layer 101, and then the intermediate layer 103.
22 neurons 24a to 24v are simultaneously given one bit at a time. Neurons 24a to 24 of the intermediate layer 103
v has the same configuration except for the value of the coefficient set for each neuron 24a to 24v, and all are configured to operate in parallel.

Since the operation of each circuit in each neuron 24a to 24v is the same as that of each neuron 24a to 24x in the first embodiment shown in FIG. 13, its detailed description will be omitted.

The only difference between the two is that the number of coefficients stored in each coefficient buffer 104 in each of the neurons 24a to 24v shown in FIG. 29 is 63, and the AND gate 26 has 63 coefficients at one time. That is, the data of is input. Note that the coefficient in the coefficient buffer is generally n here.
I have a bit.

On the other hand, the output of each of the 22 neurons 24a to 24v of the intermediate layer 103 is the same as that of the 8 neurons 32a to 3v.
It is provided to the output layer 105 composed of 2h. The circuit configuration of the eight neurons 32a to 32h in this output layer is
Output layer neuron 3 in the embodiment shown in FIG.
2a to 32e are substantially the same, and detailed description of the configuration and operation thereof will be omitted.

The difference between the two is that, like the neurons in the intermediate layer 103, the number of coefficients stored in the coefficient buffer 106 of each of the neurons 32a to 32h is 22 according to the number of neurons in the intermediate layer 103. There is a point.

In the structure described above, the input layer 10
In the neural network including the intermediate layer 103, the intermediate layer 103, and the output layer 105, the intermediate layer 103 is input every time 7 × 9 dots in which the pixel to be corrected is set to the central pixel, that is, 63 pixel data in total are input. Performs arithmetic processing on each pixel data and coefficient data. Next, the output layer 105 outputs the output data of the neurons of the intermediate layer 103 and the coefficient buffer 1
The arithmetic processing with the coefficient data held in 06 is performed. Then, the eight neurons of the output layer 105 generate an optimum sub-dot pattern corresponding to the pixel array pattern of the dot image data input to the neural network by 7 ×.
It is output to a print head controller (not shown) as data indicating the center pixel of the window of No. 9. This optimum sub-dot pattern is any one of the 28 patterns shown in FIG.

31 and 32 are diagrams showing the relationship between the input pattern given to the neural network in the embodiment shown in FIG. 29 and the teacher pattern for the input pattern. The upper side of the arrow in each figure is the input pattern, and the lower side is the teacher pattern.

As shown in FIG. 31 (a), the center pixel of the 7 × 9 window of the teacher pattern is on the right side of the eight subdots even though the center pixel of the input pattern is white. 3 sub-dots are converted to black. On the other hand, as shown in FIG. 31 (b), in the case of the input pattern shown in FIG. 31 (a) in which all the dots are shifted by one dot to the left, the central pixel of the input pattern is black. However, of the eight subdots, the right three subdots are converted to white.

Therefore, by learning FIG. 31 (a) and FIG. 31 (b) as a teacher pattern, FIG. 31 (a), (b)
It is possible to correct the jaggy of the input pattern as shown in FIG.

FIG. 31 (c) shows an example in which three subdots on the left side of the eight subdots having black central pixels are converted to white. FIG. 31D is an example in which the black central pixel is output without being converted.

FIG. 32A shows an example in which, out of the eight subdots having the white central pixel, the central four subdots are converted to black. FIG. 32B shows an example in which the sub-dots at both ends of the eight sub-dots having the black central pixel are converted to white. In the example of FIG. 32 (b), when the pixel to the right of the center pixel becomes the center pixel,
Of these subdots, two on each side, a total of four subdots, are converted to white, and the two pixels on the right are converted to black even though the central two subdots are white. , Each dot is corrected so that the dot size gradually changes.

Further, FIGS. 32C and 32D show an example in which some central subdots among the eight subdots having white central pixels are converted to black. Figure 32 (c)
, The example of FIG. 32 (d) is similar to the example of FIG. 32 (b).
In (c) and FIG. 32 (d), the white and black pixels adjacent to the pixel which is the central pixel are converted into small dots.

Incidentally, FIG. 33 shows the case of FIG.
33 shows a pattern obtained as a result of performing the correction as shown in FIG. In the figure, a dot that appears light in color means that the dot position and size, that is, the exposure timing has been corrected.

The function for transforming a neuron in the above description is not limited to the sigmoid function or the step function, and another function, for example, a function obtained by approximating a sigmoid function with a straight line, or a straight line can be used. Furthermore, the present invention can be applied not only to electrophotographic printers such as laser printers, but also to inkjet printers, thermal transfer printers, and the like.

[0092]

As described in detail above, according to the present invention, by using a neural network, it is possible to correct image data even for a pattern other than a pattern learned as a correction target. Since it is not necessary to have a mask pattern, it is possible to save memory, and this greatly contributes to improving the quality of the output image of the printer.

Further, the input value for the don't care dot is set to either 0 or 1, and the learning of the neural network is performed, so that the weight of the input connection to the hidden layer neuron is one of three values of +1, -1, and 0. , And the capacity of the weight buffer for the hidden layer neuron becomes small, and the circuit scale can be greatly reduced.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a diagram showing an example of a pattern to be modified which is a target of the present invention.

FIG. 3 is a diagram showing a relationship between an angle and how to stand out.

FIG. 4 is a diagram showing a sub-dot pattern required to reduce jaggies.

FIG. 5 is an explanatory diagram of an operation of a neuron.

FIG. 6 is a diagram showing a model of a neural network.

FIG. 7 is a diagram showing a sigmoid function.

FIG. 8 is a diagram showing a step function.

FIG. 9 is a diagram showing an example of pixel allocation to a unit of an input layer.

FIG. 10 is a diagram showing an example of a pixel size.

FIG. 11 is a diagram showing an example of positions of pixels as conversion data.

FIG. 12 is a diagram showing an example of correspondence between output values of output layer units, positions and sizes of pixels.

FIG. 13 is a block diagram showing a system configuration of a first embodiment of the image forming apparatus.

14 is a timing chart of the operation of the system of FIG.

FIG. 15 is a diagram showing an example of coefficients for a middle-layer neuron after learning.

FIG. 16 is a block diagram showing the configuration of an intermediate layer neuron in the second embodiment of the image forming apparatus.

FIG. 17 is a block diagram showing a configuration of an intermediate layer neuron in a third embodiment of the image forming apparatus.

18 is a diagram showing an example of contents of a coefficient buffer and a selection control signal in FIG.

FIG. 19 is a block diagram showing an overall configuration of a printer as an image forming apparatus.

FIG. 20 is a block diagram showing a detailed configuration of an image quality correction circuit.

FIG. 21 is an explanatory diagram of one-line image data input.

FIG. 22 is a connection diagram of a latch on the image data input side and a RAM.

FIG. 23 is an explanatory diagram of data input to a shift register.

FIG. 24 is a connection diagram of a RAM on the image data input side and a shift register.

FIG. 25 is a block diagram showing a configuration of a pulse width correction circuit.

FIG. 26 is a diagram showing an example of a light emission pulse correction signal designated by dot size and shift.

FIG. 27 is a diagram showing an example of a light emission pulse correction signal by combining the dot remaining data of the previous window and the dot data of the current window.

FIG. 28 is an operation timing chart of the image quality correction circuit.

FIG. 29 is a block diagram showing a system configuration of still another embodiment of the image forming apparatus.

FIG. 30 is an operation timing chart of the image forming apparatus.

FIG. 31 is a diagram showing an example of a correction pattern (teacher pattern).

FIG. 32 is a diagram showing an example of a correction pattern (teacher pattern).

FIG. 33 is a diagram showing an example of correcting a character and a straight line.

FIG. 34 is a diagram illustrating a conventional example of a method for improving the image quality of input image data.

FIG. 35 is a diagram showing an example of a correction pattern.

[Explanation of symbols]

 10 Smoothing Means (Neural Network) 20 Data Extraction Unit 21a to 21c Line Buffer 22a to 22c Shift Register 24a to 24x Intermediate Layer Neuron 25 Intermediate Layer Neuron Coefficient Buffer 32a to 32e Intermediate Layer Neuron 33 Output Layer Neuron Coefficient Buffer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication location H04N 1/409 (72) Inventor Toshio Kunanaka 1015 Uedoda, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited (72) Inventor Kazuhiko Sato 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited (56) References JP-A-2-43665 (JP, A) JP-A-2-72491 (JP, A)

Claims (3)

[Claims] 1. An image forming apparatus having a smoothing unit for smoothing an image by correcting dots as pixels in the dot image data according to an array of input dot image data, The conversion means is a weighting factor for each neuron in the hidden layer.
There is a 0 or a positive, and growth is, and the neural network comprises a neural network (10) comprising a binary
An upright signal of the dot image data is sent to the network (10).
An image forming apparatus, wherein an inversion signal is input . 2. The positive weighting factor is +1.
The image forming apparatus according to claim 1, which is a characteristic. 3. The smoothing means is the neural network.
Correct dot size and position according to network output
Claim 1 or characterized in that it comprises means for performing
2. The image forming apparatus according to 2.