JP2532177B2 - Image forming device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printer such as a laser printer, an ink jet printer, and a thermal transfer printer, that is, an image forming apparatus, and more specifically, to reduce jaggies of images, that is, jaggedness of images.
The present invention relates to an image forming apparatus capable of improving the image quality of an input image.

[0002]

2. Description of the Related Art Currently, printers used as image forming apparatuses are mainly 300 dpi. Therefore, many of the signals output from electronic computers are compatible with 300 dpi. However, the 300dpi printer has the drawback that jaggies are noticeable. In order to eliminate this defect, the pixel density should be increased. However, if the pixel density is increased very simply, in addition to an increase in the page buffer and an increase in the printer cost due to the higher accuracy of the engine, (1) the bitmap font for 300 dpi that is distributed between the volumes. (2) There is a drawback that you cannot use the widely distributed 300 dpi input devices (scanner, etc.). By the way, in the laser printer, it is difficult to increase the pixel density in the sub-scanning direction, that is, to increase the pitch of paper feed / drum feed, and even if it is possible, the cost will be high. On the other hand, in order to increase the pixel density in the main scanning direction, it suffices to increase the frequency for modulating the laser light, which can be realized relatively easily and at low cost. Therefore, a method has been proposed in which the positioning accuracy of pixels in the main scanning direction is tripled and the size of pixels is changed in 12 steps to improve image quality (USP 4,847,641). In this method, the pixels of the input image are cut out with a mask of a predetermined size, compared with a pattern written in ROM in advance, and when they match the pattern, the position and size of the corresponding pixel are determined. How to fix it.

FIG. 14 is an explanatory diagram of this correction method.
In the figure, the input data 1 is cut out in the sampling window 2 and compared with the template 3 on the right side of the figure, and when the data match, the position and size of the corresponding pixel are changed.

[0004]

However, in the method as described with reference to FIG. 14, in order to improve the image quality by paying attention, that is, by correcting the size and position of only the central pixel of the template, a combination of original images is used. Depending on Figure 1
As shown in FIG. 5, the pixel is divided, and the image quality after correction may be rather deteriorated.

Further, in order to change the pixel size in 12 steps and the position in, for example, the original input position and the three steps of the preceding stage, 36 kinds of light emission timing must be selectively generated, and the light There is also a problem that the circuit scale of the modulation section becomes large.

Further, there is a problem that the correction is not performed if the pattern is slightly different from the pattern written in the ROM in advance. The present invention compares the data of the pixel of interest and its surrounding pixels with a predetermined pattern, and simultaneously corrects the sizes of the central pixel and the pixels on its left and right sides to reduce jaggies and reduce the image quality. To improve. Another object of the present invention is to improve the image quality of a learning pattern, that is, a pattern that is slightly different from a predetermined pattern, by inputting the data of the pixels in the window to the neural network.

[0007]

FIG. 1 is a block diagram showing the principle of the present invention. FIG. 1 is a principle block diagram of an image forming apparatus, for example, a laser printer, which reduces jaggies included in an input image, that is, jaggedness to improve image quality.

In FIG. 1, the window data cut-out means 6 is composed of, for example, a line buffer and a shift register, etc., and is a window composed of one or more pixels on one or more lines from the input image data, for example, 9 ×. The pixel data in the window of size 7 is cut out.

The correction data output means 7 divides the center pixel of the window and the left and right pixels adjacent to each other on the same line as the center pixel into N divisions according to the data of the cut-out pixel in the window. For example, it is divided into three, and the correction data for each 3 × N, for example, 9 pixels, which are each divided into N, are output as the correction data corresponding to the center pixel in the order of left, center, and right pixels. When the correction data for each of the three divided pixels is 1 bit, the correction data is 9 bits and when the correction data is 2 bits, it is 18 bits.

The central pixel corresponding correction data output from the correction data output means 7 is input to the output pixel data output means 8. The output pixel data output means 8 outputs the processing result by itself at the input time point one time before the current input time point, that is, at the input time point of the pixel correspondence correction data on the left side of the center pixel of the window, and the current center point. Processing is performed using the pixel correspondence correction data, and the output pixel data for the pixel on the left side of the pixel on the left side adjacent to the center pixel in the window is output. That is, the output data for the pixel two pixels to the left of the current center pixel is output,
Printing is performed based on the data.

[0011]

In the present invention, for example, from the data of 7 lines input from the bit map memory, a window of 9 × 7 pixels consisting of 9 pixels is cut out on each line, and the window within the window is cut out. The pixel data is compared with, for example, a predetermined template. If it matches the template, the center and left and right pixels of the window are
For example, the correction data for 9 pixels each divided into 3 is output. For example, if the pixel data represents four gradations, each of the correction data has 2 bits, and the correction data for 9 pixels has a total of 18 bits. Of these, the central 6 bits correspond to the central pixel in the window, the left 6 bits correspond to the left pixel, and the right 6 bits correspond to the right pixel.

The 18-bit correction data is input to, for example, a register that constitutes the output pixel data output means 8 as correction data corresponding to the central pixel in the window. On the other hand, in the shift register, for example, as a component of the output pixel data output means 8, the input data at a time point before the current input data for the correction for the central pixel is input, that is, the correction data for the pixel on the left of the central pixel. The processing result at the time of input of is stored. The contents of the shift register are shifted to the left side at the time of inputting the current central pixel corresponding correction data, for example, by 6 bits for three divided pixels,
As a result, the 6-bit data overflowing from the shift register is sent to the light modulation circuit as output pixel data. This is because this shift register and the above-mentioned register have the same capacity.

The shifted result in the shift register,
The respective logical sums of the corresponding bit positions with the central pixel corresponding correction data stored in the above-mentioned register are again stored in the shift register as the processing result of the output pixel data output means 8 at the present time. Is used for processing at the time of inputting, that is, at the time of inputting the pixel-corresponding correction data on the right side of the central pixel.

As described above, in the present invention, not only the pixel at the center of the window but also the data on the left and right pixels are simultaneously corrected.

[0015]

FIG. 2 shows an embodiment of gradation for each divided pixel when the pixel in the center of the window and the pixels on the left and right of the window are divided into N, for example, 3 in the present invention. In the figure, (a) is an example of density gradation, and (b) is an example of area gradation. Each divided pixel is represented by 4 gradations including white, and its data is 2 bits, and 00 to 11 Is displayed as.

FIG. 3 is a system configuration block diagram of the first embodiment of the image forming apparatus of the present invention, and FIG. 4 is a timing chart showing the operation of the first embodiment. The operation of the system shown in FIG. 3 will be described with reference to FIG.

In FIG. 3, input data for 7 lines from a bit map memory (not shown) is given to the data cutout unit 10. Of these 7 lines, the window
The current processing line, which is the center line, is
The line buffer 11d has three lines (generally
Although processing for these lines has already been completed,
The data before processing is input again from the bitmap memory.
It ) To the line buffers 11a to 11c, respectively.
The three lines below the line buffer are line buffers 11e to 11e, respectively.
Input to 11g. De of seven lines required by this
This means that the data has been taken into the line buffers 11a to 11g.

The data stored in each of the line buffers 11a to 11g is a 9-bit shift register (SR).
12a-12g, respectively. The data loaded in these seven shift registers are serially output bit by bit from the data cutout unit 10.

Prior to data input from the data cutout unit 10 to the correction pattern output unit 15, the counter 16 in the correction pattern output unit is reset as shown in FIG. The count value of the counter 16 corresponds to the template number for comparison with the image data in the window. Template 17 after resetting counter 16
Are loaded, and the contents thereof are compared with the input data from the data cutout unit 10 by the comparator 18.

The input data corresponds to 63 pixels in the window and is 1-bit data indicating whether the pixel is black or white, that is, 63-bit data in total. The template data to be compared is 01, which represents black. In addition to 00 representing white, either black or white may be used, that is, 10 representing don't care results in 2 bits per pixel, which is a total.
It will be 126 bits.

If the input data does not match the template, the counter 16 is incremented and a comparison with the next template is made. FIG. 5 is an example of a template. In the figure, light black circles indicate don't cares, that is, pixels that may be black or white.

When a certain template matches the input data in the window, the correction pattern 19 at the address indicated by the counter 16 at that time is stored in the three-state register 21 via the selector 20. This correction pattern is a correction pattern for the correction pixel obtained by dividing the central pixel of the window having a size of 9 × 7 pixels and the pixels on the left and right of the central pixel into three. The total of nine correction pixel data is 18 bits in total. The most significant 6 bits are the left pixel in the center of the window, the middle 6 bits are the center pixel, and the right 6 bits are the right pixel. The data of the pixel which it did is shown. In the case of the area gradation shown in FIG. 2B, the correction pattern is set from left to right, that is, the dot size monotonically decreases.

Input data from the data cutout unit 10,
That is, when the data in the window does not match all of the template 17, the data in FIG. 6 is passed through the selector 20 as correction data for nine pixels obtained by dividing the center and left and right pixels of the window into three. Stored in the three-state register 21. If the central pixel is black, ie 1, 111111 only for the central pixel and 00000 for the left and right pixels.
When 0 is stored and the central pixel is white, that is, when 0 is stored, 000000 is stored for all three pixels.

In FIG. 3, three-state register 2
The correction pattern stored in 1 is the correction pattern output unit 15
To register 23. As described above, the contents stored in the register 23 are the 6-bit data for the three pixels obtained by dividing the central pixel in the window into three in the center, the 6-bit data for the left pixel in the upper, and the right in the right. The 6-bit data for the pixel is stored in the lower order, and the total is 18 bits.

For the first window in FIG. 4, the correction pattern of FIG. 6 was output to the register 23 because no matching template was found in the comparison with all of the P templates, whereas the following: This means that the data of template 2 coincides with the input image data and the correction pattern corresponding to the data is output to the window of (2), that is, the window in which the right pixel is the central pixel.

When the correction pattern for the center pixel of the window is stored in the register 23, the shift register 2
The processing result of the output of the three-state register 21 before the temporary point stored in 5 is divided into three pixels, that is, 6
Bits are shifted left. The shift register 25 has the same capacity as the register 23, and the shift register 2
The 6 bits overflowing from 5, that is, the data for the three divided pixels are output to the printer head. This data corresponds to the second pixel to the left of the current center pixel of the window and is sent to the printer head as print data.

For the correction pattern stored in register 23 for the center pixel of the current window, the shifted result in shift register 25 and OR gate 24
Is ORed by. This logical sum is the register 23
Are taken by the corresponding bits of the shift register 25, and the result of the logical sum is stored again in the shift register 25, and at the time of output from the next three-state register 21,
That is, it is used for the processing at the time of outputting the correction pattern for the pixel on the right side of the center pixel in the current window.

FIG. 7 is an explanatory diagram of the operation of the register 23 and the shift register 25 shown in FIG. In the figure (a), the contents of the shift register 25, 0333300330 (3
Is a decimal number, which is 11 in a binary number), 033 corresponding to the three leftmost pixels is sent to the printer head, and the contents of the shift register are shifted to the left by three pixels. The logical sum of the shift result and the output value 030333300 of the three-state register 21 stored in the register 23 is calculated, and the logical sum 330333300 is stored again in the shift register. FIG. 6B is an example of another case.

FIG. 8 shows an embodiment of a circuit which directly uses the output result of the shift register 25 of FIG. 3 as an optical modulation signal. In the same figure (a), the input signal is 2 bits for each divided pixel as shown in FIG.
The 2-bit data is input to the A / D converter 30, converted into an analog signal, added to the operational amplifier 31, and used for controlling the laser diode 32. FIG. 2B shows an example in which the input signal is, for example, 1 bit of 0 or 1 indicating either white or black. The signal is directly input to the operational amplifier 31, and the light emission of the laser diode 32 is controlled. To be done.

Although the first embodiment of FIG. 3 describes the embodiment in which the pixel data in the window is compared with the template, in this embodiment, except for the don't care bit, an input that completely matches the template data is input. An appropriate correction pattern is output only for the data. On the other hand, when the correction pattern is output by the neural network, it is possible to output an appropriate correction pattern even for input patterns other than the learned patterns. Therefore, in order to describe the embodiment using the neural network, firstly the neural network in general will be described.

FIG. 9 is a diagram for explaining the operation of the neurons that make up the neural network. A neuron is also called a unit. Generally, a plurality of inputs are multiplied by appropriate coefficients (weights), all the multiplication values are added, and the addition result is converted and output using an appropriate function. . The output y ⁿ of the n-th neuron is given by the following equation.

Y ⁿ = f (k ₀ ⁿ + k ₁ ⁿ x ₁ ⁿ + ... + k _m ⁿ x _m ⁿ ) ... (1) where x _i ⁿ is to the n-th neuron Is the i-th input, k _i ⁿ is a coefficient (weight) for that input, k ₀ ⁿ is a constant term, and FIG. 10 is a model of the neural network. In the figure, each circle represents a neuron. Also, the units in the input layer (provided the input to the network) only distributes the input to the units in the middle layer and are omitted. There are three units in the middle layer and two units in the output layer.

In FIG. 9, a sigmoid function or a step function is used as a conversion function. FIG. 11 shows a sigmoid function, and FIG. 12 shows a step function. The conversion function is not limited to these functions, and other functions can be used.

Generally, the better the number of pixels input to the neural network, the better the pixel can be corrected. However, the number of patterns to be corrected also increases. For example, assuming that the number of input pixels is 5 × 5, the number of combinations of all pixels is 25 ^{× 5} , that is, 33554432, and it becomes difficult to hold all correction patterns. Therefore, the patterns to be modified and the patterns not to be modified are appropriately selected, and the neural network is trained. The pixel is corrected by a neural network using the coefficient obtained by the education, and if the inconvenient conversion is performed, the re-education is performed.

With this method, pixels can be corrected without enumerating all patterns, and good pixel conversion can be performed even for patterns that are not previously trained. FIG.
3 is a system configuration diagram of the second embodiment of the image forming apparatus. In the figure, the neurons that make up the neural network are made up of hardware.

In FIG. 13, input data from a bit map memory (not shown) is given to the data cutout unit 40. The data for one line from the bit map memory is fetched into any one of the seven line buffers 41a to 41g. Due to the processing of pixels before the current input line, the other 6 line buffers already have the previous 6
The data of one line has been fetched, and the necessary pixels for seven lines have been fetched into the line buffers 41a to 41g.

The data stored in each of the line buffers 41a to 41g is a 9-bit shift register (SR).
42a-42g, respectively. These seven shift registers are connected, and the loaded data is serially output bit by bit from the data cutout unit 40. The outputs from these shift registers may be, for example, in the order in which they were loaded, ie first in, first out, or first in, last out.

The input image data output from the data slicing section 40 is simultaneously given to the 16 neurons 44a to 44p in the intermediate layer via a unit in the input layer (not shown). Each of the neurons 44a to 44p in the intermediate layer has exactly the same configuration, and all of them operate in parallel.

Prior to a series of jaggy reduction operations, coefficients are set in the coefficient buffers 45 and 53 in both the intermediate layer and the output layer. Then, the jaggy reduction operation is started. Next, the intermediate layer will be described. The calculation performed by the intermediate layer is as shown in equation (1), but since the input is 0 or 1, multiplication is not necessary, and if 1 then add the coefficient, and if 0 do not add the coefficient. The product-sum operation can be performed only with. That is, it suffices to determine whether to add the values stored in the coefficient buffer 45 according to the input value. For this purpose AN
The D gate 46 is used. 1-bit data at a predetermined bit position of the shift register is input to one input n-bit of the AND gate 46. Each bit of the coefficient is input to the other input, and the AND gate outputs 0 or the coefficient. The content of the coefficient buffer 45 is determined by the back propagation method, for example. The adder 47 and the register 48 in the next stage are used for addition. When 15 pieces have been calculated,
The result of the addition is loaded into the register 49 at the next stage. The contents of this register are set in the three-state register 51 after conversion by the sigmoid function stored in the ROM 50 of the next stage.

The input to the output layer is scanned by sequentially setting the output enable (OE) of the three-state register 51. The output layer multiplies the selected intermediate layer output by the coefficient and sets the result in the register 56 through the adder 55. After scanning all the outputs of the intermediate layer, the value of the register 56 is loaded into the register 57. When the processing for one line is completed, the same operation is performed in a state where the data for seven lines including the next new one line is fetched in the line buffers 41a to 41c. With the above operation, the pixel correction can be performed over one page.

Nine neurons 52a to 52i in the output layer
The output of each is 2 bits, and a total of 18 bits in which they are arranged in order are stored in the register 58. Register 5
8, the operation of the logical adder 59 and the shift register 60 is the register 23 and the logical adder 2 in FIG. 3 showing the first embodiment.
4 and the operation of the shift register 25 are the same.

In the above description, the size of the window cut out from the input image data is set to 9 × 7 pixels, and the central and left and right three pixels in the window are each divided into three. The number of pixels is not limited to this, and it is of course possible to set 5 × 3 pixels and divide the number of pixels into, for example, four. Although the data of the divided pixels is represented by 2 bits, the number of divisions can be increased by setting this to 1 bit. For example, it is possible to divide the original pixel into 16 parts and represent the data of each divided pixel with 1 bit.

The window in the present invention is 7 × 9.
Not only the window having a predetermined shape but also a predetermined shape may be used. In addition, the present invention can be applied not only to a printing apparatus but also to a display apparatus. Further, for each 3 bits obtained by dividing each of the left and right pixels into 3 parts, all the bits are not used. It is also possible to use a part thereof, for example, 2 bits or 1 bit out of 3 bits.

[0044]

As described above in detail, according to the present invention, not only the pixel at the center of the window but also the data at the pixels on the left and right of the window can be corrected at the same time, so that good image quality correction can be performed. It greatly contributes to the high quality of the output image of the printer. Furthermore, the output of the shift register can be used as it is as an optical modulation signal, and the circuit of the optical modulation unit can be easily configured.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a diagram showing an example of gradation for divided pixels in the present invention.

FIG. 3 is a block diagram showing a system configuration of a first embodiment of the image forming apparatus.

FIG. 4 is a timing chart showing the operation of the system of FIG.

FIG. 5 is a diagram showing an example of a template.

FIG. 6 is a diagram showing an example of a correction pattern for a window that does not match the template.

FIG. 7 is a diagram showing operations of a register and a shift register in FIG.

FIG. 8 is a diagram showing an embodiment of a circuit that directly uses the output of the shift register as an optical modulation signal.

FIG. 9 is an explanatory diagram of the operation of the neuron.

FIG. 10 is a diagram showing a model of a neural network.

FIG. 11 is a diagram showing a sigmoid function.

FIG. 12 is a diagram showing a step function.

FIG. 13 is a block diagram showing a system configuration of a second embodiment of the image forming apparatus.

FIG. 14 is a diagram illustrating a conventional example of a method for improving the image quality of input image data.

FIG. 15 is a diagram showing a conventional example of image correction.

[Explanation of symbols]

 6 window data cut-out means 7 correction data output means 8 output pixel data output means 10, 40 data cut-out section 15 correction pattern output section 23, 58 register 24, 59 OR adder 25, 60 shift register

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuhiko Sato 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Tomohisa Mikami 1015, Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (56) References JP 61-214666 (JP, A) JP 1-305772 (JP, A)

Claims (10)

(57) [Claims] 1. A window data cutout means (6) for cutting out data of a pixel in a window constituted by one or more pixels on one or more lines from input image data, and a pixel data in the window. Depending on the data, the center pixel of the window and the left and right pixels adjacent to each other on the same line as the center pixel are each divided into N, and each N divided 3 ×
The correction data output means (7) for outputting the correction data for each of the N pixels as the correction data corresponding to the central pixel in the order of left, center, and right pixels, and the correction data output means (7). The central pixel corresponding correction data to be output is input, processing is performed using the processing result at the time of inputting the pixel corresponding correction data on the left side of the central pixel and the central pixel corresponding correction data, and within the window. An image forming apparatus, comprising: output pixel data output means (8) for outputting output pixel data for a pixel on the left side of the left side pixel adjacent to the central pixel. 2. The output pixel data output means (8)
Is the register to which the correction data for the central pixel is input, and the processing result at the time of inputting the correction data for the left pixel corresponding to the central pixel, which has the same capacity as the register and is already stored, is shown to the left. The pixel is shifted by the N pixel, the logical sum of the shift result and the contents of the register is held as the processing result at the time of inputting the correction data for the central pixel, and the N pixel overflowed as a result of the left shift The image forming apparatus according to claim 1, further comprising a shift register that outputs minute data as the output pixel data. 3. The correction data output means (7) is composed of a neural network and outputs correction data corresponding to the central pixel even for pixel data in a window that has not been learned. 1. The image forming apparatus according to 1. 4. The image forming apparatus according to claim 1, wherein the output pixel data output by the output pixel data output means (8) is multi-valued. 5. The image forming apparatus according to claim 1, wherein the output pixel data output by the output pixel data output means (8) takes one of two values. 6. The output pixel data output by the output pixel data output means (8) is used as it is as an optical modulation signal of an optical modulator including a laser diode. Image forming device. 7. Among the 3 × N correction data, all N data for the central pixel are used, and a part of each N correction data for each of the left and right pixels is used. The image forming apparatus according to claim 1, wherein: 8. The image forming apparatus according to claim 1, wherein the size of the window is any predetermined size. 9. The image forming apparatus according to claim 1, wherein the image forming apparatus is a printing apparatus. 10. The image forming apparatus according to claim 1, wherein the image forming apparatus is a display device.