JPH0823857B2 - Common bus control system - Google Patents

Description

DETAILED DESCRIPTION [Outline] In an information processing system in which a master controller and a plurality of slave controllers are connected by a common bus, the slave controller sends data to a master bus for data transfer to the master controller. If the corresponding address matches any of the input / output addresses of each slave control device, the master control device temporarily converts it into an address other than the input / output address, thereby preventing the slave control device from malfunctioning and The flexibility of data transfer control from the main controller to the main controller is improved.

[Industrial applications]

According to the present invention, in an information processing system in which a master control device and a plurality of slave control devices are connected by a common bus, the slave control device can transfer data to all address areas managed by the master control device via the common bus. And a common bus control system.

[Conventional technology]

FIG. 3 is a diagram showing an example of an information processing system which is the subject of the present invention, FIG. 4 is a diagram showing an example of a conventional common bus control system, and FIG. 5 is FIG. 3 and FIG. FIG. 6 is a diagram illustrating an address configuration in FIG.
It is a figure which illustrates the address area in a figure.

3 and 4, the main memory device (MM) 2 is connected to the common bus 6 via the channel control device (CHC) 3, and the plurality of input / output devices 5 are the plurality of input / output control devices (IOC). ) 4 is connected to the common bus 6.

The channel controller 3 is based on an instruction from the central controller (CC) 1 and has a direct memory access (hereinafter referred to as DMA) between the main memory 2 and the input / output controller 4 via the common bus 6. ) Perform data transfer in controlled form.

Now, the main memory 2 has a memory capacity of 1024 kilowords, and the memory address a _m has a 20-bit configuration ([00000] _{H to} [FFFF].
F] _H ) ([] _H indicates hexadecimal notation).

On the other hand, each input / output control device (IOC) 4 and input / output device 5
It is assumed that a 16-bit input / output address a _io ([0000] _{H to} [0FFF] _H ) is given to the.

In such a case, the address bus 6a of the address for the transfer in the common bus 6 consists 20 address lines, input-output address a _io for selecting among the input-output control unit 4 therefor, and lower memory addresses a _m 16 bits (base address
16 address lines for transferring a _mb )
4 address lines for transferring the upper 4 bits (extended address a _me ) of the memory address a _m.
Called ae.

When the channel control device 3 transfers data to a specific input / output control device 4 as pre-processing for DMA transfer control, the pre-processing control circuit (PC) 33 passes the address bus 6a via the cable driver 34. The input / output address a _io of the transfer target input / output control device 4 is sent to the basic address part 6ab.

In each input / output control device 4 connected to the common bus 6, the address matching circuit (AMT) 43 has an address bus 6a.
When the input / output address a _io transferred via the basic address section 6ab of the device is received via the cable receiver 41, it is collated with the input / output address a _io ′ of the own device which is given in advance, and if they match, The coincidence signal e is transmitted to the data transmission / reception circuit (DTR) 44 to prepare for data transfer.

On the other hand, DMA from the I / O controller 4 to the main memory 2
When the data transfer is started by the control system, the base address portion 6ab and extended address portions 6ae of the address bus 6a in a path which is not shown from the output control unit 4, and sends the memory address a _m of the transfer target region.

In the channel control device 3, the DMA transfer control circuit (D
MC) 32 is received through the cable receiver 31 and 31 'a memory address a _m which is transferred via the address bus 6a, but in the input-output control unit 4 connected to the common bus 6, above Similarly, the address collating circuit 43 transfers the lower 16 bits (basic address a _mb ) of the memory address a _m transferred via the basic address part 6ab of the address bus 6a.
Only the input / output address a _io is received via the cable receiver 41, and it is compared with the input / output address a _io ′ of the own device which is given in advance, and if they match, the coincidence signal e is transmitted to the data transmission / reception circuit 44. Then, it is prepared for data transfer.

Thus, among the main memory 2 address area A _m shown in FIG. 6, the lower 12 bits [000] _H to [FFF] from the input-output control unit 4 with respect to _H and a region A _io data transfer To send the memory address a _m for
Not only that, since the input / output address a _io matches the input / output address a _io ′ of its own device, the input / output control device 4 is also erroneously activated, so that the area A of the main storage device 2 from the input / output control device 4 is erroneously activated. Data transfer is prohibited for _io .

[Problems to be solved by the invention]

More As is apparent from the description, output in some conventional common bus control system, a part of the memory address a _m sent to the address bus 6a (base address a _mb) is given to the input-output control unit 4 In the area A _io of the main storage device 2 which coincides with the address a _io , the data transfer from the input / output control device 4 becomes impossible, and the data transfer from the input / output control device 4 to the main storage device 2 is restricted. After the transfer to the transferable area, the transfer is complicated in the main storage device 2, and the transfer control becomes complicated.

[Means for solving problems]

 FIG. 1 is a diagram showing the principle of the present invention.

In FIG. 1, reference numerals 100 and 200 denote a main control device and a plurality of sub control devices that form an information processing system, and 300 denotes a common bus that connects the main control device 100 and each sub control device 200. It is assumed that the second address given to each slave control device 200 is configured by a part of the bit group of the first address allocated as the memory address of the main storage device.

400 is an address determination means 400 provided in the main control device 100 according to the present invention.

Reference numeral 500 is a logic value inverting means provided in the main controller 100 according to the present invention.

[Action]

The address determination means 400 monitors whether or not a part of the bit group of the first address transmitted from the slave control device 200 via the common bus (300) is located in each second address area. To do.

The logical value inverting means 500, when the address determining means 400 detects that a part of the bit group is located in the second address area, a predetermined 1-bit logical value in the part of the bit group. Is inverted and converted to an address different from any of the second addresses.

Further, the logical value inverting means 500, when inverting the logical values of some of the bits, notifies the address receiving unit 600 that receives the address transmitted from the common bus 300 in the main control device 100.

Therefore, even if all of the first addresses assigned as memory addresses in the master control device 100 are transmitted from each slave control device 200, there is no risk of the slave control device 200 erroneously starting, and The flexibility of data transfer to main controller 100 is improved, and the transfer control is also simplified.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. Second
FIG. 1 is a diagram showing a common bus control system according to an embodiment of the present invention. The same reference numerals indicate the same objects throughout the drawings. The target information processing system is as shown in FIG. 3, and the address configuration and address area are as shown in FIGS. 5 and 6, respectively.

In FIG. 2, a channel control device (CHC) 3 is shown as the main control device 100, and an input / output control device (IOC) 4 is shown as the slave control device 200. Further, in the channel control device 3, the address determination means 400 is shown. Address determination circuit (AD
T) 35, and gates 36 and 37 are provided as the logical value inversion means 500.

In FIG. 2, when the channel controller 3 transfers data to a specific input / output controller 4, the address bus is transferred from the preprocessing control circuit (PC) 33 through the gate 37 and the cable driver 34 as described above. 6a basic address part 6ab
The input / output address a _io of the transfer target input / output control device 4 to the address collating circuit (AM
T) 43 collates the input / output address a _io transferred via the basic address part 6ab of the address bus 6a with the input / output address a _io ′ of its own device, and if they match, the coincidence signal e is sent to the data transmitting / receiving circuit. (DTR) 44, and prepares for data transfer under DMA control.

On the other hand, when the data transfer by the DMA control method is started from the input / output control device 4 to the main memory device (MM) 2, the basic address part 6ab of the address bus 6a and the extension are provided from the input / output control device 4 through a route not shown. the address unit 6ae, sends a memory address a _m of the transfer target region.

In the channel control device 3, the DMA transfer control circuit (D
MC) 32 receives the memory address a _m transferred via the address bus 6a via the cable receivers 31 and 31 ′, and the basic address a _mb transmitted via the basic address part 6ab is the same. It is also transmitted to the address determination circuit 35 of the input / output control device 4 connected to the bus 6. DM
The A transfer control circuit 32 transmits DM to the address determination circuit 35 while data transfer by the DMA control method is being performed.
A The in-transmission display signal t is set to logic "1".

The address determination circuit 35 receives the received basic address a
The _mb, monitors whether or not located in the region of the input and output addresses a _io granted to the input-output control unit 4 ([0000] _H to [0FFF] _H), regions of the input and output addresses a _io If it is located inside, the judgment signal d transmitted to the gate 36 is set to logic "1".
And the inhibit signal i transmitted to the DMA transfer control circuit 32 is set to logic "1". When the DMA control circuit 32 of the channel controller 3 is activated by a request from the input / output controller 4, the address transmission timing signal s transmitted from the DMA transfer controller 32 to the gate 36 is set to logic "1". Therefore, the logic value inversion signal r output from the gate 36 is set to logic "1", and is sent to the uppermost address line of the basic address portion 6ab via the gate 37 and the cable driver 34.

As a result, among the memory addresses a _m being sent from the input / output control device 4 to the address bus 6a, the basic address a _mb transmitted to another input / output control device 4 via the basic address portion 6ab is [0000 ] will be converted from _H to [0FFF] _H [8000] in _H to [8FFF] _H, the address matching circuit 43 in any of the input-output control unit 4 does not output a coincidence signal e, data transmission and reception circuit 44 There is no fear of accidentally starting up.

At the same time, the basic address a _mb of the memory address a _m transmitted to the DMA transfer control circuit 32 is also [0000] _{H to} [0FFF].
Converted from _H to [8000] _{H to} [8FFF] _H , but DMA
Transfer control circuit 32 when receiving the inhibiting signal i from the address determination circuit 35, the base address a _mb of memory addresses a _m received by the [0000] _H to [0FFF] from _H [8000] _H
To [8FFF] _H , the original basic address a _mb [0000] _{H to} [0FFF] _H is restored and data transfer control is executed.

When the data transfer is completed, the DMA transfer control circuit 32 changes the DMA transfer in-progress signal t transmitted to the address determination circuit 35 from the logic "1" to the logic "0" and sets the address transmission timing signal s to the logic "0". Set to.

When the DMA transfer in-progress signal t transmitted from the DMA transfer control circuit 32 changes to logic “0”, the address determination circuit 35
The judgment signal d being sent to the gate 36 is changed from logic "1" to logic "0".
Change to

As a result, the logic value inversion signal r sent from the gate 36 to the most significant address line of the basic address portion 6ab is also returned from the logic "1" to the logic "0".

As is apparent from the above description, according to this embodiment, the input / output control device 4 that transfers data to the main storage device 2 is used.
The basic address a _mb of the memory address a _m sent by the device is the input / output address a _io ′ given to the input / output control device 4.
If it matches with, the channel controller 3 converts it to an address other than the input / output address a _io and transmits it to another input / output controller 4, so that the input / output controller 4 is prevented from malfunctioning.

Note the channel control unit 3 itself, the memory address a _m of the input-output control unit 4 is sent, the 1 bit changed DM
Since the data is restored and used by the A control circuit 32, data transfer to the area A _io is executed without error.

It is to be noted that FIGS. 2, 3, 5, and 6 are merely examples of the present invention until now. For example, the logical value inversion signal r is sent to the uppermost address line of the basic address portion 6ab. The present invention is not limited to the above, and many other modifications can be considered, but in any case, the effect of the present invention does not change. Further, the information processing system, the address configuration, and the address area which are the objects of the present invention are not limited to those shown in the figure, and many other modifications are considered, but in any case, the effect of the present invention is does not change.

〔The invention's effect〕

As described above, according to the present invention, in the information processing system, even if all the first addresses assigned as memory addresses in the master control device are transmitted from each slave control device, the slave control device may malfunction. , The flexibility of data transfer from the slave control device to the master control device is improved, and the transfer control is simplified.

[Brief description of drawings]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing a common bus control system according to an embodiment of the present invention, and FIG. 3 is a diagram showing an example of an information processing system which is the object of the present invention. FIG. 4 is a diagram showing an example of a conventional common bus control system,
FIG. 5 is a diagram illustrating an address configuration in FIGS. 3 and 4, and FIG. 6 is a diagram illustrating an address area in FIG. In the figure, 1 is a central controller (CC), 2 is a main memory (MM), 3 is a channel controller (CHC), 4 is an input / output controller (IOC), 5 is an input / output device, and 6 and 300 are Common bus, 6a is address bus, 6ab is basic address part, 6ae is extended address part, 6c is control signal bus, 31, 31 ', 41 and
42 is a cable receiver, 32 is a DMA transfer control circuit (DMC),
33 is a pre-processing control circuit (PC), 34 is a cable driver, 35
Is an address decision circuit (ADT), 36 and 37 are gates, 43
Is an address matching circuit (AMT), 44 is a data transmission / reception circuit (D
TR), 100 is a master controller, and 200 is a slave controller.

Claims (1)

[Claims] 1. A main control unit (100) and a plurality of slave control units (200) are connected by a common bus (300), and are assigned by the main control unit (100) as a memory address of a main storage unit. In the information processing system that configures a second address given to each slave control device (200) by a part of a bit group of the first address, the slave control device is provided in the master control device (100). Address judging means for monitoring whether the partial bit group of the first address transmitted from the device (200) via the common bus (300) is located in each of the second address areas ( 400), and when the address determination means (400) detects that the part of the bit group is located in the second address area, a predetermined 1 bit of the part of the bit group is detected. Invert the logical value to determine which of the second addresses Converts to a different address also, the main control unit to that effect (10
And a logical value inverting means (500) for notifying an address receiving unit (600) that receives an address transmitted from the common bus (300) in (0).