JPH08237255A - Cell switch, switch network using the switch and atm exchange network - Google Patents

Abstract

PURPOSE: To set the arbitration of the address collision of cells in a batcher banyan network or the like to be efficient with simple constitution and to allow exchanging the cell of high performance with high throughput. CONSTITUTION: The cell switch of two input/two output deciding the output destination of a cell in response to the size relation of the destination bit string of the inputted cells is provided with a preferential cell selection means (address arithmetic circuit 33) selecting one side input cell is a preferential cell based on a priority bit which is previously given to the respective input cells which address-collide with each other at the time of occurrence of address collision of the inputted cells and preferential port output means (control register 35 and multiplexers 36a and 36b) outputting the preferential cell to a preferential port 30-side.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a 2-input 2-output cell switch used in an ATM switch or the like, and in particular, it efficiently detects and arbitrates collisions due to overlapping destinations of simultaneously input cells, and has high throughput. The present invention relates to a cell switch suitable for enabling the ATM switching, a switch network using the same, and an ATM switching network.

[0002]

2. Description of the Related Art ATM exchange technology is described in, for example, "Nikkei Communication Separate Volume ISDN Handbook" (198).
8 years, published by Nikkei BP), pp. 168 to 177, it is a basic technology for efficiently processing a large amount of multimedia information. Seems to be widely used in infrastructure. As the information society advances, the information processing technology integrated with communication becomes more sophisticated, and as a result, the demand for ATM exchange increases.

The Batcher-Banyan network shown in FIG. 4 is widely used as a technique for realizing high-throughput ATM switching. This Batcher Banyan network has 2 inputs and 2
It is a type of space-division type switch network in which output cell switches are connected in multiple stages, and has the feature of high throughput because it can process multiple input packets in parallel.

FIG. 4 is a block diagram showing a configuration example of a conventional Batcher-Banyan network. This example shows a configuration example of an 8-input Batcher-Banyan network, and the first half portion (left side in the figure) of FIG. 4, that is, the S (2) switch 5
0, the part consisting of the S (4) switch network 51 and the S (8) switch network 55 is the batcher (sorter) network, and the latter half (right side in the figure) is the Banyan network 22 (Ω in the figure).
(Described as (8)). The banyan network 22 is a self-routing network whose output position is determined only by the cell destination, and is configured by connecting multiple Ω (2) switches 20 that determine the route of the cell according to the destination bit of the cell. .

In the case of the Banyan network 22, there is a possibility of cell collision (a plurality of cells having different destinations, which are simultaneously input, try to flow on the same route in the Banyan network) depending on the input pattern. To avoid this cell collision, a batcher net is provided. That is, in the batcher network, the cells are rearranged (sorted) so that the cells are arranged in the order of destination size. This batcher net is 2
It is configured by connecting S (2) switches 50, that is, cell switches whose stages are determined depending on the size relation of the cell destinations in multiple stages. In the S (2) switch 50, the destinations of the two input cells are compared, and the route is set so that the magnitude relationship of the values and the direction of the arrow match.

In the S (4) switch network 51 and the S (8) switch network 55, the S (2) switch 50 is combined to
An algorithm called bitonic sort mixes two sorted columns of length n to produce a sorted column of length 2n. Here, S
(4) Switch network 51 and S (8) switch network 5
5 produces sort sequences of lengths 4 and 8, respectively. The S (2) switch 50 and the Ω (2) switch 20 are
The difference is whether the determination criterion of the route determination is performed by the destination comparison or the destination bit (deterministically), and both basic structures are as shown in FIG.

FIG. 5 is a block diagram showing a configuration example of a conventional cell switch. This example shows a configuration example of the S (2) switch 50 in FIG. 4, and in FIG. 5, the input cells 40c and 40d composed of the cell headers 45c and 45d and the cell data 46c and 46d are the data registers 3 respectively.
4c and 34d, respectively, and at the same time, the address operation circuit 33a performs the operation on the route in the cell header 45.
c, 45d based on the cell destination bits. The result of the operation of the address operation circuit 33a is stored in the control register 35a, and the flow of cells is switched by the multiplexers 36c and 36d according to the value. S (2) of FIG.
In the switch 50, the cell path is determined by the comparison operation of the cell destinations, while the Ω (2) switch 20 in FIG.
Then, the route is determined by the value of the destination bit (one of the bits) itself.

In the Batcher Banyan network shown in FIG. 4,
It is known that cell collision does not occur in the network unless cells of the same destination are input at the same time. This is because the bitonic sequence (bitonic sequence), which is a condition for the cells not to collide in the Banyan network, is changed to the batcher sorter (S (2) switch 50, S (4) switch network 51, S (8) in FIG. 4). This is because the switch network 55) is generated. Although omitted here, details thereof are described in, for example, IEEE Trans. Commun. Vol. 36, No. 10, pp. 1175-1.
178 etc.

However, even in such a batcher-banyan network, when cells input to the network at the same time include cells of the same destination, cell collision (destination collision) occurs and arbitration is required. . When such a cell destination collision occurs, a cell to be prioritized is selected among the cells having the collision, and the processing is delayed for the cells not selected. In such a case, some cells are invalidated in the middle of the batcher network, which disturbs the permutation in the batcher sorter, which hinders normal operation of the sorter and guarantees no cell collision in the Banyan network. Disappear. Moreover, the overlap of cell destinations cannot be completely removed only by the batcher network. In conclusion, when there is a possibility that cells with the same destination will be input, the Batcher Banyan network cannot avoid cell collision.

[0010]

The problem to be solved is that the prior art cannot efficiently avoid the cell destination collision in the Batcher Banyan network or the like. An object of the present invention is to solve these problems of the prior art, efficiently arbitrate collisions by cells of the same destination with a simple configuration, and a cell switch that enables high-performance cell switching with high throughput, and It is to provide the switch network and ATM switching network used.

[0011]

In order to achieve the above object, a cell switch according to the present invention, a switch network using the same, and an ATM switching network (1) output a cell according to a destination bit string of an input cell. A two-input, two-output cell switch for determining the destination, and when a destination collision of an input cell occurs, one of the input cells is determined based on a priority bit given to each of the input cells having the destination collision. Priority cell selection means (address arithmetic circuit 33) for selecting the priority cell and priority port output means (control register 35, multiplexers 36a, 36b) for outputting the priority cell to a predetermined priority port 30 side are provided. It is characterized by (2) In the cell switch according to (1), the cell has a valid bit indicating the validity of the cell in a higher bit of a destination bit string of the cell, and the priority cell selection means (address calculation). Circuit 33)
Changes the valid bit of the unselected cell to an invalid bit and determines the output destination of the input cell based on the effective destination bit string consisting of either the invalid bit or the valid bit and the destination bit string. It is characterized by performing. Also, (3) above (1) or (2)
The cell switch according to any one of items 1 to 5 is characterized by comprising a superconducting device. Further, (4) a switch network for rearranging cells in the order of magnitude relation of cell destinations, which is configured by connecting the cell switches according to any one of (1) to (3) above in multiple stages and simultaneously input. It is characterized by performing cell collision arbitration by overlapping cell destinations.
(5) In the switch network according to (4) above,
It is characterized in that the cell switches are connected in multiple stages so as to form a bitonic string in which cell-free collision in the next-stage Banyan network is guaranteed. (6) An ATM switching network, which comprises the cell switch according to any one of (1) to (5) above, and the priority port of this cell switch is the effective cell of the destination collision occurrence. It is characterized by being fixed as a route.

[0012]

In the present invention, the cell switch has a priority port, and when a cell collision is detected, the cell to be prioritized is selected and output to the priority port. In this way, the priority port can determine the route of a valid cell when a collision occurs, so that it is possible to effectively eliminate the duplication of cell destinations and effectively prevent the collision of cells in the Banyan network. .
In particular, if the effective destination of a cell that contains valid bits in the upper part of the destination bit string is used, invalid cells can be selected by this effective destination comparison operation, so duplication of cell destinations can be eliminated and banyan networks can be used. Cell collision prevention can be handled more efficiently. Furthermore, in a sort network (switch network) in which cell switches with such priority ports are connected in multiple stages, duplicate cell destinations can be removed with a calculation amount of log2n (n is the number of inputs), but all duplicates are detected. In order to do so, the calculation amount of log2n is required, and thus the duplication detection by the sort network (switch network) is one of the methods with the smallest calculation amount. In addition, if the cell switch of the present invention is used in the construction of a so-called bitonic sorter, an input string (bitnick that guarantees cell-free collision in the Banyan network is used with a smaller number of stages than when sorting the whole). Columns) can be formed. Furthermore, by using a superconducting device, which is characterized by ultra-high-speed operation, in the cell switch of the present invention, it becomes
A TM switch can be constructed.

[0013]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the configuration of the cell switch of the present invention according to the present invention. In FIG. 1, 40a and 40b are input cells composed of a cell header 45 and cell data 46, 41a and 41b are output cells, and the cell header 45 is an input cell 40a, 40b.
Active bits 42a, 42 indicating validity / invalidity of
b, destination bits 43a and 43b indicating the destination of the input cells 40a and 40b, and priority bits 44a and 44b according to the present invention indicating the priority of the input cells 40a and 40b. In this embodiment, the active bit 42a,
42b and destination bits 43a and 43b are collectively treated as effective destinations 47a and 47b.

Further, in FIG. 1, 31 is a cell synchronization signal line for controlling the operation timing of the cell switch, 33 is a route operation based on each information in the cell header 45 to determine the output destination of the input cells 40a and 40b. An address arithmetic circuit for performing processing as the priority cell selecting means of the present invention, 32 is a collision detection signal line for outputting the detection result of the cell destination overlapping collision by the address arithmetic circuit 33, 34a,
34b is a data register that stores the input cells 40a and 40b, 35 is a control register that stores the calculation result of the address calculation circuit 33, and 36a and 36b are one of the data registers 34a and 34b based on the stored contents of the control register 35. It is a multiplexer that selects and outputs the stored input cells 40a and 40b. An output port 30 on the multiplexer 36b side is defined as a priority port of the present invention.

When the input cells 40a and 40b are input,
The address calculation circuit 33 uses the destination bit 43 in the cell headers 45a and 45b of the input cells 40a and 40b, respectively.
The comparison operation of a and 43b is performed, and the operation result is output to the control register 35. The control register 35 includes a multiplexer 36a based on the calculation result of the address calculation circuit 33,
The multiplexer 36a, 36b controls 36b to select one of the input cells 40a, 40b and output it as the output cell 41a, 41b. In this way, the cell switch determines the path of the cell by comparing the destination bits of the cell.

At this time, if the destinations of the input cells 40a and 40b are the same, the address calculation circuit 33 detects the occurrence of cell collision due to the overlapping of the destinations based on the calculation result. In this embodiment, the priority bits 44a and 44b are given to the input cells 40a and 40b, and when such a destination collision occurs, the address arithmetic circuit 33
Based on these priority bits 44a and 44b, the input cell 4
Either 0a or 40b is selected as the priority cell. Then, the active bits 42a and 42b of the input cell not selected as the priority cell are invalidated.

In this embodiment, the active bits 42a,
Since 42b is provided at the most significant position of the destination bits 43a, 43b, the effective destinations 47a, 4a of the invalidated cells
7b is always smaller than that of the effective cell. Then, by comparing the effective destinations 47a and 47b, the priority cell is always output from the priority port 30. Thus, in this embodiment, even if the destinations of the input cells 40a and 40b are the same, the cell to be prioritized is always output from the priority port 30 based on the size relationship between the effective destinations 47a and 47b. As a result, in the cell switch at the next stage, the effective destination 47
The comparison operation of a and 47b makes it possible to definitely output the priority cell to the priority port.

A switch network using the cell switch having such a configuration will be described below with reference to FIGS. 2 and 3.
FIG. 2 is an explanatory diagram showing a first embodiment of the configuration of the switch network according to the present invention using the cell switch in FIG. The embodiment shown in FIG. 2 shows a cell switching network with a 4-input collision arbitration function, and the Ω (2) switch 20 is shown in FIG.
It is the same as the conventional one shown in (4), and the route of the cell is determined according to the destination bit of the cell. Further, the S (2) switch 10 is the cell switch in FIG. 1 and has the priority port 30 which is a big difference from the conventional one shown in FIG. By comparison, the cell with the larger value is output in the direction of the arrow.

The S (2) switch 10 of this embodiment is shown in FIG.
As described above, since the destination comparison is performed on the effective destination including the effective bit, it is possible to select the invalid cell and the effective cell only by comparing the sizes of the effective destinations. Also,
The second half (right side of the figure) (Ω4) is 4 Ω (2)
The switch 20 constitutes a 4-input Banyan network.
Before a cell is input to this Ω (4) Banyan network 21,
The first half (the left side in the figure) (S (2) switch network 10,
And S (4) switch network 11), cell address duplication is eliminated, and cells are rearranged according to the size relation of the destinations so that cell permutation does not occur in Ω (4) Banyan network 21 at the subsequent stage. Generate (bitnick sequence). The structure of the first half is similar to the conventional 4-input batcher network (S (4) switch network 11a) shown in FIG. 4, but the cell switch (S (2) switch 10) shown in FIG. With the configuration, unlike the conventional batcher network, it is possible to arbitrate the collision due to the overlapping of destinations. The principle will be briefly described below.

First, when there is no overlap in cell destinations, this first half part operates in the same manner as a 4-input batcher sorter. In this case, at the final stage of the S (4) switch network 11,
The cells are output in order of destination size (without duplication). This output string can be thought of as a special form of the bitonic string,
Guaranteed to cross the Banyan net without collision.
Next, consider the case where the input (valid) cell destinations overlap. When a cell collision is detected by the S (2) switch 10 in the first stage, the cell is selected in the S (2) switch 10, the valid cell is the priority port 30, and the invalidated cell is another. Output to one port.

As described with reference to FIG. 1, the priority port 30 at the first stage matches the output port of a cell having a large effective destination. Therefore, even if collision mediation is performed,
By the first stage, two permutations (of length 2) sorted in the order of destination size are generated. These two permutations are S
(4) Two bitonic strings are generated by mixing at the first stage of the switch network 11. At that time, if there is no change in the effective destination due to the collision detection at the first stage of the S (4) switch network 11, the effective destination of the cell input to the upper half of the latter stage of the S (4) switch network 11 is the lower half of the lower half. It will be larger than this (this is indicated by the normal byteonic sort algorithm).

Further, considering that the priority port 30 at the first stage of the S (4) switch network 11 matches the port to which the cell having a large effective destination is output, at the first stage of the S (4) switch network 11. Even if the effective destination is changed due to the collision detection, the valid cell is input to the upper half of the latter stage of the S (4) switch network 11. After all, the effective destination of the cell input to the upper half of the latter stage of the S (4) switch network 11 is always larger than that of the lower half. Therefore, S
(4) If there is no change in the effective destination due to the collision detection in the latter stage of the switch network 11, the output will be arranged in the order of magnitude of the effective destination.

When the effective destination is changed by the collision detection in the latter stage of the S (4) switch network 11, the invalidated cells are designated by the priority port 30 and the S (4) switch network 11 is changed. It is output to both ends of the latter stage. This is S
(4) Do not break the bitonic nature of the output string. That is,
The first half of the circuit network can detect and arbitrate collisions due to overlapping cell destinations and generate a bitonic sequence even when the effective destination is changed. further,
Although detailed description is omitted here, all the cell destination duplications can be eliminated by this network.

After all, the S (2) switch 10 and the S (4) switch network 11 eliminate all the duplications with respect to the input of all cells including the duplication of the destination, and the Ω (4) Banyan network 21. It is possible to guarantee no collision in the. This may include invalid cells in the first entered cells. As described above, by providing the priority port 30 to the S (2) switch 10, a normal batcher
With a simple configuration similar to that of the sorter, it is possible to arbitrate the collision caused by the duplicate destination.

FIG. 3 is an explanatory diagram showing a second embodiment of the configuration of the switch network according to the present invention using the cell switch in FIG. FIG. 3 shows a cell switching network for eight-input collision arbitration. This network eliminates all duplicate cell destinations, and the latter stage (not shown)
In order to guarantee no collision in the Ω (8) Banyan network, a bitonic sequence is generated. The operation will be described below.

First, eight inputs are divided into two four inputs, and the first stage (S (2) switch 10) to the fifth stage (S) in the figure are divided.
(4) The latter part of the switch 12) removes cell destination duplication and rearranges in the order of destination size for each group of 4 inputs. Similar to the first embodiment described with reference to FIG. 2, the first to third stages (S (4) switch 11
In the latter part of a), it is possible to remove all the destination duplications within the group of four inputs. Here, in this third stage,
Since the priority port 30 and the output port of a cell having a large effective destination match (unlike the third row in FIG. 2), two bytenic sequences of length 4 (without destination duplication) are formed.

By performing the conventional bytenick sort on the 4th stage and the 5th stage (S (4) switch 12) respectively, a bytenick sequence of length 8 (sort sequence 2 of length 4) One) is generated. Destination duplication within the group of 4 inputs has been removed up to the 3rd stage, so each S (2) switch in the 4th and 5th stages is a normal (conventional) switch with no priority port. Is used.

At the sixth stage, the bitonic sequences of length 8 are mixed and the collision detection between the above two groups is performed. Even if a collision is detected at that time, the priority port processing causes The effective destination of the cell input to the upper half of the seventh row is larger than that of the lower half. Therefore, the cells input in the upper half of the seventh row and those in the lower half do not collide. Therefore, in the processing from the seventh step onward, the processing from the first step to the fifth step may be performed for each of the upper half and the lower half. As a result, it is possible to eliminate the destination duplication for all the first input cells and generate the effective destination bytenick string. Therefore, the output of this network does not collide with the 8-input Banyan network (not shown) in the subsequent stage.

As described above with reference to FIGS. 1 to 3, in the cell switch of this embodiment, the switch network using the same, and the ATM network, the cell switch detects a cell destination collision and gives priority to it. Select the cell to be transmitted and send it to the fixed priority port. Further, a valid bit indicating the validity of the cell is provided in the most significant bit of the destination bit indicating the destination of the cell, and is used for arbitration at the time of collision and route determination of the cell after collision. Then, the cell switches are connected in multiple stages, and a sorting network (switch network) for rearranging cells according to the size relation of cell destinations in order to detect and arbitrate collisions due to overlapping destinations of simultaneously input cells, for example, a byte Nick Sorter and ATM switching network are constructed.

As a result, it is possible to guarantee collision-free in the network for all input combinations of cell destinations, and to arbitrate cell collisions due to overlapping destinations, which cannot be avoided by the conventional Batcher Banyan network. The cell switching network with high throughput can be realized with a simple configuration. In addition, by using a superconducting device for the cell switch, it is possible to perform ultra-high-speed data processing and further increase the speed and bandwidth of data exchange such as ATM exchange. The present invention is not limited to the embodiment described with reference to FIGS. 1 to 3, and various modifications can be made without departing from the scope of the invention.

[0031]

According to the present invention, it is possible to efficiently arbitrate a cell destination collision in a Batcher-Banyan network or the like with a simple structure, and to perform high-performance cell switching with high throughput.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the configuration of a cell switch according to the present invention.

2 is an explanatory diagram showing a first embodiment of the configuration of a switch network according to the present invention using the cell switch in FIG. 1. FIG.

FIG. 3 is an explanatory view showing a second embodiment of the configuration of the switch network according to the present invention using the cell switch in FIG.

FIG. 4 is a block diagram showing a configuration example of a conventional Batcher Banyan network.

FIG. 5 is a block diagram showing a configuration example of a conventional cell switch.

[Explanation of symbols]

10: S (2) switch, 11, 11a to 14: S
(4) Switch network, 20: Ω (2) Switch, 21: Ω
(4) Switch network, 22: Ω (8) Switch network, 30:
Priority port, 31, 31a: Cell synchronization signal line, 32, 3
2a: collision detection signal line, 33, 33a: address arithmetic circuit, 34a to 34d: data register, 35, 35a:
Control register, 36a-36d: Multiplexer, 40
a to 40d: input cell, 41a to 41d: output cell, 4
2a, 42b: active bit, 43a, 43b: destination bit, 44a, 44b: priority bit, 45a-4
5d: cell header, 46a to 46d: cell data, 47
a, 47b: effective destination, 50: S (2) switch, 5
1: S (4) switch network, 55: S (8) switch network

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshikazu Nishino 1-280, Higashikoigokubo, Kokubunji, Tokyo Metropolitan Research Center, Hitachi, Ltd.

Claims (6)

[Claims] 1. A two-input two-output cell switch for determining an output destination of a cell according to a destination bit string of the input cell, when a destination collision of the input cell occurs, each input cell that has the destination collision Priority cell selection means for selecting one of the input cells as a priority cell based on a priority bit given in advance, and priority port output means for outputting the priority cell to a predetermined priority port side are provided. A cell switch characterized in that. 2. The cell switch according to claim 1, wherein the cell has a valid bit indicating validity of the cell,
The higher priority bit of the destination bit string of the cell, the priority cell selecting means changes the valid bit of the cell not selected to an invalid bit, and either the invalid bit or the valid bit and the destination bit string. A cell switch which determines the output destination of the input cell based on an effective destination bit string consisting of 3. The cell switch according to claim 1, wherein the cell switch comprises a superconducting device. 4. A switch network for rearranging cells in the order of magnitude relation of cell destinations, wherein the cell switches according to any one of claims 1 to 3 are connected in multiple stages, and cells are input at the same time. A switch network characterized by performing cell collision arbitration by duplication of destinations. 5. The switch network according to claim 4,
A switch network in which the above-mentioned cell switches are connected in multiple stages so as to form a bitonic sequence in which cell-free collision is guaranteed in the next-stage Banyan network. 6. A switching network for performing ATM switching, comprising the cell switch according to any one of claims 1 to 5, wherein a priority port of the cell switch is a route of a valid cell when a destination collision occurs. An ATM switching network characterized by the following.