JP3002659B2 - Data transfer network - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer network for transferring packet data.

[0002]

2. Description of the Related Art In recent years, with the advance of LSI technology, a large number of high-speed and large-capacity processors are connected and parallel processing is performed.
It is becoming possible to realize high-performance parallel computer systems. In such a system, it is necessary to exchange a large amount of data between processors, between a processor and a memory, and a data transfer network for connecting processors as shown in FIG. 3, for example. For example, Kurokawa et al., Information Processing Vol. 27, (1986), N.
o.9, Special Feature “Parallel Processing Technology” 3,1, Combination Method, p
p. The details are described in 1005 to 1021.

As a data transfer network, those using a crossbar switch and those using a multistage switch are known. In this case, a packet in which data to be transferred is added with a destination address is transmitted to the data transfer network. The packet is sent out, and a bus is sequentially created in the network for the packet.

[0004]

When the data transfer network is composed of crossbar switches, the hardware becomes enormous and it is difficult to realize the data transfer network. Therefore, it is practical to use a multi-stage switch system. In the above packet, the data length is usually several tens of bits or more,
Also, the transfer destination address needs more than ten and several bits when using several thousand or more processors. It goes without saying that it is desirable to transfer all bits of the packet in parallel for high-speed packet transfer, but if all bits of the packet can be sent in parallel, the number of signal lines and switches becomes enormous. , The bit width d of the data transfer path
Must be relatively small (at most about 10 bits or less). Therefore, from a practical viewpoint, as shown in FIG. 4, each packet is divided into a plurality of sub-packets each having a plurality of bits d, all pits are transferred in parallel in each sub-packet, and different sub-packets are sequentially transferred. We need a way to transfer it. In this case, not only the data but also the transfer destination address needs to be divided into at least two or more partial addresses.

Each switch of the multistage switch constituting the data transfer network determines a destination of an input packet from a transfer destination address in the packet, performs appropriate switching, and sends the packet to an appropriate output terminal. Output. Even if the data and the transfer destination address are divided as described above, each switch can perform this switching by waiting for the arrival of all the partial addresses. Once switching is performed, data subpackets sequentially transmitted after the transfer destination address can be transmitted to the next-stage switch in a pipeline manner. However, if the switching of each switch is performed after all the partial addresses arrive, there is a problem that the switching start time is greatly delayed as compared with the case where all the pits of the transfer destination address are transferred in parallel.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data transfer network which does not delay switching start time of each switch very much even when a transfer destination address is divided into a plurality of partial addresses.

[0007]

Therefore, according to the present invention, the partial addresses necessary for a switch to determine the next switch to which a packet should be transmitted are determined by a plurality of partial addresses each including the partial address supplied to the switch. If it is included in the first of the sub-packets, it has configured the switch to start switching when the first packet arrives. Even more preferably, if the first subpacket does not include the partial address required for the next-stage switch to switch, the preceding switch switches the partial address so that the partial address is included in the first subpacket. Can be exchanged between subpackets.

[0008]

According to the present invention, by adopting the above-described configuration, it is possible to reduce the waiting time required for the switches constituting the data transfer network to start switching, thereby realizing a high-speed data transfer network.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing an embodiment of the present invention, FIG. 5 shows an example of a data transfer network which uses the divided address but which does not attempt to speed up switching according to the present invention. Will be explained.

FIG. 5 shows a data transfer network (hereinafter, simply referred to as a network) having a multistage switch configuration.
Suppose we have 16 inputs / 16 outputs.

In FIG. 5, S00-S37 are 2-input / 2-output switches constituting a network, and the numbers in parentheses above each switch indicate the number.

0 'to 15' are input ports of the network, and 0 "to 15" are output ports of the network.
The output ports 0 "to 15" express their addresses in binary numbers as (0000) to (1111). FIG. 6 shows an example of the configuration of a switch used in the network of FIG. 5 for dividing and transferring a transfer destination address in the multistage switch. In FIG. 6, I1 and I2 are input ports of the switch and O1 and O2. an output port, E1 is the output port selection circuit, Q _1, Q ₂ output queue, Q _3, Q ₄ output queues, L1, L2, L3, L4 is for storing partial address included in the sub-packet Register, S
Reference numerals 1 and 2 denote selectors, MS1 is a memory storing information and procedures necessary for switch operation, and P1 is a switch controller for controlling switch operation.

Here, for simplicity, it is assumed that a packet provided to the network has a transfer destination address of 4 pits, data of 4 bits, and a pit width of a data transfer path of 2 bits, as shown in FIG. It is assumed that the transfer destination address is divided into partial addresses A ₁ and A ₂ and divided into data D ₁ and D ₂ . It is also assumed that this packet is transferred from the input port 1 'to the output port 11 "as indicated by the bold line in FIG.
Since 1), A ₁ and A ₂ represent bit strings of 10 and 11, respectively. The operation of the data transfer network of FIGS. 5 and 6 at this time will be described with reference to FIG. As shown in FIG.

[00] It is assumed that the partial addresses A ₁ and A ₂ and the partial data D ₁ and D ₂ are sequentially input to the input port I2 of the coordinate switch S00. At this time, the switch S00, and stored in the first, second partial address A _1, A _2, respectively register L3, L4, also partial address A _1, A ₂
The partial data D ₁ and D ₂ are sequentially stored in the input queue. Register L3, L4 output of C3, C4 (equivalent to partial address A _1, A ₂ is the current case) are respectively provided to the switch controller P1, switch controller P1
Indicates that the partial addresses A ₁ and A ₂ correspond to the registers L 1 and L ₂ respectively.
When set to 2, the control information M1 and M2 of the selectors S1 and S2 in the output port selection circuit E1 are created in response to the contents of the in-switch memory MS1 and the outputs C3 and C4 of the registers L3 and L4. give. More specifically, in this case, the switch controller P1
The determination bit position information J1 indicating that the first bit of the first sub-packet is a determination bit, as shown in FIG.
The determination bits are taken out of a 4-bit address consisting of outputs C3 (= A1) and C4 (= A2). In this case, since this value is 1, control information M for generating a path from the input port I2 to the output port O2 for the selector S2 in E1 based on this value.
Give 2. Thus, the sub-packets are sequentially output from the output port O2 via the output queue Q3 to the next-stage switch S.
Sent to 14

In FIG. 5, the output port O in the switch S00
2 is selected, the above packet is transmitted to the switch S14.
7, determination bit position information J1 that the determination bit position is the second bit of the first subpacket is given from the memory MS1 in the switch, as shown in FIG.
A path from the input port I1 of the switch S14 to the output port O1 is generated with the determination bit (0 in this case), and the packet is sent to the switch S24. Hereinafter, the switch S24
Is a determination bit (1 in this case), and the switch S35
Is the second bit of the second subpacket, and by the same processing, the packet is output to the output port 1 of the network.
1 ".

FIG. 8 is a timing chart of the above operation. In FIG. 8, each of the above sub-packets is sequentially given to the input port at every time T. It is also assumed that the switch controller P1, the selectors S1, S2, etc. in each switch operate at a sufficiently high speed. As can be seen from FIG.
In the data transfer network of FIG.
Switching is started after the arrival of two divided addresses. For this reason, in addition to the transfer time 4T for four subpackets, a time 2T × 4 = 8T for waiting for the arrival of two divided addresses at each switch is added, so that a network transfer time of 12T is required.

Next, an embodiment of the present invention will be described.

FIG. 9 shows a data transfer network comprising a multistage switch according to the present invention. In the configuration, the difference from FIG. 5 is that switches S00 'to S37' wait for the arrival of all sub-packets including the transfer destination address. Switching after the arrival of the first sub-packet, determining the output port connected to the next-stage switch to which the packet is to be transmitted, and starting transmission of the sub-packet; Steps S10 'to S17' are such that, for a plurality of subpackets including the divided transfer destination address, the divided addresses are exchanged between the first subpacket and the second subpacket. In the example of Network described with reference to FIGS. 5 and 6, in the switches S00 to S07 in the first stage and the switches S10 to S17 in the second stage, each switch determines the next-stage switch to which a packet is to be transmitted. The required partial address is the first partial address A1 in the first sub-packet of the packet to be input to each of them.
In the switches S20 to S37 of the stage,
This is the second partial address A2 in the subpacket. However, as shown in FIG. 9, the second-stage switches S10 'to S1
When the sub-packet sequence input to 7 'is output, the partial addresses A ₁ and A ₂ are set such that the first sub-packet includes the second partial address A2 and the second sub-packet includes the first partial address A _1. Are replaced by the second-stage switches S10 'to S17', so that the next sub-switch includes a partial address required for switching in the first subpacket.

FIG. 1 shows a second stage switch S10 'of FIG.
6 to S17 ', and FIG.
The difference is that the output C1 of the registers L1 and L2 is selected so that the input port I1 or I2 first selects the partial address stored in the registers L1, L2 or L3, L4 to be transmitted first. , C2, and the selectors S5, which select the outputs C3, C4 of the registers L3, L4, and select the partial address string output from the selector S3 or S5 prior to the partial data stored in the input queue Q1 or Q2. And the selector S4 or S6 for providing the output port selection circuit E1 and the switching controller P2 in parallel with the arrival of the first subpacket of the packet at the input port I1 or I2. The operation starts in response to the packet start signal PSTR1 or PSTR2 given to The point at which the operation ends in response to the packet end signal PEND1 or PEND2 provided in synchronization with the end of the packet arriving at the input port I1 or I2, and the determination bit position information J2 provided from the memory MS2 are always at the head. Point to any bit of the partial address in the subpacket of the sub-packet.

The first stage switches S00 'to S0
7 'and third and fourth stage switches S20' to S37 '
As shown in FIG. 2, registers L1 and L3 for storing subpads and selectors S3 to S6 are omitted from FIG. That is, these switches are mainly the second-stage switches S1 in that the subpackets are not exchanged.
0 'to S17', but the packet start signal PS
It is the same in that it responds to TR1, PSTR2, and packet end signal PEND2. As in the case of FIG. 5, for explanation of the operation of FIG. 9, the bit width of the data transfer path is 2 bits, the transfer destination address is composed of two partial addresses A ₁ and A ₂ , and the data is composed of two partial data D. _1, each consist of D ₂ is included in each of the 2-bit length of the sub-packet.
As shown by the thick line in FIG.
Consider the case where the data is transferred to 1 '. The operation of the data transfer network of FIG. 9 at this time will be described with reference to FIG. As shown in FIG.

The input port I2 of [00] coordinates of switch S00 ', and FIGS. 5 if the same partial address A ₁ of 7, A ₂ and partial data D _1, D ₂ are sequentially inputted. Switches S00 ', S in FIG.
24 'and S53 operate according to switch S0 in FIG.
0, S24, and S35, except that each switch starts operation when the first partial address arrives. That is, in the case of FIG. 9, since the determination bit positions for determining the destination switch of the packet from each switch are all within the partial address of the first sub packet as indicated by * in FIG. The point is that the transmission destination is decided without waiting for the arrival of the transmission, and the transmission is started.

Next, an example of the operation of the switch S14 'in FIG. 9 will be described with reference to the time chart of FIG.
From 'switch S00 to' switch S14, partial address A _1, A _2, partial data D _1, D _2, input ports I1
Are sent in sequence. At this time, a packet start signal PSRT1 is given to the switch controller P2 in synchronization with the arrival of the leading partial address and in parallel with the transfer of the packet, and the switch controller P2 performs a control operation such that the switch S00 'performs the following operation. To start. In the switch S14 ', at the first timing, the first partial address A
Storing ₁ in register L2, the first partial address A ₁ at the second timing following to move to the register L1, and stores the second partial address A ₂ in the register L2. At the third and fourth timings, the partial data D ₁ and D ₂ are sequentially stored in the input queue Q ₁ . Here, the content C2 of the register L2 is given to the switch controller P2. In the present case, this partial address A ₁ at the time when the first partial address A ₁ arrives in the register L2 is C1
Is given to the switch controller P2. The switch controller P2 creates control information M1 and M2 for the selectors S1 and S2 in the output port selection circuit E1 in response to the bit at the position indicated by the determination bit position information J2 given from the memory MS2 out of the output C2. To generate a bus from the input port I1 to the output port O1. Further switch controller P2 is first partial address A ₁ stored in the register L1, second of the partial address A ₂ stored in the register L2, at the third timing, the A _2, also, the provides a control signal M3, such as selecting the a ₁ in the fourth timing selector S3, thereby interchanging the order of the partial address a ₁ and a _2. Furthermore, the switch controller P2 is the partial address A ₂ output from the selector S3 in the third timing, select each partial address A ₁ output from the selector S3 in the fourth timing, also,
At the fifth and sixth timings, each of the partial data D ₁ and D ₂ stored in the input queue Q1 is selected, and a control signal M4 for giving to the output port selection circuit E1 is supplied to the selector S4.
Give to. The output of the selection circuit E1 is applied to queue Q3, the third, fourth, fifth, timing of the sixth, respectively _{A 2, A 1, D 1} , D 2 are input and stored in the output queue Q3 . As a result, the partial addresses A ₁ ,
It can be provided to selectively output port selection circuit E1 prior to stored a forwarding address made by replacing the A ₂ in the input queue Q1 data.

FIG. 11 shows the switches S00 'and S2 of FIG.
In 4 'and S35', the time for waiting for the arrival of the address is only half the time T in FIG. 5. Therefore, the required transfer time of the network is 9T, which is 25% faster than 12T in FIG. 5 (FIG. 8).

The switch controller P2 can perform the same processing on the packet supplied from the input port I2. As in the case of FIG.
It is possible to determine the priority of the input data 1 and I2.
The switch controller P2 has output ports O1, O2
Output enable signals OE1 and OE2 are provided, and when OE1 enters the output enable state, the output control signal OC1 is output from the switch controller P2 to the output queue Q3.
From the output queue Q3 and the partial address A
₁ , A ₂ and partial data D ₁ , D ₂ are sequentially sent to the output port O1. Similarly, when the signal OE2 is in the output permission state, the output control signal OC2 is provided from the switch controller P2 to the output queue Q4. Output queue Q3, Q4
Are filled with data and new data cannot be stored, status signals SQ1 and SQ2 connected to the switch controller P2 are applied to the switch controller P2. From there, the normal input terminal I
Although the input enable signals IA1 and IA2 of I1 and I2 are output, the input enable signals IA1 and IA2 are disabled by the status signals SQ1 and SQ2, and the input of a new packet is prohibited. In the case of the configuration in FIG. 9, the input enable signal IA1 (or IA)
2) is output to the preceding switch by the output enable signal OE1 (OE).
By inputting as 2), it is possible to prevent packets from being lost due to overflow of the queue in the middle of the transmission path. In FIG. 1, registers L1, L2, output queues Q1, Q
3 is controlled by a signal T11,
Due to T12, T13, T14, the register L3,
Control of the timing of setting data to L4 and output queues Q2 and Q4 is performed by signals T21, T22, T23 and T24, and these signals are provided from switch controller P2. FIG. 13 shows the switch controller P of FIG.
2 is a schematic configuration diagram of FIG. In the figure, timing supply circuits 10A and 10B output a packet star start signal PS.
Address decoder 16 in response to TR1 or PSTR2
A or 16B is excited, and a timing clock is applied to the counter 12A or 12B, and the end of the packet is applied in synchronization with the timing applied to the input port I1 or I2 (FIG. 1). The counter 12A or 12B and the timing decoder 14A or 14B are reset in response to the packet end signal PEND1. In the address decoder 16A or 16B, the register L2 is L4
Out of the output C2 or C4 from the memory MS2, the pit indicated by the determination bit position information J2 is cut out and the input packet is sent to the conflict control 22 as a signal indicating which of the output ports O1 and O2 should be sent. .
The timing decoders 14A and 14B have counters 12A,
In response to each of the 12B count values, the control signal T1
1 to T13, M3, and M4, and activates the output queue control 18A or 18B and the selector control 24 '. The conflict control 22 checks whether there is a conflict between the outputs of the address decoders 16A and 16B. Therefore, selector control signals M1 and M2 are generated. In the conflict control, if there is a conflict between the two outputs, only one of them is sent to the selector control 24 in response. At the same time, an input control 20A or 20B signal provided for the other of the address decoders 16A and 16B is sent. The input / controls 20A and 20B generate a signal IA1 or IA2 for inhibiting transmission of a new packet and send it to the preceding switch.

The output queue controls 18A and 18B generate signals T14 and OC for controlling the output queue Q3 or Q4, and also generate packet start signals PSTR1 or PSTR.
T2, a packet end signal PEND1 or PEND2
It is generated in synchronization with the start of packet transmission and the end of packet transmission by the output queue Q3 or Q4, and sends these signals to the next-stage switch.

FIG. 12 is a circuit diagram of FIG. 1 using the circuits of FIGS.
3 shows a time chart when a timing control different from 1 is performed. In this case, as in the case of FIG. 11, the partial address A ₁ , A ₂ and the partial data D ₁ , D ₂ are input to the switch S14 ′ of the circuit of FIG.
1 sequentially. Stores the first partial address A ₁ at the first timing in the switch S14 'in the register L2, then determines an output port to be sent the data. At a second timing following the first partial address to move to the register L1, and sends the second partial address A ₂ to the output queue Q3 by through the register L2. FIG.
In embodiments, the partial address A ₁ necessary processing (interpretation) is to determine the forwarding destination of the packet at S14 'first
Is included in the sub-packet, partial address A ₂ in the second subpacket does not require processing (interpretation) in S14 '. Therefore, it is possible to pass through the register at the second timing as described above. At this time, the switch controller P2 and the selectors S1, S2, S3, S
The control of No. 4 can be realized by a method similar to the case of FIG. Next, at the third and fourth timings, the partial data D ₁ ,
Stores sequentially input queues Q1 to D _2, and, A ₁ at the third timing, D ₁ at the fourth timing, sends D ₂ to the output queue Q3, respectively in the fifth timing. Thereby, in FIG. 12, the waiting time for 1T in S14 'required in FIG. 11 is reduced. In FIG. 12, 9T in FIG.
The required transfer time is reduced to 8T, and a pipeline operation without waiting time can be realized.

In the above description, for the sake of simplicity, the partial addresses A ₁ and A ₂ and the partial data D ₁ and D ₂ are temporarily stored in the output queue Q3 once, but the output permission signal OE1 is initially stored. Is in the output permission state, the output queue Q
3 or 4 directly through the third, fourth,
Obviously, a configuration in which the signal is transmitted to the output port O1 at the fifth and sixth timings may be employed. Also, output queues Q3 and Q4 storing the partial address sequence and the partial data sequence
May be provided after the input port, not before the output port, or both. Also, input queues Q1, Q2 output queues Q3, Q4
May be a FIFO memory, but may be a RAM or a register file. In FIG. 2, registers L3 and L4,
The registers L1 and L2 are connected in series, but the first subpacket may be stored in the register L1 (or L3) and the second subpacket may be stored in the register L2 (or L4) via a selector. . Also, in this case,
Registers L1 to L4 are RAM (the data word length is sufficient)
May be configured using a part of the register file.

As is clear from the above description, the effect of the present invention becomes large as the network is large-scale and the number of switches increases. In the above description, the data width of the data transfer path is 2 bits, the transfer destination address is 4 bits, and the data is 4 bits. However, if the number of bits of the transfer destination address is larger than the data width of the data transfer path, It is clear that the present invention is effective when the value is. In addition, although the description has been given using a 2-input / 2-output switch, it is clear that the present invention is effective regardless of the switch configuration and the network configuration.

FIG. 14 is a diagram showing another embodiment of the present invention. PE11 to PE44 are processors, and the data transfer networks connecting the processors are switches EX11 to EX44 and X partial networks NX1 to NX.
It consists of X4 and Y partial networks. The packets transferred in the data transfer network are the same as those shown in FIG. However, transfer destination partial addresses A ₁ and A ₂
Is a subscript i in the X direction and a subscript j in the Y direction of the processor PE _ij
Is set equal to That is, the address of the processor PEij is represented by a set of an X address i and a Y address j.

In FIG. 14, i is the same processor PE
ij (j = 1 to 4, i = 1, 2, 3, 4) and the processor PEij (j = 1 to 4, j = 1, 2,
3, 4) belong to one cluster.

An X partial network NXi (i = 1, 2, 2)
3, 4) mutually connect processors PEij (j = 1 to 4) of a cluster (called an X cluster) having a common i, and form a Y partial network NYj (j = 1, 2, 3, 4).
Connects processors PEij (i = 1 to 4) belonging to a cluster having the same j (called a Y cluster). These partial networks NXi and NYj are networks composed of multi-stage switches as shown in FIG. As will be described later, each of the multistage switches used therein does not need to exchange the partial addresses, and can therefore be constituted by the switches of FIG. The switch EXij (i = 1 to 4, i = 1 to 4) is a switch having three input ports and three output ports for mutually connecting the X partial network NXi, the Y partial network NYj, and the processor PEij.

For example, in the partial network NX1, processors PE11, PE12, PE13, and PE14 are provided with switches EX11, EX12, EX13, and EX, respectively.
14 and the processor PE1 is connected to NY1.
1, PE21, PE31, and PE41 are connected via re-switches EX11, EX21, EX31, and EX41, respectively.

The switch EXij has an input port IPij to the processor PEij, an output port OPij, and an input port IX to the partial network NXi as shown in FIG.
ij, an output port OXij, an input port IYij to the partial network NYj, and an output port OYij.

Since the switches EXij need to exchange the partial addresses A ₁ and A ₂ as described later, for example, the switch EXij shown in FIG. 16 in which the switch of FIG. 1 is changed to 3 inputs / 3 outputs is used. Used. Each part and each signal in FIG. 16 are the same as the part and signal having a sign starting with the same English character or English character string in FIG.

In the present embodiment, the data transfer between the processor PEij and the processor PEkl (1 ≦ i, j, k, l ≦ 4) is performed as described in detail later, by PEij → EXi
j → NXi → EXil → NYl → EXkl → PEkl or PEij → EXij → NYi → EXkj → NXk
→ EXkl → PEkl via one of two routes.

The operation of the network shown in FIG.
This will be described with reference to FIGS.

From a processor PEij to a switch EX
ij is connected to the processor PEkl via the input port IPij
It is assumed that a packet addressed to the destination is received (step 130).

The first and second partial addresses A ₁ and A _{2 at} the head of this packet are the destination processor PEkl in this case.
X-direction address k and Y-direction address l.

(1) By the way, the switch EXij is switched to the state shown in FIG.
As shown in the figure, this packet is the first condition A ₁ (= k)
= It is determined whether or not its own X-direction address (i) is satisfied (step 132). If this condition is satisfied, (that is, the destination processor PEkl and the source processor PE
ij belong to the same X class), it is determined whether or not this packet satisfies the second condition A ₂ = its own X-direction address (j) (step 134), and if this condition is also satisfied (Ie, when the source processor PEij and the destination processor PEkl are the same), the switch EXij
Sends this packet to its processor PEij via its output port OPij (step 163). On the other hand, as a result of the determination of the second condition in step 134, the second condition was not satisfied. In this case (that is, when the destination processor PEkl is another processor belonging to the same X cluster as the processor PEij), the partial addresses A ₁ and A ₂ are replaced (step 138), and the X partial network NXi is output via the output end OXij. This packet is transmitted (step 140). By this address exchange, the Y-direction address 1 of the destination processor PEkl is located at the head of this packet. As a result, each switch of the X moiety network NXi (= NXk), first subpacket arrives soon in this packet, it starts switching in response to the partial partial address A ₂ in the head portion. The subnetwork NXk sends this packet to the switch EXkl via its input port IXkl. When this switch EXkl receives this packet (step), as shown in FIG. 18, the partial address (A in this case) in the first subpacket of the packet is received.
₂ (= 1) is equal to the Y-direction address 1 of the switch EXkl (= EXil) (step 16).
4). In this case, because the condition that they are equal is satisfied, the switch EXkl sends the packet to the processor PEkl via its output port OPkl (step 165).

In this way, packet transmission is performed between processors in the same X cluster.

(2) If the result of the determination of the first condition in step 132 of FIG. 17 indicates that the first condition is not satisfied (that is, the destination processor PEkl and the source processor PEij belong to the same X cluster) If not, it is determined whether or not the second condition A ₂ (= 1) = self Y-direction address (j) (step 142). As a result of this determination, if this condition is satisfied (ie, if the processors PEkl and PEij do not belong to the same X cluster but belong to the same Y cluster), the switch EXij sends this packet to the Y partial network NYj and outputs the packet to the output port NYj. It is transmitted via OYij (step 144).

The partial network NYj sends this pocket to a switch (Ekj) having an X address equal to the partial address A ₁ (= k) at the head of this packet.
The switch (Ekj) receives this packet from the input terminal IYkj as shown in FIG.
52), it is determined whether this packet is equal to the second partial address A ₂ = the own Y-direction address (step 15).
4). In this case, since this condition is satisfied, the switch E
kj sends the packet to the connected processor (PEkj) via output port OPkj. Thus, packet transfer between the two processors belonging to the same Y cluster can be performed.

(3) If the result of the determination at step 142 in FIG. 17 is negative, that is, the destination processor PEkl and the source processor PEij do not belong to the same X cluster and also belong to the same Y cluster. If not, there are two paths connecting these two processors. That is, it is the route that first forwards the packet to the first route X subnetwork, specifically, PEij
→ EXij → NXi → EXil → NY1 → EXkl → P
Ekl. In this route, since the Y address is determined first, this route is hereinafter referred to as a Y priority route. The second route is a route for transferring a bucket to the Y partial network first, and specifically, PEij → EXij → NYj
→ EXkj → NXk → EXkl → PEkl. In this route, since the X address is determined first, this is hereinafter referred to as a priority route.

In step 146, one of these two routes is selected.

This selection is made in advance by each switch EXij
It may be set for each case. In this case, step 146
Is omitted. Alternatively, the amount (load) of packets passing through each partial network of the network may be measured, and the above selection may be dynamically changed so that the load becomes as uniform as possible.

If the X priority route is selected in step 146, the stitch EXij sends the packet to the output port OYi.
The packet is sent to the partial network NYj via j (step 144). In response to the packet, the partial network NYj switches the switch Ekj having an X address equal to the partial address A ₁ (= k) at the head of the packet.
Via the input port IYkj. As shown in FIG. 19, when this switch receives this (step 152), the second partial address A ₂ (=
1) = It is determined whether or not its own Y address (= j) is satisfied (step 154). In this case, since j ≠ l is assumed, the result of this determination is negative. The switch Ekj enters the partial addresses A ₁ and A ₂ of this packet or moves the partial address A ₂ to the head (step 15).
8). Then, the packet is transferred to the X partial network NX.
k via the output port OXjk.

Each switch in the partial network NXk can respond to the partial address A _{2 at} the head of the packet as soon as it arrives. The sub-network then sends this packet to the switch Ekl with the Y-direction address equal to the sub-address A ₂ (= 1).

This switch Ekl is connected to the input port IXk
This packet is received via l (step 162,
Determines that Figure 18), or equal to the first partial address A ₁ own X-direction address of this packet (= k). In this case, since the determination result is affirmative, the switch Ekl sends the packet to the processor PEkl. In this way, packet transfer between two processors that do not belong to the same cluster is performed by the X priority route.

If the Y priority route is selected in step 146 (FIG. 17), the switch EXij replaces the partial addresses A ₁ and A ₂ in the packet and moves A ₂ to the top (step 138). Thereafter, the packet is transmitted to the X partial network NXi (step 140). The partial network NXi sends the packet to the switch EXil having a Y address equal to the partial address A ₂ (= 1).

In this switch EXil, as shown in FIG. 18, after receiving the bucket (step 162), A ₁
It is determined whether (= k) = it is equal to its own X-direction address (= i) (step 164). In this case, the result of this determination is negative, and the switches are set to the partial addresses A ₂ , A ₁
The interchanged, transferred to A ₁ to the beginning of the packet (Step 1
68) again, this packet is
(Step 170). By means of this partial network NYl, this packet forwards this packet to the switch Ekl with an X-direction address equal to the first partial address A ₁ (= k) of this packet. In this switch Ekl, steps 152, 154, and 156 in FIG.
By means of the processor PE connected thereto.
kl. Thus, 2 which does not belong to the same cluster
Packets are routed between the two processors by the Y priority route.

The advantages of the network according to the present embodiment are as follows.
The point is that mounting becomes easy by reducing the scale of each partial network. Since the processors are clustered as described above, the partial network NY
j, the first partial address A _{1 of} the transfer destination addresses
Only, only the second partial address A ₂ becomes necessary in NXi. In this embodiment, A ₁ and A ₂ are provided in the switch EXij.
Of each partial network NX
Since the necessary partial addresses in i and NXj are always present in the first subpacket, each switch in the partial network does not need to wait for all of the partial addresses to arrive, thereby enabling high-speed data transfer.

In the operation of the network shown in FIG. 14, the speed is further increased by changing as follows.

That is, in FIG. 18, when each of the switches (EXmn) receives a packet from the X partial network NXm, where m and n are integers, a determination 16 is made.
4, it is necessary to perform the network NXm waiting for the arrival of the partial address A _1. However, as already mentioned, the network NXN, packets carry partial address A ₂ at the head. Therefore, the above determination 164
Becomes possible only after the second subpacket from the partial network NXm arrives at the switch EXmn. The same problem occurs for decision 154 in FIG.
These problems can be improved by changing the partial networks NXm, NYn, etc. as follows.

That is, the partial network NXm or N
Yn and the like are respectively represented by Step 180A in FIGS.
As shown in FIG. 18B, when each packet is output to a certain switch EXmn, the partial addresses A ₁ and A ₂ in the packet are switched in the switch in the partial network closest to the switch. This can be realized in the same manner as the method described with reference to FIG.

From these results, the NX
The operation of the switch EXnm received in the packet is
As shown in FIG. In the figure, the same reference numerals as those in FIG. 18 denote the same processes. This improved operation as can be seen from this figure, switch EXmn is performed the determination process 144 for partial address A ₁ is the same as in FIG. 18, the X moiety network NXm improvements already mentioned since this partial address a ₁ top of the packet to be sent is included, the determination processing 144 can be initiated as soon as the arrival of the partial address a _1. Also,
As a result of the X part network NXm changing the address when outputting the packet, the address change required in FIG. 18 is not required in FIG.

Similarly, the operation of the switch Exmn when receiving a packet from the Y partial network NYm is described in FIG.
It looks like 3. In the figure, the same reference numerals in FIG. 19 denote the same parts. Also in this case, the comparison between FIG. 22 and FIG. 18 is directly applicable.

In the above description, A ₁ and A ₂ are 2 bits,
Although d is 2 bits, the effect of the present invention does not change even if this is an arbitrary number of bits. Further, the transfer destination address is divided into three, a partial network is provided in the Z direction in addition to the X and Y directions, and the EXij is made into 4 input ports / 4 output ports like EXijk. It is also clear that the number of divisions of can be increased.

FIG. 24 shows an embodiment of such a data transfer network. In the figure, NX ₁₁ , NX ₁₂ , NX
₁₄ , N _44, etc. represent partial transfer networks 7.1 in the X direction, NY ₁₁ , NY ₁₂ , NY ₁₄ , NY ₄₄ etc. represent partial transfer networks in the Y direction, which are the same as those in FIG. In the embodiment, the partial network N in the Z direction is used.
_{Z 11, NZ 21, NZ 41} , NZ 14 ... NZ 44 and the like.

The switches EX ₁₁₁ , E ₁₄₁ , EX ₄₁₁ , EX _{444 and the} like and the processors PE ₁₁₁ , PE ₁₄₁ , PE ₄₁₁ , PE ₄₄₄ are provided at the intersections of these three partial networks.

In the figure, for the sake of simplicity, each partial network is represented by a straight line, switches and processors are only partially illustrated, and switches and processors are partially illustrated.

[0059] Switch EX ₁₁₁ is connected at the input and output ports for each of the X-direction partial network NX _11, Y-direction partial network NY _11, Z-direction partial network NZ ₁₁ and processor PE1 _11.

The same applies to other processors.

When a packet is transferred from one processor to another processor, the transfer destination address in the packet is set to A
₁ , A ₂ , and A ₃ . Assuming that the packet destination processor is Pijk, each is equal to the respective X, Y, Z direction coordinates i, j, k.

Now, for example, the processors PE ₁₁₁ to PE
_When sending a packet to _444, there are several packet transfer routes. For example, PE ₁₁₁ → EX ₁₁₁ → NX ₁₁ →
EX ₄₁₁ → NY ₁₄ → EX ₄₄₁ → NZ ₄₄ → EX ₄₄₄ → PE ₄₄₄
Is one of them.

The operation for transferring a packet according to this route is as follows.

[0064] When the switch EX ₁₁₁ sends out the packet to the partial network NX _11, switch EX ₁₁₁ is similar to the case of FIG. 17, partial address A _1, A _2, A ₃ without replacing the transfers. Partial network NX
₁₁ this packet, and sends to the switch EX ₄₁₁ with the X coordinate equal to the address A _1. Since the switch EX ₄₁₁ is A ₂ of the partial address in the packet A _2, A _3, A ₁ is different from the self-Y coordinate, Y-direction partial network NY
Send to ₁₄ . At that time, the address in the packet is A ₂ ,
Replace A ₃ and A ₁ in that order. Switch EX ₄₄₁ this network with equal Y coordinate a packet to the address A ₂
To send to.

The switch EX ₄₄₁ sends this packet to the Z-direction partial network NZ ₄₄ because the partial address A _{3 in it} is different from its own Z coordinate. At this time, the addresses are changed in the order of A ₃ , A ₁ , and A ₂ . The network sends the packet to the EX ₄₄ with equal Z coordinate address A _3. Switch EX ₄₄₄ which received this
_Sends this packet to the processor PE ₄₄₄ .

As described above, in this embodiment, when there are more processors than in the case of FIG. 14, data transfer between them can be performed. In addition, since each switch EX performs the above-described switching of the addresses, the switches can be switched in response to the leading partial address of the packet that has arrived at the partial network.

As shown in FIGS. 22 and 23, the addresses are switched in the EX ₄₁₁ and EX ₄₄₁ at the time of switching, and the partial networks NX ₁₁ , NY ₁₄ and NZ ₄₄ change three addresses at the time of packet output. A higher speed operation can be processed.

FIG. 25 shows an embodiment of the present invention. PE is a processor, and EX is a switch. As shown in the figure, one switch similar to the switch EX100 is provided for each of a plurality of processors similar to the processor PE100, and each switch EX An input port and an output port are connected to a nearby switch to form a net-like data transfer network. FIG.
As shown in FIG. 6, the switch EX100 is connected to the processor PE.
100 input / output ports IP100 / OP10
Input / output port between 0, and 4 neighbor switches, I
N100 / ON100, IW100 / OW100, IS
100 / OS100 and IE100 / OE100. In this embodiment, as described above, packets transferred between processors are exchanged as packets composed of examples of subpackets divided for each bit width d of the data transfer path as shown in FIG. This embodiment is different from the other embodiments in that the transfer destination address in the packet is d.
The upper part of the divided transfer destination address is used as a global address AG and the lower part is used as a local address AL. It is stored in a sub-packet, and the first sub-packet is provided with a flag bit L indicating whether the division address stored therein is AG or AL. For simplicity, d =
4, and AG and AL each have 3 bits. FIG.
As shown in FIG.
The processors are connected by switches as shown in FIG. 25, and the processors are clustered by eight having the same global address as shown in FIG. In this embodiment, each switch can use the configuration shown in FIG. 30 in which, for example, a switch similar to that shown in FIGS. 9 and 16 has a configuration of 5 input ports / output ports. The operation of each unit in FIG. 30 and the meaning of the reference numerals are the same as those in FIG. 9 having the reference signs starting with the same English characters (strings). The configuration of FIG. 30 differs from the configuration of FIG. 9 in that the set circuit X21 of the flag bit L is provided between the divided address storage registers L12 and L22 and the selector S31. X21 sets the flag bit L according to a set signal XC21 from the switch controller P21.
The operation of the switch will be described below. In FIG. 30, R
Portions indicated by 22 to R25 have the same configuration as the portion indicated by R21, and are omitted for simplicity.
In each processor, when data is transmitted for the first time, AG is included in the first subpacket, and the L bit is set to 0.
FIG. 29 shows the processing procedure in each switch. In this embodiment, since the L bit is provided, each switch does not need to refer to the local address AL while L = 0, and therefore, all switches including the transfer destination address divided as described above are included. The next-stage switch to which the packet should be sent can be determined without waiting for the arrival of the subpacket. When packets are successively transferred and enter a switch in the cluster having the same global address as the target processor, the switch waits for the arrival of a subpacket including the local address AL, and as in FIG. A
G is exchanged so that the local address is included in the first subpacket, and L = 1 is transmitted to the next stage. Subsequent switches can determine the next switch to which the packet should be sent without waiting for the arrival of the second subpacket including the global address.

In FIG. 27, when each processor has an address as shown in the figure, a case is considered where a packet is sent from the processor NS of A _G = 000, AL = 110 to the processor NR of A _G = 110, AL = 110. . Here, each switch stores the local address of the adjacent processor and the global address of the adjacent cluster together with its own address, and compares the global address _AG with its own global address while L = 0. If different, the transfer direction and output port are determined by comparing _AG with the global address of the adjacent cluster. In the simplest case, the transmission may be performed in a direction in which the difference between the global addresses is minimized. According to this algorithm, the packet follows the route as shown in FIG. 27, and the position indicated by NX (A _G
= 110, AL = 000). Where N
The switch of X is AL and A in the same manner as the switch of FIG.
_G is exchanged, and L = 1 is transmitted to the next stage. Later,
The local address is compared with the local address of the adjacent processor, and the transfer direction and the output port can be determined by the same algorithm as described above. In this embodiment, of the switches in each stage, only the NX switch needs to wait for the arrival of two subpackets including A _G and AL, and the other switches wait for the arrival of the transfer destination address. The time is half that of the case where the present invention is not used, and the effect is extremely large especially when the number of processors is large.

In the above description, A _G and AL each have 3 bits. However, the effect of the present invention does not change even if the number of bits is arbitrary.

Although the transfer destination address is divided into two,
Even if the number of divisions is increased and the L bits are changed to a plurality of bits, the effect of the present invention remains unchanged.
Further, although the switches of the data transfer network are connected to the vicinity of four, even if the switches are connected to an arbitrary number, the effect of the present invention does not change.

In the above description of the embodiment, the destination of the data packet is indicated by the transfer destination address contained in the first two or more subpackets. It is clear that the tag information may be used. As such tag information, it is possible to use, for example, an exclusive OR of an address of a transmission processor and a transfer destination address.

[0073]

As described above, according to the present invention, it is not necessary to wait for the arrival of all of the plurality of subpackets including the transfer destination address at each stage of the plurality of switches configured in the multistage in the data transfer network. High-speed data transfer becomes possible.

Further, in the data transfer network of the present invention, the switch itself selects the transfer path, so that efficient data transfer is possible.

[Brief description of the drawings]

FIG. 1 is a second-stage switch (eg, S14 ′) of the device of FIG.
FIG.

FIG. 2 is a schematic configuration diagram of first, third or fourth stage switches (S00 ′, S24 ′ or S35 ′) of the device of FIG. 8;

FIG. 3 is a diagram showing blocks of a parallel computer system to which a data transfer network according to the present invention is applied.

FIG. 4 is a diagram showing the structure of a packet according to the present invention.

FIG. 5 is a schematic configuration diagram of a low-speed data transfer network for comparison with the present invention.

FIG. 6 is a schematic configuration diagram of a switch (Sij) of the network in FIG. 3;

FIG. 7 is a diagram for explaining the operation of a switch of the network in FIG. 3;

FIG. 8 is a time chart of the operation of the network of FIG. 3;

FIG. 9 is a schematic configuration diagram of a data transfer network according to the present invention.

FIG. 10 is a diagram for explaining the operation of the switch of the device in FIG. 8;

FIG. 11 is a time chart showing an example of the operation of the device shown in FIG. 8;

FIG. 12 is a time chart of another example of the operation of the device in FIG. 8;

FIG. 13 is a schematic configuration diagram of a switch controller (P2) used for the switch of FIG. 9;

FIG. 14 shows another embodiment of the data transfer network according to the present invention using a partial network.

FIG. 15 shows another embodiment of the data transfer network according to the present invention using a partial network.

FIG. 16 shows a switch (E) used in the devices shown in FIGS. 14 and 15;
The schematic block diagram of Xij).

FIG. 17 is a flowchart of the operation when the switch (EXij) in FIG. 16 receives a packet from a processor.

FIG. 18 shows a switch (EXij) used in the apparatus shown in FIG.
9 is a flowchart of an operation performed when a packet is received from a partial network NY.

FIG. 19 shows a switch (EXij) used in the apparatus shown in FIG.
9 is a flowchart of an operation performed when a packet is received from a partial network NX.

FIG. 20 shows an X-direction partial network (N
The flowchart of the improved operation of Xj).

FIG. 21 shows a Y-direction partial network (N
10 is a flowchart of the improved operation of Yi).

FIG. 22 is a flowchart of the improved operation when the switch (EXij) of the apparatus of FIG. 16 receives a packet from the Y-direction subnetwork (NYi).

FIG. 23 is a flow chart of the improved operation when the switch (EXij) of the device of FIG. 16 receives a packet from the X-directional subnetwork (NXj).

FIG. 24 is an embodiment of a data transfer network using a three-dimensional partial network.

FIG. 25 shows another embodiment of the present invention using a lattice-coupled network.

FIG. 26 is a diagram showing input / output ports of the switch (EX100) in FIG. 25.

FIG. 27 is a diagram showing a data transfer route in the device of FIG. 25;

FIG. 28 is a diagram showing a packet used in the device of FIG. 25;

FIG. 29 is a flowchart showing the operation of a switch (EX) of the apparatus shown in FIG. 25;

FIG. 30 is a schematic configuration diagram of a switch (EX) of the device in FIG. 25.

Continuing on the front page (72) Inventor Teruo Tanaka 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (72) Inventor Shigeo Nagashima 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (56) References JP-A-60-232743 (JP, A) JP-A-61-289746 (JP, A)

Claims (3)

(57) [Claims] A first network having a plurality of pairs of input terminals and output terminals and capable of transferring data in parallel between them; a first network having a plurality of pairs of input terminals and output terminals; A second network capable of transferring data in parallel between the first network, a pair of the input terminal and the output terminal of the first network, and a pair of the input terminal and the output terminal of the second network. connected, the output of the first network
The data transferred from the force end, and any one output terminal of the output terminal of the second network, said input of said first network said input terminal and said second network in response to the transfer data data transfer network, characterized in that a switch for controlling to be transferred to one input terminal of the edge. 2. The data transfer network according to claim 1, wherein said switch has a switch controller for selecting a transfer path in response to a part of transfer address information in transfer data. 3. The switch according to claim 2, wherein the switch has a memory for storing information for determining which part of the transfer destination address information is for determining the transfer path. Data transfer network.