JPH08236701A - Semiconductor intergrated circuit device - Google Patents

Abstract

PURPOSE: To provide a semiconductor integrated circuit device decreasing a fluitnation of analog characteristics due to the difference in forming places in a plurality of semiconductor circuit blocks. CONSTITUTION: A plurality of semiconductor circuit blocks B1 to B240 of the same constitution composing an electric circuit controlling analog voltage are jaxtaposed in a line on a semiconductor substrate Sb and dummy semisemiconductor circuit blocks DB1, DB2 of about the same constitution with the semiconductor circuit blocks B1 to B240 are respectively juxtaposed in both of the outside positions of a plurality of the semiconductor circuit blocks B1 to B240 of the semiconductor substrate Sb.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to, for example, a color TFT.
A semiconductor in which a plurality of semiconductor circuit blocks of the same configuration that form an electric circuit that controls an analog voltage of a liquid crystal driver that drives liquid crystal cells in each column of a matrix liquid crystal panel according to a digital signal supplied from the outside are arranged in a row The present invention relates to an integrated circuit device.

[0002]

2. Description of the Related Art A conventional semiconductor integrated circuit device of this type is
As shown in FIG. 3, a plurality of vertically elongated semiconductor circuit blocks B1 and B1 having the same configuration and forming an electric circuit for controlling an analog voltage are formed in the central portion of a horizontally elongated semiconductor substrate Sb.
2, ..., B240 are arranged side by side in a row. Each of the semiconductor circuit blocks B1, B2, ..., B240 has an input signal line (not shown) for an external digital signal formed at one end portion (the lower end portion on the paper surface) in the vertical direction, and the other end portion in the vertical direction (paper surface). An output signal line (not shown) of an analog signal is formed at the upper end portion) and is connected to, for example, the liquid crystal cells in each column of the color TFT matrix liquid crystal panel.

For example, when the color TFT matrix liquid crystal panel is composed of liquid crystal cells of horizontal 1920 lines (= 3 × 640), one semiconductor integrated circuit device has, for example, 240 semiconductor circuit blocks B1 on the semiconductor substrate Sb. , B2, ..., B240 are arranged side by side in a row, and one color TFT matrix liquid crystal panel is driven by eight semiconductor integrated circuit devices (8 × 240 = 1920).

FIG. 4 shows each semiconductor circuit block B1, B2, ..., B240 in the semiconductor integrated circuit device shown in FIG.
Shows an example of an electric circuit configuration realized respectively, and in this example, an example of a liquid crystal driver for driving a color TFT matrix liquid crystal panel is shown. In FIG. 4, the sub-block 1 comprises an operational amplifier and an output circuit, and an analog output is taken out through the output wiring. The sub block 2 is composed of an analog voltage switch circuit. The sub-block 3 is composed of a capacity group. The sub block 4 is composed of an analog voltage switch circuit and a reference voltage switch circuit.
The sub block 5 is composed of a two-stage latch circuit, and a digital signal is supplied through the input wiring.

Digital data is input to the sub-block 5 from an external control circuit for displaying an image or the like. The two-stage latch circuit of the sub-block 5 is a storage circuit that temporarily stores the input digital data, and a first-stage storage circuit that sequentially stores the input digital data, and a digital circuit that converts digital-to-analog conversion simultaneously. The second stage storage circuit stores digital data.

The analog voltage switching circuit of the sub-block 4 is a switching circuit that switches the voltage supplied to the capacitance for digital / analog conversion according to digital data from the outside. The reference voltage switching circuit of the sub-block 4 is a circuit for switching an analog reference voltage for digital / analog conversion. The capacitance group of the sub-block 3 constitutes a capacitance type digital-analog converter and has a function of determining an output voltage by distribution of charges.

The analog voltage switch circuit of the sub-block 2 comprises a switch circuit for switching the circuit configuration for operating the capacitance type digital-analog converter. The operational amplifier of the sub-block 1 constitutes a capacitance type digital-analog converter, and requires a sufficient voltage amplification factor in order to stably transfer charges regardless of manufacturing variations. The output circuit of the sub-block 1 is a current amplifier circuit for driving an external load (liquid crystal panel),
It functions as a switch circuit that separates the external load from the internal circuit.

The analog output extracted from the sub-block 1 is a digital-analog converted analog signal, which is output to the terminal of the semiconductor integrated circuit device. The output terminal of the semiconductor integrated circuit device is a liquid crystal panel (wiring and TF
A glass plate on which T is patterned, a liquid crystal material, and an adhesive) are connected to each other with an anisotropic conductive adhesive. Among the sub-blocks 1 to 5 described above, the ones that cause capacitive coupling are the sub-block 1 that constitutes an operational amplifier having a high-impedance circuit and an output circuit, and the sub-block 2 that constitutes an analog voltage switch. And a sub-block 3 that constitutes a capacity group.

FIG. 5 is a block diagram showing an example of a concrete circuit configuration of the semiconductor circuit block of FIG. As shown in FIG. 5, this semiconductor circuit block includes a two-stage latch circuit 11 (sub-block 5 in FIG. 4) to which a digital input is supplied.
Corresponding to the two-stage latch circuit) and the reference voltage switching circuit 12
(Corresponding to the reference voltage switching circuit of sub-block 4 in FIG. 4)
And a circuit portion shown below. That is, this semiconductor circuit block includes eight capacitors CP ₀ connected in parallel,
A capacitor group consisting of CP ₁ , ..., CP ₇ , and a capacitor C
The capacitance values of P ₀ , CP ₁ , ..., CP _K , ..., CP ₇ are reference capacitance values C, 2C, ..., 2 ^K C ,.
Is.

[0010] Each capacitor CP _0, CP _1, ..., negative electrode CP ₇ are connected to the negative input terminal A of the operational amplifier 41, the capacitors CP _0, CP _1, ..., the positive side electrode of the CP ₇ is The discharge switches SWB ₀ , SWB ₁ , ...,
Power supply V ^- _ref that supplies the reference input voltage via SWB ₇
It is connected to the. Furthermore, each capacity CP ₀ , CP ₁ ,
..., to the positive electrode of the CP _7, respectively charging switch SWA _0, SWA _1, ..., one terminal is connected the SWA _7. These charging switches SWA ₀ , SW
A ₁ , ..., SWA ₇ are set to the ON state when sampling the input voltage.

Charging switches SWA ₀ , SWA ₁ , ...,
One terminal of each of the digital input switches SW ₀ , SW ₁ , ..., SW ₇ is connected to the other terminal of SWA ₇ . Digital input switches SW ₀ , SW ₁ , ...,
SW ₇ corresponds to each bit of the digital signal input to this output circuit, and is set to an on state when the corresponding bit is “1” and set to an off state when the corresponding bit is “0”. .

Further, each digital input switch SW ₀ ,
The other terminals of SW ₁ , ..., SW ₇ are connected to a power supply V ⁺ _ref that supplies a reference input voltage. SWA ₈ is a charging switch connected between the input and output terminals of the operational amplifier 41,
SWA ₉ is a charging switch that is turned on when the input voltage of the operational amplifier 41 is sampled, and is a negative feedback capacitor CP.
It is connected between the positive electrode of ₈ and the reference input voltage (power supply) V ^- _ref . SWB ₉ is a discharging switch for discharging the charged electric charge, and is connected between the positive electrode of the negative feedback capacitor CP ₈ and the output V _out .

The output Y of the operational amplifier 41 is fed back to the negative input terminal A of the operational amplifier 41 via the charging switch SWA _{8 and also} to the negative input terminal via the discharging switch SWB ₈ and the negative feedback capacitance CP _8. You have been returned to A. Further, the positive input terminal B of the operational amplifier 41 is connected to the reference input voltage (power supply) V ^- _ref, and is also connected to the negative input terminal A via the charging switch SWA ₉ and the negative feedback capacitor CP _8. There is. The negative feedback capacitance CP ₈ has a capacitance value of 2 ⁸ × C (256C) which is the reference capacitance value.
The output voltage generated by this output circuit is the output terminal V
is output from the _out.

The capacitance group consisting of the capacitances CP ₀ , CP ₁ , ..., CP ₇ together with the feedback capacitance CP ₈ corresponds to the capacitance of the sub-block 3 in FIG. Digital input switch S
W ₀ , SW ₁ , ..., SW ₇ correspond to the analog voltage switch circuit of the sub-block 4 in FIG. Charging switches SWA ₀ , SWA ₁ , ..., SWA ₇ , SWA ₈ , SWA
₉ , discharge switches SWB ₀ , SWB ₁ , ..., SW
B ₇ and SWB ₈ correspond to the analog voltage switch circuit of the sub-block 2 in FIG. The operational amplifier 41 corresponds to the operational amplifier and output circuit of the sub-block 1 in FIG.

The operation of the semiconductor circuit block having the above configuration will be described. First, the discharge switch SW
B ₀ , SWB ₁ , ..., SWB ₇ are set to the ON state. As a result, the output Y of the operational amplifier 41 is negatively fed back to the negative input terminal A of the operational amplifier 41 via the discharging switch SWB ₈ . Due to such negative feedback, the potential difference between the negative input terminal A and the positive input terminal B becomes the offset voltage shown in [Equation 1].

[0016]

## EQU1 ## _Voff = (potential of the positive input terminal B of the operational amplifier 41)-(potential of the negative input terminal A of the operational amplifier 41) Also, between the positive and negative electrodes of the capacitors CP ₀ , CP ₁ , ..., CP ₇ . The potential difference also becomes equal to the offset voltage _Voff . At this time, the charge amount Q _DCn charged in each of the capacitors CP ₀ , CP ₁ , ..., CP ₇ is

[0017]

[Formula 2] Q_DCn= 2ⁿ× C × V_off [N = 0 to 7]. Next, the 8-bit digital input signal is
TAL input switch SW₀, SW ₁,,, SW₇Entered in
Corresponding to each bit of the digital input signal.
Input switch SW₀, SW₁,,, SW₇Is on,
Or it is set to the off state. Best of digital input signal
Significant bit (MSB) is digital input switch SW₇To
Corresponding, least significant bit (LSB) of digital input signal
Is the digital input switch SW₀It corresponds to.

Next, the discharge switches SWB ₀ , SWB
After setting all of ₁ , ..., SWB ₇ to the off state, all of the charging switches SWA ₀ , SWA ₁ , ..., SWA ₇ are set to the on state. At that time, the charge Q _CCn charged in the capacitance connected to the switch that is set to the ON state among the digital input switches SW ₀ , SW ₁ , ..., SW ₇ is

[0019]

## _EQU3 ## Q _CCn = 2 ⁿ × C × (V ⁺ _ref −V ⁻ _ref + V
_off ), (n = 0 to 7). Since the charging switch SWA ₉ is set to ON, the offset voltage is applied to the capacitor CP ₈ as shown in [Equation 4].

[0020]

(4) V _CP8 = V _off Therefore, the charge Q stored in the capacitor CP _8
CP8 becomes as shown in [ _Equation 5].

[0021]

[Formula 5] Q_CP8= 256 x C x V_off Next, the charging switch SWA₀, SWA₁,,, SW
A₇After setting all of the
SWB₀, SWB₁,…, SWB₇All turned on
Set to. At that time, the output Y of the operational amplifier 41 is for discharging
Switch SWB ₈Is fed back to the negative input terminal A through
Therefore, the potential difference between the negative input terminal A and the positive input terminal B is
Is again offset voltage V_offIs equal to

The potential difference between the positive and negative electrodes of the capacitors CP ₀ , CP ₁ , ..., CP ₇ is also equal to the offset voltage V _off . At this time, the charges transferred from the negative electrodes of the capacitors CP ₀ , CP ₁ , ..., CP ₇ gather at the negative electrodes of the capacitor CP ₈ . The amount of charge ΔQ _CP8 transferred to the negative electrode of the capacitance CP ₈ is the bit information “0” of the digital input signal.
Or if the numerical value of "1" is represented by bitn,

[0023]

[ _Equation 6] ΔQ _CP8 = (1 × bit0 + 2 × bit1 + 4 × bit2 +
8 x bit3 + 16 x bit4 + 32 x bit5 + 64 x bit6 + 12
8 × bit7) × C × (V ⁺ _ref− V ⁻ _ref ).

For example, when a digital input signal of "10110010" in binary number is input, bit0, bit2, bit3 and bi
t6 is “0” (off state), bit1, bit4, bit5 and bit7
Becomes "1" (ON state), and the amount of charge ΔQ _CP8 transferred to the negative electrode of the capacitor CP _{8 at} this time can be obtained by [ _Equation 7].

[0025]

ΔQ _CP8 = (2 + 16 + 32 + 128) × C × (V ⁺ _ref− V ⁻ _ref ) = 178 × C × (V ⁺ _ref− V ⁻ _ref ) At this time, the polarity of the transferred charge is opposite and the same. A certain amount of charge collects on the positive electrode of the capacitor CP ₈ . The potential of the negative electrode of the capacitor CP ₈ is the same potential as the negative input terminal A of the operational amplifier 41, and from [Equation 1],

[0026]

(Equation 8) (potential of the negative electrode of the capacitance CP ₈ ) = V ⁻
_ref- V _off . As a result, the output V _out of this output circuit is obtained from [Equation 4] and [Equation 8] when there is no charge transfer due to the capacitors CP ₀ , CP ₁ , ..., CP ₇ .

[0027]

[Formula 9] V _out = V ⁻ _ref −V _off + V _off = V ⁻ _ref , and when there is a charge transfer shown in [ _Formula 6],

[0028]

[Formula 10] V _out = (1/256) × (1 × bit0 + 2 × bit1 +
4 x bit2 + 8 x bit3 + 16 x bit4 + 32 x bit5 + 64 x
bit6 + 128 × bit7) × ( V + ref -V - ref) + V -
It becomes _ref .

When the binary digital signal "10110010" shown in the above example is input,

[0030]

[Number 11] _{V out = (178/256) × (} V + ref -
V ^- _ref ) + V ^- _ref . As described above, this semiconductor circuit block is
2 for each bit of the digital signal
Capacity CP ₀ with a ^{0-2 seven} times the capacitance value, CP _1, ...,
A capacitance group consisting of CP ₇ and a switch group for on / off controlling charging to these capacitance groups based on each bit information of the input digital signal are provided, and the numerical value represented by the input digital signal is provided. Is charged in the capacitance group, and the voltage generated by the charged charges is input to the amplifier to obtain the required output voltage. That is, the required voltage can be generated without providing many reference voltages. Therefore, the number of wires is significantly reduced.

[0031]

In the semiconductor integrated circuit device as described above, the semiconductor circuit blocks B1, B2, ...
Since the B240s are arranged side by side in a row, the semiconductor circuit blocks B1, B2 ,.
Are the other semiconductor circuit blocks B1 and B on both sides.
2, ..., B240 and capacitive coupling occur.
6 is an enlarged view of a portion of semiconductor circuit blocks B1, B2, ..., B8, ... Of the semiconductor integrated circuit device of FIG.
_1-2 is the coupling capacitance between the semiconductor circuit blocks B1 and B2, C _2-3 is the coupling capacitance between the semiconductor circuit blocks B2 and B3, and C _3-4 is the semiconductor circuit blocks B3 and B4.
Coupling capacitance between them, C _4-5 is semiconductor circuit block B
_C5-6 is a coupling capacitance between the semiconductor circuit blocks B5 and B6, _C6-7 is a coupling capacitance between the semiconductor circuit blocks B6 and B7, and C is a coupling capacitance between the semiconductor circuit blocks B6 and B7.
_7-8 is a coupling capacitance between the semiconductor circuit blocks B7 and B8.

Each semiconductor circuit block B1, B2, ..., B
The analog characteristics of 8, ... are the coupling capacitances C _1-2 , C
_2-3 , ..., C _7-8 , are influenced by the semiconductor circuit blocks B1, B2, ..., B8, ... Adjacent to both sides, and for example, the semiconductor circuit block B2 other than the both end positions is coupled with the coupling capacitance C _1-2. , C _2-3 through two semiconductor circuit blocks B
Since they are connected to the semiconductor circuit blocks B1 and B3, they are influenced by the two semiconductor circuit blocks B1 and B3. On the other hand, the semiconductor circuit block B1 at both ends, for example, the right end, has a coupling capacitance C
_Since it is only connected to one semiconductor circuit block B2 through _1-2 , one semiconductor circuit block B2
Only affected by.

As described above, in the conventional semiconductor integrated circuit device, the semiconductor circuit blocks B2 to B239 are capacitively coupled with the semiconductor circuit blocks B1 to B240 adjacent on both sides, whereas the semiconductor circuit blocks B on both ends are capacitively coupled.
1, B240 are semiconductor circuit blocks B adjacent to one side.
2 and B239 are capacitively coupled, and the degree of capacitive coupling is different, even if the circuit patterns of the semiconductor circuit blocks B1 to B240 are all designed to be the same, the analog circuits of the semiconductor circuit blocks B1 and B240 at both ends are analog. The characteristics are different from the analog characteristics of the other semiconductor circuit blocks B2 to B239, and there is a problem that the same characteristics cannot be obtained.

Semiconductor circuit blocks B1 and B240 at both ends
Analog characteristics of other semiconductor circuit blocks B2 to B2
The problem that is different from the analog characteristics of 39 is that color T
When the FT matrix liquid crystal panel is driven by the above semiconductor integrated circuit device, the following problems will appear. To drive a color TFT matrix liquid crystal panel having 1920 lines in the horizontal direction by using a semiconductor integrated circuit device in which 240 semiconductor circuit blocks B1 to B240 are formed, as described above, Eight semiconductor integrated circuit devices are required. This state is shown in FIG. In FIG. 7, LCP is a color TFT matrix liquid crystal panel having 1920 lines in the horizontal direction. IC _{1 to} IC
₈ is eight semiconductor integrated circuit devices, each of which is 240
The analog output line of the book is connected to the color TFT matrix liquid crystal panel LCP.

In this way, one color TFT matrix is
Liquid crystal panel LCP with 8 semiconductor integrated circuit device ICs₁
~ IC₈When driven by, each semiconductor integrated circuit device IC₁~
IC ₈In the semiconductor circuit blocks B1 and B2 at both ends
The analog characteristics of 40 are other semiconductor circuit blocks B2 to
Color T is different from the analog characteristics of B239.
On the screen of the FT matrix liquid crystal panel LCP, the same
Semiconductor integrated circuit device even if one digital data is input
IC₁~ IC₈Boundary BD of analog voltage output
The brightness of the part of the
There is a fatal defect in the image quality that streaks occur
There was a problem.

Therefore, an object of the present invention is to provide a semiconductor integrated circuit device capable of eliminating variations in analog characteristics due to differences in formation locations in a plurality of semiconductor circuit blocks.

[0037]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit device, wherein a plurality of semiconductor circuit blocks having the same structure and forming an electric circuit for controlling an analog voltage are arranged in a line on a semiconductor substrate. Dummy semiconductor circuit blocks are arranged in parallel on both outer sides of the plurality of semiconductor circuit blocks on the substrate.

A semiconductor integrated circuit device according to a second aspect is the same as the semiconductor integrated circuit device according to the first aspect, wherein the electric circuit has liquid crystal cells constituting a matrix liquid crystal panel in a horizontal direction.
It is a liquid crystal drive circuit that drives line by line.

[0039]

According to the structure of the present invention, since the dummy semiconductor circuit blocks are arranged in parallel on both outer sides of the plurality of semiconductor circuit blocks, the semiconductor circuit blocks at both ends are adjacent semiconductor circuit blocks and dummy semiconductor circuit blocks. Capacitive coupling with the block, and thus all of the plurality of semiconductor circuit blocks are similarly capacitively coupled, and all analog characteristics of the plurality of semiconductor circuit blocks are equalized. .

According to the structure of claim 2, when the matrix liquid crystal panel is driven by a plurality of semiconductor integrated circuit devices, vertical stripes are generated at the boundary of the analog output voltage of each semiconductor integrated circuit device of the matrix liquid crystal panel. To be prevented.

[0041]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a schematic plan view of a semiconductor integrated circuit device according to an embodiment of the present invention. In this semiconductor integrated circuit device, as shown in FIG. 1, a large number of vertically elongated semiconductor circuit blocks B having the same configuration that constitute an electric circuit for controlling an analog voltage are formed in a central portion of a horizontally elongated semiconductor substrate Sb.
1, B2, ..., B240 are arranged side by side in a row. Further, the semiconductor circuit blocks B1, B2 of the semiconductor substrate Sb are
, And dummy semiconductor circuit blocks DB1 and DB2 are arranged in parallel on both outer sides of B240.

Each semiconductor circuit block B1, B2, ..., B
An input signal line (not shown) for a digital signal from the outside is formed at one end portion (the lower end portion in the drawing) of 240 in the vertical direction,
An analog signal output signal line (not shown) is formed at the other end (upper end on the paper) in the vertical direction.
It is connected to the liquid crystal cells in each column of the matrix liquid crystal panel.

Further, the dummy semiconductor circuit block DB1,
DB2 is a semiconductor circuit block B1, B2, ..., B24.
The structure is almost the same as that of 0, except that output wiring is not provided, input wiring is provided, digital data is supplied to the dummy semiconductor circuit blocks DB1 and DB2, and semiconductor circuit block B1 and B2, ..., B2
It is operating like 40. Here, in the color liquid crystal panel, since the three horizontal lines correspond to the three colors of R, G, and B, respectively, the dummy semiconductor circuit block DB
1 is supplied with the same digital data as the semiconductor circuit block B3, and dummy semiconductor circuit block DB2 is supplied with the same digital data as the semiconductor circuit block B238.

The configuration other than the above is the same as the conventional example. 2 is a semiconductor circuit block B of the semiconductor integrated circuit device of FIG.
1, B2, ..., B8, ... And a dummy semiconductor circuit block DB1 are enlarged views, C _1-2 is a coupling capacitance between the semiconductor circuit blocks B1 and B2, and C _2-3 is a semiconductor circuit block B2. Coupling capacity between B3, C
_3-4 is the coupling capacitance between the semiconductor circuit blocks B3 and B4, C _4-5 is the coupling capacitance between the semiconductor circuit blocks B4 and B5, and C _5-6 is the semiconductor circuit blocks B5 and B6.
Coupling capacitance between C _6-7 is semiconductor circuit block B
6, B7 is a coupling capacitance, C _7-8 is a coupling capacitance between the semiconductor circuit blocks B7 and B8, and C _DB1 is a semiconductor circuit block B1 and a dummy semiconductor circuit block DB1.
Is the coupling capacity between and.

Each semiconductor circuit block B1, B2, ..., B
The analog characteristics of 8, ... are the coupling capacitances C _1-2 , C
_2-3 , ..., C _7-8 , ..., C DB1 are influenced by the semiconductor circuit blocks B1, B2, ..., B8, ... _Adjacent to both sides and the dummy semiconductor circuit block DB1 and, for example, the semiconductor circuit block B2 other than the both end positions. the coupling capacitance C _1-2, via a C _2-3 2 single semiconductor circuit blocks B
Since they are connected to the semiconductor circuit blocks B1 and B3, they are influenced by the two semiconductor circuit blocks B1 and B3.

On the other hand, the semiconductor circuit at both ends, for example, the right end
Block B1 is coupling capacity C _1-2Through semiconductor
It is connected to the circuit block B2 and has a coupling capacitance C.
_DB1Is connected to the dummy semiconductor circuit block DB1 via
Therefore, the influence of the semiconductor circuit block B2 and the dummy
It is affected by the semiconductor circuit block DB1. Dummy semi-conductor
Body circuit block DB1 except that there is no output wiring
Has the same configuration as the semiconductor circuit blocks B1 to B240.
Therefore, the effect of capacitive coupling is
Blocks B1 to B240 and the dummy semiconductor circuit block
It is considered to be the same as in the case of DB1 and DB2.

As described above, in the semiconductor integrated circuit device of this embodiment, the semiconductor circuit blocks B2 to B239 are capacitively coupled with the semiconductor circuit blocks B1 to B240 which are adjacent on both sides, and the semiconductor circuit blocks B1 and B240 on both ends.
Are semiconductor circuit blocks B2 and B239 adjacent to one side.
And the dummy semiconductor circuit blocks DB1 and DB2 adjacent to each other on the other side, respectively.
1 to B240 have the same degree of capacitive coupling, the semiconductor circuit blocks B1 to B240
All of the circuit patterns are designed to be the same, and the dummy semiconductor circuit blocks DB1 and DB2 on both sides thereof are also designed to be the same as the semiconductor circuit blocks B1 to B240 except for the output wiring.
The analog characteristics of 0 are set to other semiconductor circuit blocks B2 to B
It can be the same as the analog characteristics of 239.

As a result, as in the conventional example, even when one color TFT matrix liquid crystal panel is driven by eight semiconductor integrated circuit devices, it is fatal that vertical stripes appear on the screen of the color TFT matrix liquid crystal panel. Occurrence of specific defects is prevented. According to this semiconductor integrated circuit device,
Dummy semiconductor circuit blocks DB1 and DB2, which have the same structure as the semiconductor circuit blocks B1 to B240, are arranged side by side, except that output wirings are not provided at the outer side positions of the semiconductor circuit blocks B1 to B240. , The semiconductor circuit blocks B1 and B240 at both outer ends are capacitively coupled to the adjacent semiconductor circuit blocks B2 and B239 and the dummy semiconductor circuit blocks DB1 and DB2, respectively, so that all of the semiconductor circuit blocks B1 to B240 are the same. Capacitive coupling to the semiconductor circuit blocks B1 to B24
It is possible to make all the analog characteristics of 0 uniform, and it is possible to eliminate variations in the analog characteristics due to the difference in the formation location in the semiconductor circuit blocks B1 to B240.

In this embodiment, the semiconductor integrated circuit device has 240 semiconductor circuit blocks B1 to B240 arranged side by side, but the number is not limited to the above.

[0050]

According to the semiconductor integrated circuit device of the first aspect, since the dummy semiconductor circuit blocks are arranged in parallel on both outer sides of the plurality of semiconductor circuit blocks, the semiconductor circuit blocks at both outer ends are adjacent to each other. Capacitive coupling with the semiconductor circuit block and dummy semiconductor circuit block means that all of the semiconductor circuit blocks are capacitively coupled in the same way, and all analog characteristics of the semiconductor circuit blocks are uniform. Therefore, it is possible to eliminate variations in analog characteristics due to differences in formation locations in a plurality of semiconductor circuit blocks.

According to the semiconductor integrated circuit device of the second aspect, when the matrix liquid crystal panel is driven by a plurality of semiconductor integrated circuit devices, vertical stripes at boundaries of analog output voltages of the respective semiconductor integrated circuit devices of the matrix liquid crystal panel. Can be prevented.

[Brief description of drawings]

FIG. 1 is a schematic plan view of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is an enlarged view of a main part of the semiconductor integrated circuit device of FIG.

FIG. 3 is a schematic plan view of a conventional semiconductor integrated circuit device.

FIG. 4 is a schematic diagram showing a specific example of a semiconductor circuit block.

FIG. 5 is a circuit diagram showing an example of a specific circuit configuration of a semiconductor circuit block.

6 is an enlarged view of a main part of the semiconductor integrated circuit device of FIG.

FIG. 7 is a schematic view of a state in which a semiconductor integrated circuit device is connected to a color TFT matrix liquid crystal panel.

[Explanation of symbols]

 Sb Semiconductor substrate B1 to B240 Semiconductor circuit block DB1, DB2 Dummy semiconductor circuit block

Claims (2)

[Claims] 1. A plurality of semiconductor circuit blocks having the same structure, which form an electric circuit for controlling an analog voltage, are arranged side by side in a row on a semiconductor substrate, and the semiconductor substrate is provided on both sides of the semiconductor substrate on both outer sides. A semiconductor integrated circuit device, wherein dummy semiconductor circuit blocks are arranged in parallel. 2. The semiconductor integrated circuit device according to claim 1, wherein the electric circuit is a liquid crystal drive circuit for driving liquid crystal cells constituting a matrix liquid crystal panel line by line in a horizontal direction.