JPH08235019A - Instruction table generation method - Google Patents

Abstract

PURPOSE: To provide a method in order to automatically generate an instruction table that can be suitably processed to a general purpose debugger and a general-purpose simulator that are constructed to correspond to the instruction sets of various types of computers by rewriting the instruction table. CONSTITUTION: In the mask data table generation processing 51, 0 is set at the bit position of the corresponding entry of a mask data table corresponding to the character position where a character showing 1 or 0 emerges out of a character pattern in every entry included in an instruction definition body showing the definition of an instruction set and then sets 1 in other cases. In the operation code table generation processing 52, 1 is set at the bit position corresponding to the character position where a character showing 1 emerges out of the character pattern in every entry of the instruction definition body and sets 0 in other cases.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a debugger or a simulator for use in computer program debugging, and more particularly to a general-purpose debugger configured to correspond to a variety of computer instruction sets by rewriting an instruction table, The present invention relates to an instruction table generation method that provides a general-purpose simulator with an instruction table that can be appropriately processed.

[0002]

2. Description of the Related Art Before describing a conventional technique related to instruction table generation, an instruction decoding process in a general configuration of a debugger or a simulator will be described first, and then an instruction decoding process in a general-purpose debugger and a general-purpose simulator will be described. Finally, a conventional instruction table generation method used for a general-purpose debugger and a general-purpose simulator will be described.

First, as shown in FIG. 7, an instruction of a computer which is input to the instruction decoding process is generally composed of one opcode (hereinafter referred to as OPC) field and zero or more operand fields. The OPC field represents the type of instruction, and is defined as, for example, a MOV instruction when bits 4 to 7 are a binary 1101 bit pattern and a NOP instruction when bits 4 to 7 are a binary 1000 bit pattern. It Since all instructions have an OPC field, the instruction type is uniquely specified by extracting the OPC field from the instruction code and determining the bit pattern. The operand field is, for example, M
In the OV instruction, bits 2 and 3 represent the register number of the source register, bits 0 and 1 represent the register number of the destination register, and in the NOP instruction, bits 0 to 4 are defined as unused fields. . In the operand field, the bit number is divided and defined as a register number, a memory address, an immediate value or an unused field for each instruction in this way, and detailed information of the instruction operation is displayed.

The instruction decoding process of the debugger or simulator performs the process for determining the instruction type and the operand from the bit pattern of the instruction as described above. That is, the OPC field is extracted and determined from the instruction code to specify the instruction type, and the operand field is analyzed to obtain detailed information of the instruction operation.

Next, the instruction decoding process in the general-purpose debugger or general-purpose simulator will be described with reference to FIG.

The instruction table including the mask data table and the operation code table (hereinafter referred to as the OPC table) shown in FIG. 8 stores the bit pattern definitions of all the instructions based on the instruction set definition. For example, bit 4
When a MOV instruction in which 7 is 1101 is defined, bits 4 to 7 are set to 1 and other bits are set to 0 in the mask data table.
Is stored, that is, an entry having a value of the binary number 1110000 is stored, and 10000000 is placed in the OPC table at the same entry position. That is, the AND 81 of the value of the mask data table for judging the type of the input instruction and the input instruction is taken, and then the value of the OPC table and the EXOR 82 are taken.

To explain further, a debugger or simulator (including a general-purpose debugger or general-purpose simulator) determines an instruction type in an instruction decoding process, and further extracts an operand field defined for each instruction for each item (entry).・ Perform analysis, for example, input command
The determination result is that the instruction type is MOV and the operands are D0 and D1.

The conventional instruction table generation method manually creates the above-mentioned mask data table and OPC table. Further, no table is defined for operand data, and the extraction / analysis of operand data is performed in the processing for each instruction. It was necessary to create a program to perform.

Although the length of the OPC field may be variable depending on the computer, the same processing can be performed, and the description thereof will be omitted.

[0010]

However, in the method of generalizing the debugger and the simulator by creating the instruction table described above, it takes a lot of time to create the mask data table and the OPC table, and the operand data is different for each instruction. Since it is necessary to program the process of extracting / analyzing, there is a problem that it takes a lot of time to deal with each computer.

SUMMARY OF THE INVENTION Therefore, in view of the above problems, it is an object of the present invention to provide an instruction table generating method that simplifies the instruction set table definition and realizes a general-purpose debugger or a general-purpose simulator.

[0012]

In order to achieve the above-mentioned object, a first instruction table generating method of the present invention uses an instruction definition body expressing the definition of an instruction set as an input and uses a character pattern of the instruction definition body. The mask data table generating process for generating a mask data table used by the instruction decoding process and the OPC table generating process for generating an OPC table are provided. Character representing 1 or 0 from the character pattern of each entry in
Corresponding item (entry) in the mask data table corresponding to the character position where the S code "1" or "0" appears.
In the OPC table generation process, 1 is placed in the corresponding bit position of 0, and 0 in other cases. In the OPC table generation process, 1 is placed at the character position where 1 appears from the character pattern of each item (entry) in the instruction definition body. A process of placing 1 in the corresponding bit position and placing 0 in the other cases is performed.

The second instruction table generating method of the present invention comprises an operand data generating process for generating operand data, and the operand data generating process includes each item in the instruction definition body. This is a process of extracting an operand definition field composed of one or more continuous characters (for example, JIS alphabetic characters) from the (entry) character pattern and generating operand data.

Further, according to the instruction table generating method of the present invention, the mask data table generating process, the operation code table generating process and the operand data generating process are processed in a series of steps for each item of the instruction defining structure, It is desirable to repeatedly process all items of.

[0015]

According to the first aspect of the present invention, the mask data table generation process is performed by the mask data table corresponding to the character position where the character expressing 1 or 0 appears from the character pattern of each item in the instruction definition body. Of 1 in the bit position of the corresponding entry of 0, and 0 in other cases, and the operation code table generation process is performed at the character position where the character representing 1 appears from the character pattern of each item in the instruction definition body. The mask data table and the OPC table are automatically generated based on the definition of the instruction definition body by including the step of placing 1 in the bit position corresponding to, and 0 otherwise.

According to the second aspect of the present invention, the operand data generation process extracts an operand definition field composed of one or more consecutive characters from the character pattern of each item in the instruction definition structure, and By including the step of generating data, the operand data is automatically generated based on the definition of the instruction definition body.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An instruction table generating method according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an instruction table generating process in an embodiment of the present invention. Reference numeral 101 is an instruction definition body, which is a definition body of an instruction set manually created according to a format described later. In the instruction table generation processing of 102, the instruction definition body 101 is input and the instruction table 103 is output. The general-purpose debugger or general-purpose simulator 105 inputs the instruction table 103 and the program to be debugged 104 and displays debug information on the screen 106.
The instruction definition unit 101, the instruction table 103, and the program to be debugged 104 are stored in a disk device, and the instruction table generation process 102, a general-purpose debugger or a general-purpose simulator 105 are processes to be loaded and executed in a computer central processing unit (not shown).

FIG. 2A shows the format of the instruction definition body. In the instruction definition body, each entry is composed of a character string representing the definition of one instruction, and each entry shows the structure of the OPC field and the operand field as shown in FIG. As an example, FIG. 2B shows that when a computer has bits 4 to 7 of a binary 1101 bit pattern, M
OV instruction is a NOP instruction when bits 4 to 7 are bit patterns of binary 1000, and MOV instruction is a register number of the source register with bits 2 and 3, and a register number of the destination register with bits 0 and 1. In the case of the NOP instruction, bits 0 to 3 have the instruction MOV and NOP defined as unused fields.
Corresponding to each, 1101ssdd, 1000 ---
It is shown that it has an entry represented by-.

FIG. 3 outlines the processing of the instruction table generation processing in which the instruction definition body thus created is input and the instruction table, that is, the mask data table, the OPC table, and the generation of the operand data are output. It is a figure.

First, each entry of the input instruction definition structure is searched from the beginning, and 1 is placed at the bit position of the corresponding entry in the mask data table corresponding to the character position where 1 or 0 appears from the character pattern, Place 0 in the other bit positions of the entry. Furthermore, 1 is set in the corresponding entry of the OPC table corresponding to the character position in which 1 appears.
, And 0s in other bit positions of the entry.
The same processing is performed for all the entries of the instruction definition body. In this way, first, the mask data table and the OPC table are generated.

Before explaining how the mask data table and the OPC table are used by a general-purpose debugger or a general-purpose simulator, referring to FIG.
A method of generating operand data will be described.

In FIG. 4, each entry of the input instruction definition is searched from the beginning, and an operand definition field composed of one or more consecutive letters is extracted from the character pattern to generate operand data. An example is shown. The operand definition field is composed of one or more consecutive alphabetic characters and indicates its bit position. In the example of FIG. 4, field names ss and dd are defined, the field ss is indicated by bits 2 and 3, and the field dd is indicated by bits 0 and 1. In the fields ss and dd, a variable ss definition statement and a variable dd definition statement are generated by an operand data generation process described later. Each is a program code for extracting the fields ss and dd from the instruction code, and includes mask data and shift amount.
For example, the mask data required for the field ss is 16
Since the decimal number C0 and the shift amount are 2 and the mask data necessary for the field dd is the hexadecimal number 3 shift amount,
For example, for the C language, two lines of program code (Equation 1) are generated as operand data. Here, inst is the input instruction code shown in FIG.

[0024]

[Equation 1]

The general-purpose debugger or general-purpose simulator refers to an instruction table having a structure such as the mask data table and the OPC table described above in the instruction decoding processing which is a constituent element thereof, and executes an instruction input from the program to be debugged. Parsing, the algorithm is realized by known techniques.

FIG. 5 shows the instruction table generation process 10 of FIG.
2 is a detailed flow chart showing the operation of No. 2, and a mask data table generation for inputting an instruction definition that expresses the definition of the instruction set and generating a mask data table used by the instruction decoding process from the character pattern of the instruction definition Opcode table generation process 52 for creating an opcode table from the process 51 and the character pattern of the instruction definition
And an operand data generation process 53 for generating an operand data used in the instruction decoding process from a character pattern of the instruction definition structure as an input.

First, the index value i is set to 1 (step S501), and it is determined whether i is smaller than the number of entries in the instruction definition body (step S502). When i exceeds the number of entries in the instruction definition field, the process branches to the step of ending the process (S503). Then 1 for index value j
Is set (step S504), and it is determined whether j is smaller than the number of characters in each entry of the instruction definition structure (step S505). When j exceeds the number of characters in each entry of the instruction definition field, i is incremented by 1 (step S
506), the process branches to step S502.

Subsequently, j of the i-th entry of the instruction definition field
It is determined whether the th character is 1 or 0 (step S5
07), if yes, 1 is stored in the i-th bit position of the mask data table (step S508), no
If so, 0 is stored (step S509).

Further, j of the i-th entry of the instruction definition field
It is determined whether the th character is 1 (step S51
0), if yes, store 1 in the i-th bit position of the OPC table (step S511), and if no, 0
Is stored (step S512).

Next, it is judged whether the j-th character of the i-th entry of the instruction definition is an alphabetic character (step S51).
3) If yes, the operand definition field composed of the same alphabetic characters is extracted (S514), and the operand generation process is called (step S515). If no,
It is determined whether it is a'- 'character (step S
516), if no, an undefined character is included in the instruction definition body, and the process branches to the error processing. If yes and the process following step S515 is a process of incrementing j (step S517), the process returns to step S505.

FIG. 6 is a flow chart showing the operation of the operand data generation process. First, a variable name is generated from the character string of the extracted field (step S518), and then a mask data value is generated. (Step S51
9). Specifically, this is calculated as a value in which 1 is given to the bit position corresponding to the alphabetic character of the extracted field and 0 is given to the other bit positions. Next, the shift amount is generated (step S520). Specifically, this is set as the value of the shift amount for shifting the bit position corresponding to the last character position of the extracted field to the least significant bit.

The mask data table, the OPC table, and the operand data can be created by performing the above processing.

In this embodiment, each entry of the instruction definition field is shown to be composed of 8 characters, but it is premised that each instruction has a length of 8 bits or less. However, an entry having a length exceeding 8 characters may be used in correspondence with a bit length exceeding 8 bits.

The code of the characters forming the instruction definition may be other than the JIS code, and the binary number 0,
An arbitrary identifier for indicating the distinction of 1 may be used or configured.

[0035]

As described above, according to the instruction table generating method of the present invention, the instruction table generating process automatically generates the mask data table, the OPC table and the operand data by manually generating the instruction definition body. It can be an instruction table for a general-purpose debugger or a general-purpose simulator. Since it is extremely easy to create the instruction definition body based on the definition of the instruction set of the computer, it becomes possible to easily create the instruction table corresponding to the instruction set of each computer, and the effect is great.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of a computer according to an embodiment of the method of the present invention.

FIG. 2A is a diagram showing a format of an instruction definition body of the embodiment, and FIG. 2B is a diagram showing an example of its entry.

FIG. 3 is a diagram showing a relationship between a mask data table and an OPC table configuration and an instruction definition body of the embodiment.

FIG. 4 is a diagram showing a relationship between a structure of operand data and an instruction definition body in the embodiment.

FIG. 5 is a flowchart showing an instruction table generating process of the embodiment.

FIG. 6 is a flowchart showing an operand data generation process of the same embodiment.

FIG. 7 is a block diagram of computer instructions.

FIG. 8 is a flowchart showing instruction decoding processing in a general-purpose debugger or general-purpose simulator.

[Explanation of symbols]

 101 instruction definition body 102 instruction table generation processing 103 instruction table 104 debugged program 105 general-purpose debugger or general-purpose simulator 106 debugger or simulator screen

Claims (3)

[Claims] 1. A method of generating an instruction table for reference by an instruction decoding process of a debugger or a simulator, wherein an instruction definition representing an instruction set definition is input, and an instruction decoding process is performed from a character pattern of the instruction definition. A mask data table generation process for generating a mask data table used by the above, and an operation code table generation process for generating an operation code table from the character pattern of the instruction definition body, wherein the mask data table generation process is performed by the instruction definition. The step of placing 1 at the bit position of the corresponding entry of the mask data table corresponding to the character position where the character expressing 1 or 0 appears from the character pattern of each item in the body, and 0 otherwise. The operation code table generation process is performed by the character pattern of each item in the instruction definition body. 1 placed in the bit positions corresponding to the character position where the character appears to represent the instruction table generation method comprising the steps of placing a 0 otherwise. 2. A method of generating an instruction table for reference by an instruction decoding process of a debugger or a simulator, wherein an instruction defining body expressing an instruction set definition is input, and an instruction decoding process is performed from a character pattern of the instruction defining body. Operand data generation processing for generating operand data to be used by the operand data generation processing, wherein the operand data generation processing extracts an operand definition field composed of one or more consecutive characters from the character pattern of each item in the instruction definition structure. And an instruction table generating method having a step of generating operand data. 3. The mask data table generating process, the opcode table generating process, and the operand data generating process, wherein the mask data table generating process, the opcode table generating process, and the opcode table generating process are performed for each item of the instruction definition body. 3. The instruction table generation method according to claim 1, wherein the operand data generation processing is processed in a series of steps and is repeatedly processed over all items of the instruction definition body.