JPH08234743A - Integrated circuit for sound processing - Google Patents

Abstract

PURPOSE: To provide an LSI system of optimum constitution to which external memories corresponding to plural function blocks can be connected with a small number of pins. CONSTITUTION: A CPU part 102 and a sound source part 103 in the sound source integrated circuit 101 share a ROM 104 or RAM 105 through a memory control part in the CPU part 102 by using a data bus 111 and an address bus 112. When a sound source part 103 does not output a request signal, the CPU part 102 occupies 1st and 2nd predetermined access timing periods. When the sound source part 103 outputs the request signal, the CPU part 102 occupies the 1st access timing and the sound source part 103 occupies the 2nd access timing. In this case, the CPU part 102 enters a stop state in the 2nd access timing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an acoustic processing integrated circuit for processing an acoustic signal, such as a musical tone generating integrated circuit used in an electronic musical instrument, and more specifically to an external bus from each block in the integrated circuit. The present invention relates to a technique of controlling access to a connected storage device.

[0002]

2. Description of the Related Art Conventionally, in a sound processing system such as a sound generation system for an electronic musical instrument, a general-purpose micro-computer is used for detecting the operation state of a keyboard or a switch, controlling the sound generation, or setting the sound processing such as various effect processing. This is performed by a computer (microcomputer), and acoustic processing such as actual generation of a musical tone waveform or effect processing is performed by a dedicated sound source LSI or DSP (signal processing processor). Also, for example, the sound source L
As a waveform generation method by SI, a waveform read from an external PCM waveform ROM is generally subjected to arithmetic processing such as a filter to form a musical tone waveform. Also, DSP
For effect processing by, R for external delay
It is common to read and write waveform data to and from AM to obtain an effect-processed tone waveform.

Now, due to the recent progress of LSI technology,
It has become possible to integrate a microcomputer and a plurality of functional blocks such as a sound source block on a one-chip LSI.

[0004]

However, even in that case, since a large capacity memory cannot be built in the LSI,
ROM / ROM for microcomputer as external parts
A RAM, a tone generator ROM, a delay RAM, etc. are required. Therefore, if the microcomputer and the sound source block are integrated into one chip as they are, the number of pins of the LSI becomes very large, resulting in an increase in the unit price of the LSI and an increase in the mounting cost. Therefore, conventionally, the programs and data used by the microcomputer have to be stored in the built-in ROM.

As a result, for example, program development needs to be performed by using a prototype, and the development environment is not necessarily good. And, it becomes very difficult to shorten the program development period, which in turn leads to an increase in development cost, and in addition to the risk of unexpected troubles caused by using a prototype, It has a problem that a reliable development schedule cannot be established.

An object of the present invention is to provide an LSI system having an optimum configuration in which an external memory corresponding to each of a plurality of functional blocks can be connected with a small number of pins.

[0007]

The present invention provides an acoustic processing circuit (sound source section 103, 803) for processing acoustic data.
And an acoustic processing integrated circuit (101, 801) containing a microcomputer circuit (CPU section 102, 802) for controlling the acoustic processing circuit. The acoustic processing circuit generates acoustic waveform data by reading the waveform data from the second storage device described later. Alternatively, the acoustic processing circuit further executes acoustic processing or digital filtering processing on the generated acoustic waveform data by reading and writing the waveform data in the second storage device described later.

This integrated circuit has the following memory access control circuit (memory controller units 201 and 9).
01) is built in. That is, in this memory access control circuit, the first memory access timing at which the microcomputer circuit can access the first storage device (ROM 104, RAM 105) connected to the external bus, and the sound processing circuit is connected to the external bus described above. When the second storage device which is the same as or different from the first storage device is not accessed, the microcomputer circuit can access the first storage device, and when the sound processing circuit accesses the second storage device, the sound processing is performed. Managing a second memory access timing at which the circuit can access the second storage device. The memory access control circuit has a second acoustic processing circuit.
When the memory device is not accessed, the control for allocating the memory access to the first memory device by the microcomputer circuit to the first or second memory access timing is executed. Further, the memory access control circuit allocates the memory access to the first storage device by the microcomputer circuit only to the first memory access timing when the sound processing circuit accesses the second storage device, and at the same time, performs the sound processing circuit operation. The memory access to the second storage device is assigned to the second memory access timing, and the control for bringing the microcomputer circuit into the suspended state is executed at the second memory access timing.

According to the configuration of the invention described above, the sound processing circuit and the microcomputer circuit in the integrated circuit can share the external bus via the memory access control circuit.

In this case, the sound source processing circuit can access the external bus when necessary, and when the sound source processing circuit does not access the external bus,
The microcomputer circuit can be made to occupy the external bus.

Therefore, the sound processing circuit and the microcomputer circuit can share the same storage device connected to the external bus, and the system can be configured with a minimum number of parts, and the microcomputer circuit can be used. It is possible to minimize the decrease in the operating efficiency of.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. <First Embodiment> FIG. 1 is an overall configuration diagram of a first embodiment of the present invention.

What is shown as the sound source integrated circuit 101 is an integrated circuit in which the CPU section 102 and the sound source section 103 are formed in one chip. The program data for controlling the operation of the CPU unit 102 includes the address bus 112 and the data bus 1.
It is stored in the ROM 104 connected via 11.

The CPU section 102 reads the parameter data stored in the ROM 104 or the address bus 11 according to the program read from the ROM 104.
2 and the RAM 105 connected to the data bus 111 as a work area, the switch 107 and the keyboard 106 connected to the CPU unit 102 are scanned, and the sound source unit 103 is controlled according to the scanning result.

The tone generator 103 reads the waveform memory data stored in the ROM 104 via the address bus 112 and the data bus 111, and performs signal processing on the waveform memory data to generate musical tone waveform data. Output.

The musical tone waveform data output from the sound source section 103 is converted into an analog musical tone signal by the D / A converter 108, the analog musical tone signal is amplified by the amplifier 109 and then emitted as a musical tone from the speaker 110. .

Here, the ROM 104 and the RAM 105 connected to the address bus 112 and the data bus 111 are
It is shared by the CPU unit 102 and the sound source unit 103. It should be noted that the individual ROMs or RAMs corresponding to the CPU unit 102 and the sound source unit 103 are the address bus 11
2 and the data bus 111 may be connected.

FIG. 2 shows C in the sound source integrated circuit 101 of FIG.
FIG. 3 is a connection diagram of the periphery of a memory controller unit 201 provided in the PU unit 102. In FIG. 2, a portion surrounded by a broken line corresponds to the CPU unit 102 in FIG. 1, and is configured by the MPU unit 202 that performs various arithmetic processes and the like, and the memory controller unit 201 described above.

The MPU (microprocessor unit) unit 202, the memory controller unit 201, and the tone generator unit 103 in FIG. 1 manage an internal address CA managed and generated by the MPU unit 202, an internal data CD, and an internal write signal C.
It is connected via WRB. Further, these blocks operate in synchronization with a common basic clock.

The sound source section 103 is a memory controller section 2
For 01, the waveform memory address WA and the waveform request signal WRQ are output in synchronization with the timing that requires the waveform memory data WD. Then, the sound source unit 103
Receives the waveform memory data WD read from the ROM 104 based on the waveform memory address WA from the memory controller unit 201 and outputs the waveform memory data WD.
Based on, the operation of generating musical tone waveform data is executed.

The MPU section 202 uses the internal address CA, the internal data CD, and the internal write signal CWRB in accordance with the program executed by the MPU section 202 to send a sound generation control command to the sound source section 103, and also to the ROM 104 or the RAM 105. The memory controller unit 201 is operated to access the program data, parameter data, and work data stored in the memory.

The memory controller section 201 is a sound source section 1.
When the waveform request signal WRQ from 03 is not active and the access request of the waveform memory data WD stored in the ROM 104 is not generated, the internal address CA and the internal write signal CWRB output from the MPU unit 202 are output. Use ROM 104 or RA
The internal data CD is read or written to M105.

On the other hand, the memory controller section 201 outputs from the tone generator section 103 at the timing when the waveform request signal WRQ from the tone generator section 103 becomes active and an access request for the waveform memory data WD stored in the ROM 104 is generated. Output waveform memory address W
The waveform memory data WD is read from the ROM 104 using A. At the same time, the memory controller unit 201
Outputs a wait signal WAIT to the MPU unit 202. The MPU unit 202 is in a stopped state (NOP state) while the wait signal WAIT is being output.

The access request operation of the waveform memory data WD performed by the tone generator 103 to the memory controller 201 will be described in detail below. FIG. 3 is a basic operation timing chart of the external address AD output to the address bus 112. FIG. 3A shows the CPU unit 10.
2 is the basic clock φ for operating 2 and address bus 1
The external address AD output to 12 changes in synchronization with the basic clock φ, as shown in FIG.

In FIG. 3 (b), the timing shown as CA corresponds to the timing at which the waveform request signal WRQ is never activated, and the memory controller unit 201 outputs the internal address CA output from the MPU unit 202 as it is to the outside. It is shown that the address is output.

On the other hand, in FIG. 3B, the timing shown as WA corresponds to the timing when the waveform request signal WRQ can be active, and the memory controller section 201 outputs from the sound source section 103 when the waveform request signal WRQ is active. The waveform memory address WA to be output is output as the external address AD. At this timing, the waveform request signal W
When the RQ is not active, the memory controller unit 201 outputs the internal address CA output from the MPU unit 202 as the external address AD.

Then, the timing C shown in FIG.
A and timing WA are alternately reserved in units of two cycles of the basic clock φ. Next, the waveform memory data WD per sound channel in the tone generator 103
The access request operation will be described with reference to FIGS. 4 to 7.

First, in the present embodiment, it is assumed that the maximum number of waveform memory data WD to be accessed at each sampling timing is 4 data for one sound generation channel. The reason for this is as follows.

That is, in the present embodiment, the sound source unit 103
Generates musical tone waveform data based on the DPCM (differential PCM) method. Therefore, the differential waveform data is stored as the waveform memory data WD in the waveform memory area of the ROM 104. Then, the sound source unit 103, for one sound channel, at each sampling timing,
The difference waveform data is read from the ROM 104 and the waveform memory data W
By reading as D and accumulating them sequentially,
Generate musical tone waveform data.

Now, for example, in the waveform memory area of the ROM 104, the difference waveform data DV _n , D _n shown in FIG.
V _{n + 1} , DV _{n + 2} , ... Are stored. And
It is assumed that the value of the musical tone waveform data at the current sampling timing is the value D _now shown in FIG. 7A and the current waveform address (real value) is ad _now . Consider a case where a pitch change that allows the pitch to rise up to 2 octaves occurs in such a state. For example, it is assumed that the step width PD _next shown in FIG. 7A corresponding to a pitch change close to 2 octaves is given to the current waveform address ad _now . In this case, the value of the musical tone waveform data at the next sampling timing is shown in FIG.
It should be the value D _next shown in (a).

To calculate the waveform value D _next , the sound source section 103 calculates the integrated value IV _next and the adjacent integrated value IV _next.
It is necessary to calculate _{next + 1} and perform an interpolation operation on them. Then, the sound source unit 103 outputs the difference waveform data D from the ROM 104 in order to calculate the integrated value IV _next.
It is necessary to sequentially read V _n , DV _{n + 1} , and DV _{n + 2} and sequentially accumulate them in the current waveform integration value IV _now . Further, the sound source unit 103 needs to read out the differential waveform data DV _{n + 3} from the ROM 104 and accumulate it in the waveform integral value IV _next in order to calculate the integral value IV _{next + 1} .

Thus, in the above example, the sound source unit 103
Needs to sequentially read out the four differential waveform data DV _n , DV _{n + 1} , DV _{n + 2} , and DV _{n + 3} from the ROM 104 as waveform memory data WD.

As described above, the tone generator section 103 generates the tone waveform data corresponding to one tone generation channel which allows a pitch change within 2 octaves at the maximum.
It is necessary to access up to four waveform addresses WAD at each sampling timing. Of course, depending on the pitch change, the number of access data for each sampling timing may change between 1 and 4.

The number of access data shown here is not limited to that of the present embodiment, and the method of generating musical tone waveform data in the tone generator 103 is not restricted to the DPCM method. Absent.

FIG. 4 is a block diagram of a waveform address generation block in the tone generator 103, which performs an address generation operation for generating tone waveform data from the difference waveform data.

The current value address OSA and the address increment amount OPI, which are stored in an internal storage means (not shown) and are read out at a timing required, are input to the adder 401. By the addition operation here, the new current value address is calculated and output as the waveform memory address WA.

The address step generator 402 generates the address step value STP by calculating the change amount of the address from the current value address OSA and the waveform memory address WA which is the new current value address.

This address step value STP is sent to the request generator 403 and also to a differential waveform data integration block (not shown) for use in controlling the integration operation.

In the request generator 403, the above-mentioned address step value STP and the tone generation operation state signal CHS transmitted from a tone generation operation state control block (not shown) are used.
From this, the waveform request signal WRQ is generated. The tone generation operation state signal CHS distinguishes between the tone generation channel during the tone generation operation and the tone generation channel during which the tone generation operation is stopped.

5 and 6 show the address step signal S
5 is an operation timing chart showing an access operation by the sound source unit 103 in each state of TP and the tone generation operation state signal CHS.

FIG. 5A shows the sounding operation state signal CH of FIG.
S indicates the tone generation stop state, and the address step value ST
7 is an operation timing chart when P is an arbitrary value. In this case, as shown in FIG. 5A, the waveform request signal WRQ is inactive (low level) at all four reservation timings. As a result, the memory controller unit 201 determines the address value output as the waveform memory address WA from the tone generator unit 103 at all four reservation timings (see FIG. 3B) for the waveform memory address in the external address AD. Ignore and open those reservation timings for the MPU unit 202 as shown as "(CA)" in FIG. 5 (a).

FIG. 5B is an operation timing chart when the tone generation operation state signal CHS indicates the tone generation operation state and the address step value STP is 0 or 1. In this case, since the waveform memory data WD corresponding to the new current value address only needs to be acquired, the waveform memory address WA that is the new current value address is output as shown in FIG. External address A shown
It suffices to secure the single timing WA4 of D. Therefore, as shown in FIG. 5 (b), the waveform request signal W
The RQ becomes active (high level) at the fourth time out of all four reservation timings. As a result, the memory controller unit 201 ignores the address value output as the waveform memory address WA from the tone generator unit 103 at three reservation timings among the four reservation timings for the waveform memory address in the external address AD, Those reservation timings are released for the MPU unit 202 as indicated by "(CA)" in FIG. 5 (b).

FIG. 5C is an operation timing chart when the tone generation operation state signal CHS indicates the tone generation operation state and the address step value STP is 2. In this case, the new current value address and (new current value address −
Each waveform memory data W corresponding to the two addresses of 1)
D is required. Therefore, the integer part of the waveform memory address WA that is the new current value address, and (the integer part-1)
It is sufficient to secure the two timings WA3 and WA4 of the external address AD shown in FIG. Therefore, as shown in Fig. 5 (c),
The waveform request signal WRQ becomes active (high level) at the third and fourth times out of all four reservation timings. As a result, the memory controller unit 201 performs the tone generator unit 1 at two reservation timings of the four reservation timings for the waveform memory address in the external address AD.
The address value output as the waveform memory address WA from No. 03 is ignored, and their reservation timings are shown in FIG.
As indicated by “(CA)” in FIG.
Open for.

The operation of subtracting the integer part address is
It is executed in the memory controller unit 201 of FIG. FIG. 6D is an operation timing chart when the tone generation operation state signal CHS indicates the tone generation operation state and the address step value STP is 3. In this case, each waveform memory data WD corresponding to three addresses of the new current value address, (new current value address-1) and (new current value address-2) is required. Therefore, the external address shown in FIG. 6D for outputting the integer part, (the integer part-1), and (the integer part-2) of the waveform memory address WA which is the new current value address, respectively. It suffices to secure the timings WA2, WA3, WA4 for three times of AD. Therefore, as shown in FIG. 6 (d), the waveform request signal WRQ is 2 out of 4 reserved timings.
Active (high level) on the 3rd and 4th times
Becomes As a result, the memory controller unit 201 ignores the address value output as the waveform memory address WA from the sound source unit 103 only at the first reservation timing of the four reservation timings for the waveform memory address in the external address AD, The reservation timing,
As indicated by "(CA)" in FIG. 6 (d), the MPU
Open for part 202.

FIG. 6 (e) is an operation timing chart when the tone generation operation state signal CHS indicates the tone generation operation state and the address step value STP is 4. In this case, the new current value address and (new current value address −
Each waveform memory data WD corresponding to four addresses of 1), (new current value address-2) and (new current value address-3) is required. Therefore, the integer part of the waveform memory address WA, which is the new current value address, (the integer part-
1), (integer part-2) and (integer part-3), respectively, to output four timings WA1, WA2, WA3, WA of the external address AD shown in FIG. 6 (e).
All 4 need to be secured. Therefore, as shown in FIG. 6 (e), the waveform request signal WRQ becomes active (high level) at all four reservation timings. As a result, the memory controller unit 201 causes the tone generator unit 103 to use all four reservation timings for the waveform memory address in the external address AD.

As described above, the waveform memory data WD can be read into the tone generator section 103 with a minimum weight for the CPU section 102. <Second Embodiment> FIG. 8 is an overall configuration diagram of a second embodiment of the present invention. The configuration of FIG. 8 is different from that of the first embodiment of FIG. 1 in that a sound source integrated circuit 801 (corresponding to the sound source integrated circuit 101 of FIG. 1) includes an effector in addition to a CPU unit 802 and a sound source unit 803. The unit 804 is built in, and the CPU unit 802 and the sound source unit 803 have the function of controlling the effector unit 804 in addition to the functions of the CPU unit 102 and the sound source unit 103 of FIG. 1, respectively. In FIG. 8, the parts with the same numbers as in FIG. 1 have the same functions as in FIG.

Program data for controlling the operation of the CPU section 802 is stored in the ROM 104 connected via the address bus 112 and the data bus 111. CP
The U unit 802 reads the parameter data stored in the ROM 104 according to the program read from the ROM 104, or the address bus 112 and the data bus 1
The switch 8 connected to the CPU section 802 while accessing the RAM 105 connected to 11 as a work area.
07, the keyboard 106 is scanned, and the sound source unit 803 and the effector unit 804 are controlled according to the scanning result.

The tone generator 803 reads the waveform memory data stored in the ROM 104 via the address bus 112 and the data bus 111, and executes signal processing on the waveform memory data to generate musical tone waveform data. Output.

The effector section 804 has the address bus 11
2 and the work memory data are read from or written to the delay processing area in the RAM 105 connected to the data bus 111, the acoustic effect is added to the musical tone waveform data generated by the sound source unit 803. Then, the musical tone waveform data to which the acoustic effect is added is converted into an analog musical tone signal by the D / A converter 108, and the analog musical tone signal is amplified by the amplifier 1.
After being amplified at 09, the speaker 110 emits a musical sound.

Here, the ROM 104 connected to the address bus 112 and the data bus 111 is shared by the CPU unit 802 and the sound source unit 803, and the RAM 105 is also C.
It is shared by the PU unit 802 and the effector unit 804. An individual ROM or RA corresponding to each of the CPU unit 802, the sound source unit 803, and the effector unit 804.
M may be connected to the address bus 112 and the data bus 111.

FIG. 9 shows C in the sound source integrated circuit 801 of FIG.
FIG. 3 is a connection diagram around the memory controller unit 201 provided in the PU unit 802. The configuration of FIG. 9 is different from the configuration of the first embodiment of FIG. 2 in that the memory controller unit 901 and the MPU unit 902 in the CPU unit 802 respectively include the memory controller unit 201 and the MPU unit 2 of FIG.
In addition to the function of 02, it has a function of controlling the effector unit 804. In FIG. 9, signals having the same numbers as in FIG. 2 have the same functions as in FIG.

The MPU section 902, the memory controller section 901, the sound source section 803 and the effector section 8 in FIG.
Reference numeral 04 denotes an internal address CA managed and generated by the MPU unit 902, internal data CD, and an internal write signal CWRB.
Connected through. Further, these blocks operate in synchronization with a common basic clock.

Memory controller section 90 of sound source section 803
The access operation for 1 is the same as the access operation for the memory controller unit 201 of the tone generator 103 in the first embodiment.

The effector unit 804 synchronizes with the memory controller unit 901 at the timing when the work memory data ED needs to be accessed, and the work memory address EA, the effect request signal ERQ, and the effect write signal at the time of write access. The signal EWR is output. The effector unit 804 inputs / outputs the work memory data ED to / from the RAM 105 based on the work memory address EA to / from the memory controller unit 901, and based on the work memory data ED, tone waveform data The action of adding the sound effect to is executed.

The MPU section 902 sends a control command to the tone generator section 803 and the effector section 804 using the internal address CA, the internal data CD, and the internal write signal CWRB according to the program executed by the MPU section 902. An operation of accessing the program data, the parameter data, and the work data stored in the ROM 104 or the RAM 105 is performed on the memory controller unit 901.

The memory controller section 901 is a sound source section 8
03 waveform request signal WRQ is inactive and waveform memory data WD stored in ROM 104
Access request has not occurred, and the effector unit 8
The effect request signal ERQ from 04 is inactive and the work memory data ED is sent to the RAM 105.
At the timing when no access request of
Using the internal address CA and the internal write signal CWRB output from the U unit 902, the ROM 104 or the RAM 105
The internal data CD is read or written with respect to.

On the other hand, at the timing when the waveform request signal WRQ from the tone generator 803 becomes active and the access request for the waveform memory data WD stored in the ROM 104 is issued, the memory controller 901 outputs from the tone generator 803. Output waveform memory address W
The waveform memory data WD is read from the ROM 104 using A. At the same time, the memory controller unit 901
Outputs a wait signal WAIT to the MPU unit 902. The MPU unit 902 is in a stopped state (NOP state) while the wait signal WAIT is being output.

Similarly, the memory controller section 901 is
Effect request signal E from the effector unit 804
At the timing when the RQ is activated and the access request for the work memory data ED to the RAM 105 is generated, the work memory address EA output from the effector unit 804 is used to read or write the work memory data ED to the RAM 105. To do. At the same time, the memory controller unit 901 causes the MPU unit 902 to
A wait signal WAIT is output to. MPU section 902
Is NOP while the wait signal WAIT is being output.
It becomes a state.

The sound source section 803 and the effector section 8 will be described below.
The access request operation of the waveform memory data WD performed by the memory 04 to the memory controller unit 901 will be described in detail.

FIG. 10 is a basic operation timing chart of the external address AD output to the address bus 112 regarding the access operation of the tone generator section 803 and the effector section 804.

The operation timing chart regarding the sound source section 803 of FIG. 10A is the same as that of FIG. 3 described in the first embodiment. The effector section 804 of FIG.
The operation timing chart is the same as that of the sound source unit 803.

That is, in FIG. 10B, the timing shown as CA is the effect request signal ERQ.
Indicates that the memory controller unit 901 outputs the internal address CA output from the MPU unit 902 as it is as the external address AD, corresponding to the timing at which it is never activated.

On the other hand, in FIG. 10B, the timing shown as EA is the effect request signal ERQ.
Corresponding to the timing at which the memory controller unit 901 can be activated, the effect request signal ERQ
Indicates that the work memory address EA output from the effector unit 804 is output as the external address AD when is active. At this timing, when the effect request signal ERQ is not active, the memory controller section 901 outputs the internal address CA output from the MPU section 902 as the external address AD.

The timing CA and the timing WA shown in FIG. 10B are alternately reserved in units of two cycles of the basic clock φ. The timing WA corresponding to the waveform request signal WRQ in FIG. 10 (a) and the timing EA corresponding to the effect request signal ERQ in FIG. 10 (b) are mutually adjusted by the sound source unit 803 and the effector unit 804 of FIG. , They do not overlap.

Next, the access request operation of the waveform memory data WD per tone generation channel in the tone generator 803 is the same as that described above with reference to FIGS. 4 to 7 in the description of the first embodiment. .

Next, the access request operation of the work memory data ED in the effector section 804 will be described with reference to FIGS. 11 and 12. First, the maximum number of work memory data ED to be accessed at each sampling timing for one sound channel is the sound source unit 803.
As in the case of accessing the waveform memory data WD by, the data is 4 data.

FIG. 11 is a diagram showing a first example of the access operation by the effector section 804. The first example is an example in which the effector unit 804 executes a well-known sound addition process called a delay process. By this sound addition processing, an echo effect or a reverb effect can be added to the musical tone waveform data. First, in FIG. 11A, the delay unit 1101 is realized as a delay processing area in the RAM 105. The effector unit 804 is the RAM 1
After writing the work memory data ED in the delay unit 1101 in 05, the output (R) and the output (L) are read as the work memory data ED at two timings delayed in time, and one of the read outputs (R ) Is added to the input musical tone waveform data by the addition process shown as the addition unit 1103, and the addition result is sent to the delay unit 1101 as work memory data ED. Perform the write operation again.

Therefore, in the first example, the effector section 804 performs two read accesses and one write access to the RAM 105 for each sounding channel at each sampling timing. Therefore, as shown in FIG. 11B, the effect request signal ERQ is active (high level) at the first timing EA1 and the second timing EA2 for read access among all the four reserved timings. Level), the work memory address EA is output to the address bus 112 as the external address AD, and at the fourth timing EA4, the effect request signal ERQ and the effect write signal EWR are both active (high level).
And the work memory address EA becomes the external address A.
The effect write signal EWR is output as D to the address bus 112, and is also output to the RAM 105 as an external write signal WRB (see FIG. 8). Then, the memory controller unit 201 selects 3 out of 4 reservation timings for the work memory address in the external address AD.
The address value output as the work memory address EA from the effector unit 804 is ignored only at the reservation timing EA3 for the first time, and those reservation timings are set as MPU as shown by “(CA)” in FIG. 11B.
Open for part 202.

FIG. 12 is a diagram showing a second example of the access operation by the effector section 804. This second example is similar to the case of the first example of FIG.
4 is an example of the case where delay processing is executed. First, FIG.
In 2 (a), the delay unit 1201 is realized as a delay processing area in the RAM 105, as in the case of the first example. Then, the effector unit 804 writes the work memory data ED in the delay unit 1201 in the RAM 105 and then outputs the feedback output, the output (R), and the output (L) at three timings delayed in time. At the same time as reading out as the memory data ED, a multiplication process shown as a multiplication unit 1202 is executed for the feedback output, the multiplication result is added to the input musical tone waveform data by an addition process shown as an addition unit 1203, and the addition result is obtained. Work memory data ED is added to the delay unit 1201.
And write it again.

Therefore, in the second example, the effector section 804 makes three read accesses and one write access to the RAM 105 for each sounding channel at each sampling timing. Therefore, as shown in FIG. 12 (b), the effect request is made at the first timing EA1, the second timing EA2, and the third timing EA3 for read access among all the four reserved timings. The signal ERQ becomes active (high level), the work memory address EA is output to the address bus 112 as the external address AD, and at the fourth timing EA4, the effect request signal ERQ and the effect write signal EWR are both active (high level). ), The work memory address EA is used as the external address AD on the address bus 11
2, and the effect write signal EWR is output to the RAM 105 as the external write signal WRB (see FIG. 8). Therefore, the memory controller unit 201
4 for work memory address in external address AD
The effector unit 804 is caused to use all the reservation timings of the times.

As described above, also in the second embodiment, with the minimum weight for the CPU section 802,
The tone generator 803 reads the waveform memory data WD from the ROM 104.
Can be read, and in parallel with this, the effector unit 804 stores the work memory data ED in the RAM 105.
Can be accessed. <Third Embodiment> Next, a third embodiment of the present invention will be described.

The configuration of the third embodiment of the present invention is the same as the configuration of the first embodiment of the present invention shown in FIGS. 1, 2 and 4. In this embodiment, the sound source unit 1
03 reads the waveform memory data stored in the ROM 104 via the address bus 112 and the data bus 111 and executes digital filtering processing on the waveform memory data to generate and output musical tone waveform data.

First, the basic operation timing chart of the external address AD output to the address bus 112 in the third embodiment is the same as that shown in FIG. 3 described in the first embodiment.

First, in the present embodiment, it is assumed that the maximum number of waveform memory data WD to be accessed at each sampling timing is 6 data for one sound generation channel. Of these, 4 data are data for reproducing musical tone waveform data. In the third embodiment, as in the case of the first embodiment, the sound source unit 103 uses the DPCM
Musical tone waveform data is generated based on the (differential PCM) method. Therefore, as described above in the description of the first embodiment (see FIG. 7), the tone generator 103 needs to sequentially read the four differential waveform data from the ROM 104 as the waveform memory data WD. The remaining 2 data are for a delay register (read 1 data, write 1 data) of a digital filter described later.

As the tone reproduction system, various other systems can be adopted. Here, the digital filter function provided in the sound source unit 103 will be described. FIG.
First realized by the sound source unit 103 in the third embodiment
It is a functional block diagram showing the digital filter function of.

In the figure, the block shown as "Z ^-1 " has a delay register function to delay the input data by one sampling time. Further, A and B are multiplication coefficients and take positive and negative values, and the triangular blocks corresponding to them have a multiplier function.

Although not shown, when this multiplier function executes fixed-point arithmetic, a clipper function is required to perform a predetermined process when overflow or underflow occurs.

FIG. 14 is an operation timing chart (No. 1) showing an access operation to the RAM 105 used as the delay register function constituting the digital filter function shown in FIG.

FIG. 14A shows the sounding operation state signal C of FIG.
6 is an operation timing chart in the case where HS indicates a sound generation operation stopped state. In this case, as shown in FIG. 14A, the read request signal RQ _r and the write request signal RQ which are the waveform request signals WRQ.
_w is inactive (low level) at all two reservation timings. As a result, the memory controller unit 201 performs all the two reservation timings for the waveform memory address in the external address AD (see FIG. 3).
(b)), the address value output as the waveform memory address WA from the sound source unit 103 is ignored, and the reservation timings thereof are indicated by “(CA)” in FIG. Open for 202.

The operation timing chart of FIG. 14 (a) is not limited to the sound generation stopped state as described above.
This operation state is shown when the digital filter is selected to be invalid even during the sounding operation in the sound source system in which the digital filter can be enabled / disabled for each sounding channel.

FIG. 14B is an operation timing chart in the case where the tone generation operation state signal CHS indicates the tone generation operation state. The read request signal RQ _r becomes active at the first allocation timing, and the write request signal RQ _w becomes active at the next allocation timing.

As a result, the memory controller unit 201
Outputs the digital filter external memory address WAf as the external address AD, and sets the external write signal WRB to the write instruction state at the timing when the write request signal RQ _w becomes active.

The operation timing chart shown in FIG. 14 (b) is not limited to the sounding operation state as described above, and the sounding operation is being performed in the sound source system in which the enable / disable of the digital filter can be selected for each sounding channel. This operating state is shown when the digital filter is selected to be effective in.

The configuration of the first digital filter function described above is a configuration having only one delay register as shown in FIG. 13, but the number of delay registers is not limited to one. .

FIG. 15 is a functional block diagram showing a second digital filter function realized by the sound source unit 103 in the third embodiment. In this figure, the two blocks shown as "Z ^-1 " have the same delay register function as in the case of FIG. Further, A to D are multiplication coefficients and take positive and negative values, and the triangular blocks corresponding to them have a multiplier function. The configuration of FIG. 15 differs from the configuration of FIG. 13 in that the number of delay stages is two.
As a result, it is possible to perform filtering with sharper cutoff characteristics.

FIG. 16 is an operation timing chart (No. 2) showing an access operation to the RAM 105 used as the delay register function constituting the digital filter function shown in FIG. This access operation example is
Both delay register functions shown in FIG. 15 are RAM
This is the case where it is configured on 105. That is, the sound source unit 103 does not have the substance of the delay register function.

FIG. 16A shows the sounding operation state signal C of FIG.
6 is an operation timing chart in the case where HS indicates a sound generation operation stopped state. In this case, as shown in FIG. 16A, the read request signal RQ _r and the write request signal RQ which are the waveform request signals WRQ.
_w is inactive (low level) at all four reservation timings. As a result, the memory controller unit 201 ignores the address value output as the waveform memory address WA from the tone generator unit 103 at all four reservation timings for the waveform memory address in the external address AD, and sets those reservation timings. , As indicated by “(CA)” in FIG.
Open for the MPU unit 202.

The operation timing chart of FIG. 16 (a) is not limited to the sound generation stopped state as described above.
This operation state is shown when the digital filter is selected to be invalid even during the sounding operation in the sound source system in which the digital filter can be enabled / disabled for each sounding channel.

FIG. 16B is an operation timing chart in the case where the tone generation operation state signal CHS indicates the tone generation operation state and two delay register functions are used. The read request signal RQ _r becomes active at the first allocation timing, and the write request signal RQ _w becomes active at the next allocation timing.

As a result, the memory controller unit 201
Outputs the external memory address WAf1 and WAf2 digital filter sequentially alternately as the external address AD, at the timing when the write request signal RQ _w becomes active, the external write signal WRB to the state of the write instruction.

The operation timing chart shown in FIG. 16 (b) is not limited to the sounding operation state as described above, and the sounding operation is performed in the sound source system in which the enable / disable of the digital filter can be selected for each sounding channel. This operating state is shown when the digital filter is selected to be effective in.

FIG. 16 (c) is an operation timing chart in the case where the tone generation operation state signal CHS indicates the tone generation operation state and only one delay register function is used. The read request signal RQ _r becomes active at the first allocation timing, and the write request signal RQ _w becomes active at the next allocation timing.

As a result, the memory controller unit 201
Outputs only the digital filter external memory address WAf1 as the external address AD, and sets the external write signal WRB to the write instruction state at the timing when the write request signal RQ _w becomes active.

Furthermore, the memory controller section 201 ignores the address value output as the digital filter address from the tone generator section 103 at all two unused reservation timings for the digital filter in the external address AD, and The reservation timing of Figure 16 (c)
As indicated by “(CA)” in FIG.
Open for.

The operation timing chart shown in FIG. 16 (c) is not limited to the sounding operation state as described above, and the sounding system is in operation in the sound source system in which the enable / disable of the digital filter can be selected for each sounding channel. This operating state is shown when the digital filter is selected to be effective in.

The configuration of the second digital filter function described above is a configuration having only two delay registers as shown in FIG. 15, but the number of delay registers is not limited to two. .

FIG. 17 is an operation timing chart (No. 3) showing an access operation to the RAM 105 used as the delay register function constituting the digital filter function shown in FIG. This access operation example is
One of the two delay register functions shown in FIG. 15 is configured on the RAM 105 and the other one is built in the sound source unit 103 as a real register.

In this case, the RAM 103 is accessed by one delay register function. Therefore, the reservation timing for accessing the external memory is once for each of read and write, that is, only twice in total.

FIG. 17A shows the sounding operation state signal C of FIG.
6 is an operation timing chart in the case where HS indicates a sounding operation stopped state or the sounding operation state signal CHS indicates a sounding operation state and two delay register functions are used. In this case, as shown in FIG. 17A, the read request signal RQ _r and the write request signal RQ which are the waveform request signals WRQ.
_w is inactive (low level) at all two reservation timings. As a result, the memory controller unit 201 ignores the address value output as the waveform memory address WA from the tone generator unit 103 at all the two reservation timings for the waveform memory address in the external address AD, and sets those reservation timings. , M as shown as “(CA)” in FIG.
Open for PU unit 202.

The operation timing chart of FIG. 17 (a) is not limited to the sound generation stopped state as described above.
This operation state is shown when the digital filter is selected to be invalid even during the sounding operation in the sound source system in which the digital filter can be enabled / disabled for each sounding channel.

FIG. 17B is an operation timing chart in the case where the tone generation operation state signal CHS indicates the tone generation operation state and two delay register functions are used. The read request signal RQ _r becomes active at the first allocation timing, and the write request signal RQ _w becomes active at the next allocation timing.

As a result, the memory controller unit 201
Outputs the digital filter external memory address WAf as the external address AD, and sets the external write signal WRB to the write instruction state at the timing when the write request signal RQ _w becomes active.

Note that the operation timing chart shown in FIG. 17 (b) is not limited to the sounding operation state as described above, but the sounding operation is performed in the sound source system in which the enable / disable of the digital filter can be selected for each sounding channel. This operating state is shown when the digital filter is selected to be effective in.

[0104]

According to the present invention, the sound processing circuit and the microcomputer circuit in the integrated circuit can share the external bus via the memory access control circuit. Therefore, it becomes possible to hold the data required for each with a small number of pins in an external large-capacity memory.

In this case, since the program data used by the microcomputer circuit can be stored in the external memory, it is possible to improve the verification accuracy and shorten the development period during software development.

Furthermore, according to the present invention, when the tone generator processing circuit does not access the external bus, the microcomputer circuit can occupy the external bus. It is possible to limit it.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of a first embodiment.

2 is an internal connection diagram of the sound source integrated circuit 101. FIG.

FIG. 3 is a basic operation timing chart of an external address AD according to the first embodiment.

FIG. 4 is a configuration diagram of a waveform address generation block according to the first embodiment.

FIG. 5 is an operation timing chart (No. 1) showing an access operation by the sound source unit 103 according to the first embodiment.
Is.

FIG. 6 is an operation timing chart (No. 2) showing an access operation by the sound source unit 103 according to the first embodiment.
Is.

FIG. 7 is an explanatory diagram of the number of access requests for waveform memory data.

FIG. 8 is an overall configuration diagram of a second embodiment.

9 is an internal connection diagram of a sound source integrated circuit 801. FIG.

FIG. 10 is an external address AD according to the second embodiment.
3 is a basic operation timing chart of the above.

FIG. 11 is an explanatory diagram (1) of an access operation by the effector unit 804.

FIG. 12 is an explanatory diagram (No. 2) of the access operation by the effector unit 804.

FIG. 13 is a functional block diagram of a first digital filter realized in the third embodiment.

FIG. 14 is an operation timing chart (No. 1) showing an access operation by the sound source unit 103 according to the third embodiment.

FIG. 15 is a functional block diagram of a second digital filter realized in the third embodiment.

FIG. 16 is an operation timing chart (No. 2) showing the access operation by the sound source unit 103 according to the third embodiment.

FIG. 17 is an operation timing chart (No. 3) showing an access operation by the sound source unit 103 according to the third embodiment.

[Explanation of symbols]

 101, 80 1 Sound source integrated circuit 102, 802 CPU section 103, 803 Sound source section 104 ROM 105 RAM 106 Keyboard 107 Switch 108 D / A converter 109 Amplifier 110 Speaker 111 Data bus 112 Address bus 201, 901 Memory controller section 202, 902 MPU Section 401 adder 402 address step generator 403 request generator 804 effector section

Claims (4)

[Claims] 1. An acoustic processing integrated circuit comprising an acoustic processing circuit for processing acoustic data and a microcomputer circuit for controlling the acoustic processing circuit, wherein the microcomputer circuit is connected to an external bus. The first memory access timing at which the storage device can be accessed, and the microcomputer when the sound processing circuit is not connected to the second storage device which is connected to the external bus and is the same as or different from the first storage device. A second memory access timing at which the sound processing circuit can access the second storage device when the circuit can access the first storage device and the sound processing circuit accesses the second storage device. , When the acoustic processing circuit is not accessing the second storage device, A control for allocating memory access to the first storage device by the computer circuit to the first or second memory access timing is executed, and when the sound processing circuit accesses the second storage device, the microcomputer circuit executes the control. The memory access to the first storage device is assigned only to the first memory access timing, and the memory access to the second storage device by the acoustic processing circuit is assigned to the second memory access timing. An acoustic processing integrated circuit, comprising a memory access control circuit for executing a control for bringing the microcomputer circuit into a stopped state at the memory access timing. 2. The integrated circuit for acoustic processing according to claim 1, wherein the acoustic processing circuit generates acoustic waveform data by reading the waveform data from the second storage device. 3. The acoustic processing circuit further executes acoustic processing on the generated acoustic waveform data by reading and writing the waveform data to and from the second storage device. The integrated circuit for acoustic processing according to claim 2. 4. The acoustic processing circuit further executes digital filtering processing on the generated acoustic waveform data by reading and writing the waveform data to and from the second storage device. The integrated circuit for acoustic processing according to claim 2.