JPH0823280A - D/a converter device - Google Patents

Abstract

PURPOSE:To effectively attenuate high frequency component included in a digital signal by outputting a signal which is average-moved with respect to the digital input signal of one bit in the constitution of delaying or inverting one of the control signals of a switch. CONSTITUTION:The switch 11 connects with the side of (a), namely connects the one terminal of a capacitor 13 to a reference voltage source when a control signal phi1 is one and connects with a ground side (b) when phi1d is zero. On the other hand, a switch 12 connects with the side of (a) when a control signal phi2 is one and with the ground side (b) when phi2 is zero. Then, the control signal phi1d is delayed by half synchronization of the control signal phi2. Thereby the analog output signal of an integration circuit 16 becomes a code contrary to the output signal of the switch 11. Namely, the analog output signal of the analog integration circuit 16 is obtained by calculating the running mean of the last two values of the digital input signal and inverting a code. Consequently, the frequency characteristic of an output amplitude attenuates largely near Nyquist frequency.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a D / A (digital / analog) converter for converting a digital signal into an analog signal, and more particularly to a D / A converter using a switched capacitor circuit.
The present invention relates to an A / A converter.

[0002]

2. Description of the Related Art As one of D / A converters, a D / A converter applying a switched capacitor circuit is known. A conventionally reported D / A converter of this system will be described with reference to FIG. Regarding this technology, "Radio Technology (Radio Technology Co., Ltd.) May 1991 pp.142-14
7 ”has the description.

FIG. 5 is a circuit diagram showing an example of a conventional D / A converter. 11 and 12 are switches with three terminals,
The connection is switched by control signals φ1 and φ2, respectively. Reference numerals 13 and 14 are capacitors, and 15 is an operational amplifier. The capacitor 14 is connected between the inverting input terminal and the output of the operational amplifier 15, and the non-inverting input terminal of the operational amplifier 15 is connected to the ground. The capacitor 14 and the operational amplifier 15 form an inverting output type analog integrating circuit 16. .

The switch 11 connects the "a" side when the control signal φ1 is "1", that is, one terminal of the capacitor 13 is connected to the reference voltage source, and the "b" side when φ1 is "0", that is, the ground. Connect to. For the sake of explanation, it is assumed here that the reference voltage source has a positive potential with respect to the ground potential. The switch 12 connects the "a" side, that is, the other terminal of the capacitor 13 to the integrating circuit 16 when the control signal φ2 is "1",
When φ2 is "0", it is connected to the "b" side, that is, the ground. As described above, the so-called switched capacitor circuit is configured, and by changing the control signal φ1 in response to the 1-bit digital input signal, the D / A
It is supposed to do the conversion. The output of the integrating circuit 16 is D
It becomes the analog output of the / A converter.

Next, the operation of the D / A converter shown in FIG. 5 will be described in more detail with reference to FIGS. 6 and 2. Figure 6
Shows four connection states of the switches 11 and 12 of the D / A conversion device of FIG. 5, where “+1” is selected by the combination of (a) and (b), and “+1” is selected by the combination of (c) and (d). "-
1 "is output. Figure 2 (here (1)
(2), (3) and (4) are used to show a timing chart of each part of the D / A conversion device of FIG.

First, in FIG. 6A, φ1 = "1" and φ2 = "0", and the capacitor 13 is charged by the reference voltage source.
Next, in the case of (b), φ1 = “0” and φ2 = “1”, and since the switch 11 is connected to the ground, the other terminal of the capacitor 13 has a charge of the opposite sign to the reference voltage source with respect to the ground. Is output to the integrating circuit 16. Since the integrating circuit 16 is of the inverted output type, the sign of the charge is inverted again to obtain a positive output with respect to the ground. The output at this time is "+1".
Will be described below.

Further, in (c), φ1 = "0" and φ2 = "0", and both terminals of the capacitor 13 are connected to the ground and discharged. Next, in the case of (d), φ1 = “1” and φ2 = “1”, and the switch 11 is connected to the reference voltage source. However, since the capacitor 13 is discharged in advance, the other terminal of the capacitor 13 is the reference voltage source. The charge having the same sign as is output to the integrating circuit 16. Since the integrating circuit 16 is an inverting output type, a negative output with respect to the ground is obtained at this time, and "-1" is output.

Attention is paid to the switch 12 as shown in FIG.
The combination of (b), (c) and (d) starts with "b".
Then, the control signal φ2 is connected to "a" and has a common operation, so that the control signal φ2 may be any signal that periodically repeats "0" and "1".

When attention is paid to the switch 11, (a)
In the combination of (b), the connection order of "a" and "b" is opposite to that of the switch 12, and in the combination of (c) and (d), it is the same as that of the switch 12. Therefore, the value of φ1 may be the exclusive OR of the 1-bit digital input signal and φ2. By doing this, when the digital input signal is "1", "+1" becomes
It constitutes a 1-bit D / A converter that outputs "-1" when it is "0".

The above operation will be described with reference to FIG.
The 1-bit digital input signal of
~ Input as shown at t8. The control signal φ2 of (3) is
As described above, the signal may be any signal that periodically repeats "0" and "1", so that it is a square wave with a duty ratio of 50% as shown in the figure. The control signal φ1 of (4) is the exclusive OR of (1) and (3) as described above. Therefore, the output at this time is obtained as shown in the analog output signal of (2).

[0011]

However, in the configuration shown in FIG. 5, since the 1-bit digital input signal is D / A converted as it is, the high frequency component contained in the input is also converted as it is to the analog output signal. For this reason,
For example, the operational amplifier 15 of the integrating circuit 16 is required to operate at high speed, which is a practically difficult problem.

In particular, when a noise-shaped signal is used as a 1-bit digital signal, only a low frequency component is required as an analog output signal and a high frequency component is not required, and the conventional D / A conversion device can obtain such a signal. The high-frequency component of the analog output signal
A method such as removal using a (low pass filter) has been used. That is, the conventional D / A conversion device has a problem that high-speed operation of the circuit element is required to perform D / A conversion of unnecessary high frequency components.

The present invention solves the above-mentioned problems of the prior art by a D / D which has a simple structure and which attenuates high frequency components contained in a 1-bit digital input signal and does not require high speed operation of the integrating circuit 16 and the like. An object is to provide an A converter.

[0014]

To achieve this object, a D / A converter of the present invention comprises a capacitor, first and second switches, and an integrating circuit, and the first switch is 1 One terminal of the capacitor is connected to a reference voltage source or ground corresponding to the digital input signal of the bit, and the second switch alternately connects the other terminal of the capacitor to the input of the integrating circuit or ground, and
The first corresponding to the 1-bit digital input signal
The operation of the switch is shifted by a half cycle from the cycle of the digital input signal, and the output of the integration circuit is an analog output signal.

Further, the D / A converter of the present invention comprises a capacitor, first and second switches, and an integrating circuit, the first switch corresponding to one bit of the digital input signal and one of the capacitors. The terminal is connected to a reference voltage source or ground, the second switch alternately connects the other terminal of the capacitor to the input of the integrating circuit or ground, and the operation of the second switch is determined by the cycle of the digital input signal. The output of the integration circuit is an analog output signal so that it is shifted by a half cycle.

Further, the D / A converter of the present invention comprises a plurality of the capacitors and the first switches connected in the same connection, and the other terminals of the capacitors are all connected to the second switch. The sum of the conductive admittances of the first switches is equal to the conductive admittance of the second switch.

[0017]

With the above-described structure, the present invention has an extremely simple structure in which one of the control signals is delayed or inverted.
Since a signal obtained by performing a moving average on a 1-bit digital input signal can be output, high-frequency components included in the digital input signal are effectively attenuated, and elements such as an integrating circuit do not need to operate at high speed. Such a D / A converter can be realized.

Further, according to the present invention, when the input is a plurality of bits, a plurality of switched capacitor circuits sharing the second switch are used, and the sum of the admittances when the plurality of first switches are conductive. , By making it equal to the admittance when the second switch is conducting,
It is possible to realize a circuit having a time constant equivalent to the case where the D / A converter is configured without sharing the second switch. Further, by sharing the second switch, it is possible to minimize the noise generated at the time of switching and to avoid the noise and the characteristic change due to the time mismatch of switching.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of a D / A converter according to the present invention. In FIG. 1, 11 and 12 are switches with three terminals, and control signals φ1d and φ2, respectively.
The connection is switched by. Reference numerals 13 and 14 are capacitors, and 15 is an operational amplifier. The capacitor 14 is connected between the inverting input terminal and the output of the operational amplifier 15, and the non-inverting input terminal of the operational amplifier 15 is connected to the ground. The capacitor 14 and the operational amplifier 15 form an inverting output type analog integrating circuit 16. . Note that D in FIG.
In the A / A converter, the same reference numerals are given to the components equivalent to those of the conventional D / A converter of FIG. The basic operating principle of the switched capacitor circuit is shown in FIG.
Since it is the same as the A / A converter, detailed description thereof will be omitted.

Next, the operation of the D / A converter of FIG. 1 will be described with reference to FIGS. 2 and 6. Figure 2 (here (1)
(3) (5) (6) are used are timing charts of each part of the D / A converter of FIG. First, the 1-bit digital input signal (1) is input, for example, as shown in cycles t1 to t8. The control signal φ2 of the switch 12 is a square wave with a duty ratio of 50% as shown in (3). Further, the control signal of the conventional switch 11 is the control signal φ1 of (4) which is the exclusive OR of (1) and (3) as described above, but in the present embodiment, this control signal of (4) is used. The control signal φ1d of (5) obtained by delaying the control signal φ1 by a half cycle of the control signal φ2 of (3) is used.

Thus, when the 1-bit digital input signal of (1) is "1" or "0" in the past two times, (5)
Since the control signal φ1d of (3) is delayed from the control signal φ2 of (3) by a half cycle, the combinations of (a) and (b) and (c) and (d) shown in FIG. The analog output signal of (2)
Has the opposite sign.

When the values of the past two times in (1) are different,
Since the control signal φ1d of (5) is fixed to "0" or "1", in the combination of the connection states shown in FIG. 6, (a) and (c)
Alternatively, it is a combination of (b) and (d). In these cases, the switch 11 does not operate, the switch 12 simply switches from the ground to the input of the integrating circuit, and the transfer of charges does not occur, the analog output signal of (6) becomes "0".

That is, the analog output signal of (6) is obtained by moving the average of the past two values of the digital input signal of (1) and inverting the sign. Therefore, if the sign is ignored, the transfer function can be calculated by (Equation 1).

[0024]

[Equation 1]

From this, the frequency characteristic of the output amplitude is (Equation 2)
Becomes

[0026]

[Equation 2]

Therefore, it can be seen that it has a characteristic of being greatly attenuated near the Nyquist frequency. In addition, in order to make the sign non-inverted, as is clear from the above description (5)
The control signal φ1d of 1 may be inverted.

Next, another embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a circuit diagram showing another embodiment of the D / A converter according to the present invention. In FIG. 3, 11, 1
Reference numeral 2 is a switch with three terminals, which are control signals φ1,
The connection is switched by the bar φ2. 13,
Reference numeral 14 is a capacitor, and 15 is an operational amplifier. The capacitor 14 is connected between the inverting input terminal and the output of the operational amplifier 15, and the non-inverting input terminal of the operational amplifier 15 is connected to the ground. The capacitor 14 and the operational amplifier 15 form an inverting output type analog integrating circuit 16. . In the D / A conversion device of FIG. 3, the same reference numerals are given to the components equivalent to those of the conventional D / A conversion device of FIG. Further, since the basic operating principle of the switched capacitor circuit is the same as that of the D / A conversion device of FIG. 5, detailed description thereof will be omitted.

Next, the operation of the D / A converter shown in FIG. 3 will be described with reference to FIGS. Figure 2 (here (1)
(4), (7) and (8) are used in the timing chart of each part of the D / A converter of FIG. First, the 1-bit digital input signal (1) is input, for example, as shown in cycles t1 to t8. The control signal φ1 of the switch 11 is (1)
The control signal φ1 in (4), which is the exclusive OR of (3), is used.
The control signal of the conventional switch 12 is, as described above,
The control signal φ2 in (3) was used, but in the present embodiment, this
The control signal φ2 of (7) which is the inverted (or delayed by a half cycle) of the control signal φ2 of (3) is used.

Control signal bars φ2 and φ1 for these (7) and (4)
As is clear from FIG. 2, the control signal φ2 of (3)
The control signal φ1d in (5) is shifted by a half cycle each. Therefore, the analog output signal of (8)
The analog output signal of (6) is shifted a half cycle forward, that is, the analog output signal of (8) is the average of the past two values of the digital input signal of (1) and the sign is inverted. ing. Of course, the frequency characteristic is represented by (Equation 2).

In the case of the embodiment shown in FIG. 3, it is only necessary to invert and use φ2, which can be easily realized as compared with the case of delaying φ1 by a half cycle as in the case of the embodiment of FIG. Further, as is clear from (2), (6) and (8) of FIG. 2, the delay with respect to the analog output signal of the conventional example is one cycle in the case of the embodiment of FIG. The case is half cycle.

Incidentally, in order to make the sign non-inverted, as is apparent from the above description, (4) the control signal φ1 may be inverted. Next, still another embodiment of the present invention will be described with reference to the drawings.

FIG. 4 is a circuit diagram showing still another embodiment of the D / A converter according to the present invention. In FIG. 4, 11,1
Numerals 2 and 17 are switches of three terminals, which switch the connection by the control signal .phi.1 and the bars .phi.2 and .phi.3, respectively. The conduction admittance of the switch 12 is equal to the sum of the conduction admittance of the switches 11 and 17. Reference numerals 13, 14, 18 are capacitors, and 15 is an operational amplifier. The capacitor 14 is connected between the inverting input terminal and the output of the operational amplifier 15, and the non-inverting input terminal of the operational amplifier 15 is connected to the ground. The capacitor 14 and the operational amplifier 15 form an inverting output type analog integrating circuit 16. . In the D / A converter of FIG. 4, constituent elements equivalent to those of the conventional D / A converter of FIG. 5 are designated by the same reference numerals. Further, since the basic operating principle of the switched capacitor circuit is the same as that of the D / A conversion device of FIG. 5, detailed description thereof will be omitted.

The D / A converter shown in FIG. 4 converts a 2-bit digital input signal into an analog signal. For each bit, the control signals .phi.1 and .phi.3 are the same as in the embodiment described with reference to FIG. To generate switches 11 and 1 respectively
The control signal 7 is used to add the charges from the capacitors 13 and 18 in the integrating circuit 16 to obtain an analog output.

Here, the switch 12 includes a capacitor 13,
The two switches that should be provided for each of the eighteen are grouped into one, so that the noise generated at the time of switching is minimized, and the noise and the characteristic change due to the time mismatch of switching are avoided. It is a thing.

Further, by making the admittance when the switch 12 is conductive equal to the sum of the admittances when the switches 11 and 17 are conductive, the D / A converter is configured without sharing one switch 12. A circuit with a time constant equivalent to can be realized.

The D / A conversion device is configured as described above. Although the switched capacitor circuit is basically based on the configuration of FIG. 1 here, it can be realized in various configurations. For example, the switch 11 is an MO.
It is also possible to use two S analog switches. Further, in FIG. 2, a signal having a half cycle is used as the control signal of the switch with respect to the cycle of the digital input signal of (1), but this can also be realized by using a multi-phase clock signal, for example. Further, although FIG. 4 shows a 2-bit input D / A converter, the present invention is not limited to this, and any number of bits may be used. It need not be weighted.

[0038]

As described above, the D / A conversion device of the present invention has a very simple structure in which one of the control signals of the switch is delayed or inverted, and is moved with respect to a 1-bit digital input signal. Since an averaged signal can be output, an excellent D / A converter that effectively attenuates high-frequency components contained in a digital input signal and does not require high-speed operation of elements such as an integrating circuit is realized. It is possible.

Further, according to the present invention, even when the input is a plurality of bits, the noise generated at the time of switching is minimized, and the noise and the characteristic change due to the time mismatch of the switching are avoided, and the second switch is shared. Without D
It is possible to realize a circuit having a time constant equivalent to that in the case of configuring the / A converter.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a D / A conversion device according to the present invention.

FIG. 2 is a timing chart of each part of a D / A conversion device according to the present invention and a conventional example.

FIG. 3 is a circuit diagram showing another embodiment of the D / A conversion device according to the present invention.

FIG. 4 is a circuit diagram showing still another embodiment of the D / A conversion device according to the present invention.

FIG. 5 is a circuit diagram showing an example of a conventional D / A conversion device.

FIG. 6 is a diagram illustrating a switch operation of the D / A conversion device.

[Explanation of symbols]

 11, 12, 17 switch 13, 14, 18 capacitor 15 operational amplifier 16 integrating circuit

Front page continuation (72) Inventor Akira Sojima 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Hideaki Hatanaka, 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd.

Claims (3)

[Claims] 1. A capacitor, a first and a second switch, and an integrating circuit, wherein the first switch connects one terminal of the capacitor to a reference voltage source or ground corresponding to a 1-bit digital input signal. And the second switch alternately connects the other terminal of the capacitor to the input of the integrating circuit or the ground, and the operation of the first switch corresponding to the 1-bit digital input signal is changed to the digital input signal. A D / A converter in which the output of the integrating circuit is an analog output signal, which is shifted by a half cycle from the cycle. 2. A capacitor, a first switch, a second switch, and an integrating circuit, wherein the first switch connects one terminal of the capacitor to a reference voltage source or ground corresponding to a 1-bit digital input signal. And the second switch alternately connects the other terminal of the capacitor to the input of the integrating circuit or the ground, and shifts the operation of the second switch by a half cycle from the cycle of the digital input signal, A D / A conversion device in which the output of the integration circuit is an analog output signal. 3. A plurality of capacitors and a first switch are connected in the same connection, and the other terminals of the capacitors are all connected to a second switch, the admittance at conduction of the plurality of first switches. 3. The D / A converter according to claim 1, wherein the sum is equal to the admittance when the second switch is on.