JPH06326610A - Deltasigma type a/d converter - Google Patents

Abstract

PURPOSE:To realize a high S/N and the wide band of an input signal without increasing a clock frequency by preparing the plural sets of comparators, DFF, and D/A circuits, performing an interleave operation, and increasing an oversampling ratio. CONSTITUTION:A CLK is impressed to the clock input terminal of a D-FF 11, and the inversion signal of the CLK is impressed to a D-FF 12. When the output signal of an integrator I1 is more than 0V, H are outputted by comparators CMP1 and CMP 2, and when the output signal of the integrator I1 is less than OV, L are outputted by the comparators CMP1 and CMP 2. Then, the output signal of each comparator is latched by the D-FF 11 and 12 of the succeeding stages at the time of the rising of the CLK, and output signals Q1 and Q2 are outputted to a Q output terminal. Analog signals are outputted by D/A conversion circuits 21 and 22 according to the output signals Q1 and Q2, the analog output signals of the D/A conversion circuits 21 and 22 are subtracted from the analog input signal of a DELTASIGMA type A/D converter, and impressed to the input terminal of the integrator I1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter using a ΔΣ modulation technique, and more particularly, to improve the oversampling rate of the A / D converter in a circuit manner to realize a high S / N characteristic. Technology.

[0002]

2. Description of the Related Art FIG. 9 is a block diagram showing an example of a conventional ΔΣ type A / D converter.

In this conventional example, an integrator I and a comparator C are used.
MP, D-FF10, 1-bit D / A conversion circuit 2 for feedback
The output terminal of the integrator I is connected to the + input side of the comparator CMP, the − input side of the comparator CMP is grounded, and the output terminal of the comparator CMP is connected to the D input of the D-FF 10. The clock signal is input to the CLK input terminal, the Q output terminal is connected to the input terminal of the D / A conversion circuit 20, the output signal thereof is subtracted from the analog input by the adder 30, and the input terminal of the integrator I is connected. Q output of the D-FF10 is applied to the ΔΣ type A / D
It is the digital output of the converter.

This conventional example can be grasped as a negative feedback circuit, and if the output voltage of the D / A conversion circuit 20 takes two values of + 1V and -1V, an analog input signal and a 1-bit D / A are used. The feedback operation is performed so that the output signal of the conversion circuit 20 becomes substantially equal. However, since the 1-bit D / A conversion circuit 20 outputs only binary values, the output signal of the 1-bit D / A conversion circuit 20 has a density-modulated coarse / fine waveform.
That is, the analog input signal and the 1-bit D / A conversion circuit 2
The relationship with the output signal of 0 is as follows.

Assume that the analog input signal changes between + 1V and -1V, and the analog input signal is + 1V, -1V, 0.
In the case of V, the 1-bit D / A conversion circuit 20 outputs an L (low level) continuous output signal, an H (high level) continuous output signal, and an alternating output signal of H and L, respectively. , If the analog input signal is at a level between + 1V and -1V, the compression wave signal of H and L is 1 bit D /
The ratio of H and L in the compressional wave of H and L output from the A conversion circuit 20 is determined according to the level of the analog input signal. The digital output signal of the above conventional example is 1
It is the same as the output signal of the bit D / A conversion circuit 20.

As an example of returning a digital output signal to an analog signal, there is a method of converting this digital signal into a binary voltage by a 1-bit D / A conversion circuit and passing it through a low-pass filter, which returns it to an analog signal.

Incidentally, in the conventional example shown in FIG.
The F10 is shown separately from the comparator CMP and the D / A conversion circuit 20, but this is for the purpose of making the functions easy to understand, and in the actual circuit, the comparator CMP and the D-FF function are provided. Sample-and-hold type comparator that integrates the D-FF10 and D / A
It can be realized by a D / A conversion circuit integrated with a conversion function.

The above-described conventional ΔΣ A / D converter has a smaller circuit scale and a relatively high S / N can be realized relatively easily as compared with a flash type A / D converter. A for audio because it can be realized on
Widely used as a / D converter.

Regarding the ΔΣ type A / D converter, it is described in the reference "Oversampling A / D conversion technology" (Akira Yukawa, published by Nikkei BP). According to page 39, FIG. 3.11, it is possible to improve the theoretical S / N of the ΔΣ method by increasing the oversampling rate (sampling frequency ÷ signal band).

[0010]

When the oversampling rate is increased in order to increase the S / N of the ΔΣ type A / D converter, the S / N is limited by the operating speed of the circuit used therein. There is a problem that

In the above conventional example, when the analog input frequency is 1 KHz and the clock frequency (sampling frequency) is 128 KHz, for example, 128 KH
The circuit that must operate in z is the comparator CM
The P, D-FF 10 and the D / A conversion circuit 20. In addition,
Since the integrator I is a kind of low pass filter, the requirement for high speed operation is low.

Here, if an attempt is made to increase the clock frequency in order to increase the S / N ratio and widen the band of the input signal, the operating speed of these circuits (comparator CMP, D-FF10, D / A conversion circuit 20) is increased. Is a problem.
That is, if the clock frequency is simply increased with the configuration of the conventional example, the rate is limited by the performance of the transistor used therein, and there is a problem that the limit is, for example, about 100 MHz in the CMOS process and about 1 GHz in the bipolar process. is there.

It is an object of the present invention to provide a ΔΣ type A / D converter which can realize a high S / N ratio and a wide band of an input signal without increasing the actual clock frequency. is there.

[0014]

The present invention is intended to increase the effective oversampling rate by preparing a plurality of sets of comparators, DFFs and D / A circuits and performing interleave (circuit parallelization) operation. is there.

[0015]

In the present invention, the effective oversampling rate is increased by preparing a plurality of sets of comparators, DFFs, and D / A circuits and performing interleave operation. Therefore, it is possible to increase the S / S ratio without increasing the actual clock frequency. It is possible to realize N conversion and wide band of the input signal.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a ΔΣ type A / A which is an embodiment of the present invention.
It is a figure which shows a D converter, FIG.1 (1) is the circuit diagram, FIG.1 (2) is the timing chart.

This embodiment has one integrator I1 and two sets of "comparator, D-FF, D / A conversion circuit", one set of which is "comparator, D-FF, D". /
The "A conversion circuit" includes a comparator CMP1 and a D-FF11.
And a 1-bit D / A conversion circuit 21 for feedback, and the remaining one set of "comparator, D-FF, D / A conversion circuit" includes comparators CMP2 and D-FF12 and 1-bit D / A for feedback. And a conversion circuit 22.

The output terminal of the integrator I1 is the comparator C.
It is connected to the + input terminals of MP1 and CMP2, each − terminal is grounded, and the output terminal of the comparator CMP1 is DF
It is connected to the D input terminal of F11, the Q output terminal of the D-FF11 is connected to the input terminal of the D / A conversion circuit 21, and the output terminal of the comparator CMP2 is connected to the D input terminal of the D-FF12. -The Q output terminal of FF12 is D /
It is connected to the input terminal of the A conversion circuit 22. Analog output signal A1 of D / A conversion circuit 21 and D / A conversion circuit 2
The two analog output signals A2 are added by the adder 31 to the analog input signal of the ΔΣ A / D converter according to the present embodiment and applied to the input terminal of the integrator I1.

Output signal Q1 of D-FF11 and D-FF1
The output signal Q2 of 2 is added by the adder 41,
The result of this addition becomes the digital output signal of the ΔΣ type A / D converter of this embodiment.

Next, the operation of the above embodiment will be described.

The basic operation of the ΔΣ modulator is the same as that of the conventional example described above, and the analog input signal is + 1V to -1.
Assuming that it changes between V, the analog input signal is + 1V, −
In the case of 1V and 0V, 1-bit D / A conversion circuit 21
Are continuous output signals of L (low level) and H, respectively.
(High level) continuous output signal, an output signal in which H and L are alternately generated is output, and the analog input signal is + 1V and −.
When the level is between 1V, the compressional wave signal of H and L is output from the 1-bit D / A conversion circuit 21 by pulse number modulation, and the H of compressional wave of H and L is H.
The ratio between L and L depends on the level of the analog input signal. The 1-bit D / A conversion circuit 22 also operates similarly to the 1-bit D / A conversion circuit 21.

Next, the operation of the two sets of "comparator, D-FF, D / A" in the above embodiment will be described.

A clock having two opposite phases of CLK and an inverted signal of CLK is used, CLK is applied to the clock input terminal of the D-FF 11, and the inverted signal of CLK is applied to the D-FF.
12 clock input terminals. If the output signal of the integrator I1 is 0 V or higher, the comparators CMP1 and CMP
2 outputs H and the output signal of the integrator I1 is less than 0V, the comparators CMP1 and CMP2 output L, and the output signals of the comparators CMP1 and CMP2 are D- of the next stage.
The FFs 11 and 12 latch the signal at the rising edge of CLK (or an inverted signal of CLK) and output the output signals Q1 and Q2 to the Q output terminal. In accordance with the output signals Q1 and Q2, the D / A conversion circuits 21 and 22 output an analog high level V _H or an analog low level V _L , and Δ
The analog output signal of the D / A conversion circuits 21 and 22 is subtracted from the analog input signal of the Σ-type A / D converter to obtain an integrator I.
1 to the input terminal.

As a result, the effective oversampling rate can be doubled without raising the clock frequency (frequency of CLK). That is, in one cycle, two D-F
Since the F11 and 12 output at different timings, and the 1-bit D / A conversion circuits 21 and 22 output at different timings in response to the both outputs, the sampling frequency is effectively doubled. The oversampling rate (sampling frequency / signal band) is effectively doubled. By thus increasing the effective oversampling rate, it is possible to realize a high S / N ratio and a wide band of the input signal without increasing the actual clock frequency.

In the above embodiment, two sets of "comparator, D-FF, D / A" are used, two-phase clocks are prepared, and double interleaving is performed using these clocks. However, not limited to this, two or more sets of “comparator, D-FF, D / A” may be used. That is, N sets (N is an integer of 2 or more) of "comparators, D
-FF, D / A "and N-phase clocks may be prepared and used for N-fold interleaving, whereby the oversampling rate can be increased N-fold.

That is, N comparators are provided,
N D-FFs are provided, N D / A conversion circuits are provided, the output terminal of the integrator is connected to each input terminal of the N comparators, and the output terminal of each comparator is N D-
It is connected to the respective input terminals of the N D / A conversion circuits via the respective FFs, and all the output signals of the respective D / A conversion circuits and the analog input signal of the ΔΣ type A / D converter are added. The applied signal is applied to the input terminal of the integrator, and each D-FF
May be used as the digital output signal of the ΔΣ type A / D converter, and each of the N D-FFs may be operated by clocks having different phases.

FIG. 2 is a diagram showing a circuit example in which the D / A conversion circuits 21 and 22 are modified to embody the integrator I1 and the adder 31 in the embodiment shown in FIG. 1 (1).

The embodiment shown in FIG. 2 is a D / A conversion circuit 2
The circuits 21a and 22a are used instead of the circuits 1 and 22, respectively, and the circuit 21a uses the output signals Q1 and CL.
AND circuit 211 receiving K and this AND circuit 21
D / A conversion circuit 212 for converting the output signal of No. 1 into an analog signal, and the circuit 22a includes output signals Q2 and C2.
AND circuit 221 which receives the inverted signal of LK and this A
D for converting the output signal of the ND circuit 221 into an analog signal
And an A / A conversion circuit 222.

The integrator I1 is composed of a resistor, a capacitor and an operational amplifier. The subtraction between the analog input signal and the output signals of the D / A conversion circuits 212 and 222 is realized by addition via a resistor at the input terminal of the integrator. That is, since this integrator is configured to use the inverting input of the operational amplifier, the phase of the output signal of the integrator is inverted, and as a result, the output signals of the D / A converters 212 and 222 have the same phase. It remains inverted and the D / A converter 2
By adding the output signals of 12 and 222 to the analog input, the result is subtraction.

As shown in FIG. 2, two sets each having a D-FF and a D / A conversion circuit are configured, and D belonging to one set is D.
-The FF and the D / A conversion circuit operate with clocks having the same phase, and when each set operates with clocks having different phases, unstable operation such as oscillation occurs when a high-order loop filter is used. Can be avoided.

That is, the output signal Q1 of the D-FF11 is ANDed with CLK, and the output signal Q2 of the D-FF12.
Is ANDed with the inverted signal of CLK, so CLK,
If the inverted signal of CLK is 50% duty, AND
The duty of the circuits 211 and 221 is also 50%, so that the output signals A1 and A2 of the circuits 21a and 22a are also du.
ty becomes 50%, and the output waveform shown on the right side of FIG. By adding the AND circuits 211 and 221, the energy centers (center times of the output pulses) of the analog output signals A1 and A2 are shifted forward, so that D
This is equivalent to the case where the delay time between the -FFs 11 and 12 and the D / A conversion circuits 212 and 222 is shortened, and when a high-order loop filter is used, unstable operation such as oscillation can be avoided.

FIG. 3 is a diagram showing a circuit example obtained by modifying the circuits 21a and 22a in the embodiment shown in FIG.

The embodiment shown in FIG. 3 has circuits 21a and 22a.
Instead of the circuit 21b and 22b, the circuit 21b is composed only of an AND circuit 211 that receives the output signal Q1 and CLK, and the circuit 22a is
The AND circuit 221 only receives the output signal Q2 and the inverted signal of CLK. That is, the embodiment shown in FIG. 3 is different from the embodiment shown in FIG.
22 is deleted, and is used in an LSI or the like. That is, the AND circuits 211 and 221 basically have the function of a D / A conversion circuit, and in addition, since the wiring distance from the D-FFs 11 and 12 to the adder 31 can be set short in an LSI or the like, the interval between them can be set. The level of the signal does not decrease so much, and it is not necessary to separately provide the D / A conversion circuits 212 and 222.

In the embodiment shown in FIGS. 2 and 3, D-FF and D
Although two sets each having the / A conversion circuit are configured, the present invention is not limited to this, and N sets (N is an integer of 2 or more) including the D-FF and the D / A conversion circuit are configured. Good. That is, N sets each including one D-FF and one D / A conversion circuit are configured, and D-FFs and D / A belonging to one set are included.
The conversion circuit may operate with clocks having the same phase, and each of the N sets may operate with clocks having different phases. By doing so, unstable operation such as oscillation can be avoided when a high-order loop filter is used.

FIG. 4 is a diagram showing an example in which the comparator and D-FF in the embodiment shown in FIG. 1 (1) are multi-bit. That is, the embodiment shown in FIG.
The output signal of is a 1-bit type in which the H state or the L state is discriminated by a comparator. In the embodiment shown in FIG. 4, the output signal of the integrator I1 is multi-bit.

In the embodiment shown in FIG. 4, in the circuit 50, two comparators 51 and 52 and two D-FFs are provided.
53 and 54, an adder 55 that adds the output signals of the D-FFs 53 and 54, and a 2-bit D / A conversion circuit 56 are used, and the threshold values of the comparators 51 and 52 are set to +0.
5 and -0.5, the integrated output is +0.5
As described above, three states of −0.5 or less can be discriminated between +0.5 and −0.5. Thereby, the comparators 51, 5
The output signal of 2 goes through the D-FFs 53 and 54, and the adder 55
2 bit coded signal, which is input to the 2 bit D / A 56, and the analog output signal A
I got 1.

Further, in the circuit 60, two comparators 61 and 62, two D-FFs 63 and 64, and D-FF
An adder 65 for adding the output signals of the FFs 63 and 64;
Using the bit D / A conversion circuit 66, the comparator 6
By setting the thresholds of 1 and 62 to +0.5 and -0.5, the integrated output is discriminated between three states of +0.5 or more, between +0.5 and -0.5, and -0.5 or less. it can. As a result, the output signals of the comparators 61 and 62 are D-
It is input to the adder 65 via the FFs 63 and 64, and 2bi
It becomes a coded signal of t, and this is 2bit D / A6
Input to 6 to obtain the analog output signal A2.

In FIG. 4, for simplicity, a type in which two comparators are used to determine a ternary state is shown, but the number of comparators is further increased, and for example, 15 comparators are used. , 16 states,
It is also possible to code into 4 bits by an adder and obtain the analog output signal A1 or A2 by a 4 bit D / A conversion circuit.

FIG. 5 is a circuit diagram showing a modification of the comparator in the above embodiment, and FIG. 5 (1) is a diagram showing a circuit in which one comparator of the embodiment shown in FIG. 5 (2) is a diagram showing a circuit in which one comparator of the embodiment shown in FIG. 2 is used.

The circuit shown in FIG. 5 (1) uses a comparator CMP1a instead of the comparators CMP1 and CMP2 of the embodiment shown in FIG.
Is connected to the + input terminal of the comparator CMP1a, the-input terminal of the comparator CMP1a is grounded, and the output terminal of the comparator CMP1a is D-FF1,
It is connected to each of the 12 D input terminals. The configuration other than these is the same as that of the embodiment shown in FIG. By reducing the number of comparators in this way, the amount of hardware can be reduced.

The circuit shown in FIG. 5 (2) uses a comparator CMP1a instead of the comparators CMP1 and CMP2 of the embodiment shown in FIG.
Is connected to the + input terminal of the comparator CMP1a, the-input terminal of the comparator CMP1a is grounded, and the output terminal of the comparator CMP1a is D-FF1,
It is connected to each of the 12 D input terminals. The other configuration is the same as that of the embodiment shown in FIG. By reducing the number of comparators in this way, the amount of hardware can be reduced.

In the embodiments shown in FIGS. 5A and 5B, the operation as the ΔΣ A / D converter is the same as that of the embodiments shown in FIGS. 1 and 2, and the oversampling rate ( Sampling frequency ÷ signal band) is effectively 2
Higher S / N without doubling the actual clock frequency
It is possible to realize a wide band of input signals. In the embodiment shown in FIGS. 5A and 5B, N sets (N is an integer of 2 or more) of “comparators, D-FF, D
/ A ”and N-phase clocks may be prepared and used to perform N-fold interleaving, whereby the oversampling rate can be increased to N-fold.

FIG. 6 is a circuit diagram showing an example in which the embodiment shown in FIG. 1 is operated with four-phase clocks.

The embodiment shown in FIG. 6 is provided with comparators CMP3 and CMP4 in addition to the comparators CMP1 and CMP2 of the embodiment shown in FIG.
The output signal of D-FF11a is applied to the D input terminal of D-FF11a, and D
-The Q output signal Q1 of the FF11a is sent to the 1-bit D / A conversion circuit 21, and the output signal of the comparator CMP2 is D-
It is applied to the D input terminal of FF12a, and Q of D-FF12a is applied.
The output signal Q2 is sent to the 1-bit D / A conversion circuit 22, the output signal of the comparator CMP3 is applied to the D input terminal of the D-FF 13a, and the Q output signal Q3 of the D-FF 13a becomes 1.
sent to the bit D / A conversion circuit 23 and the comparator CMP
The output signal of 4 is applied to the D input terminal of the D-FF 14a,
The Q output signal Q4 of the D-FF 14a is sent to the 1-bit D / A conversion circuit 24.

Further, the D-FFs 11a, 12a, 13a,
CLK1 and C are respectively applied to the clock input terminals of 14a.
Apply LK2, CLK3, CLK4, CLK1, CL
The phases of K2, CLK3, and CLK4 are shifted by 90 degrees, as shown in FIG. 6 (2).

While the embodiment shown in FIG. 1 is operated with a two-phase clock, the embodiment shown in FIG. 6 has four sets of "comparator, D-FF, 1-bit D / A conversion circuit". And CLK1, CLK2, CLK3, CLK4 input to the D-FFs 11a, 12a, 13a, 14a.
Is a four-phase clock whose phase is shifted by 90 degrees, so that the embodiment shown in FIG. 6 can effectively increase the sampling frequency four times.

Also in the embodiment shown in FIG. 6, as shown in FIG. 2, the 1-bit D / A conversion circuits 21, 22, 23, 2 are shown.
An AND circuit is inserted in 4 and the D-FF and the D / A conversion circuit belonging to one set are operated by the clocks of the same phase,
Unstable operation such as oscillation may be avoided, or one comparator may be integrated as shown in FIG.

FIG. 7 shows a two-stage integration type Δ of the embodiment shown in FIG.
It is a block diagram which shows an example at the time of applying to a (Sigma) A / D converter.

The embodiment shown in FIG. 7 has two integrators I2,
I3 are connected in series, an adder 33 is provided in a stage preceding the integrator I2, an adder 34 is provided in a stage preceding the integrator I3, and an integrator I3 is provided.
Is applied to the + input terminals of the comparators CMP1 and CMP2, and the output signals A1 and A2 of the 1-bit D / A conversion circuits 21 and 22 are applied to the adders 33 and 34.

The double integration type ΔΣ A / D converter is formed by connecting two integrators in series and makes the low pass filter characteristic of one round of the feedback loop steeper to increase the one round gain on the low frequency side. However, by reducing the loop gain on the high frequency side, the quantization noise at the time of ΔΣA / D conversion can be further reduced (noise shaped) on the low frequency side. A description of the two-stage integration type ΔΣ A / D converter itself is given in the above-mentioned Reference P37, FIG. 2.9.

Similar to the embodiment of FIG. 7, it is possible to realize a ΔΣ A / D converter with higher S / N by increasing the number of stages such as 3 stages and 4 stages. In addition, the two-stage integration type Δ shown in FIG.
Σ A / D converter is a triple or higher (third or higher) integral type ΔΣ
It can be applied to A / D converters.

FIG. 8 shows a double MAS of the embodiment shown in FIG.
It is a block diagram which shows an example at the time of applying to H type (triangle | delta) (Sigma) A / D converter.

In the embodiment shown in FIG. 8, an adder 35 similar to the adder 31 and an integrator I4 similar to the integrator I1 are followed by a circuit 70 (comparators CMP1, CMP2, D-).
FFs 11 and 12, adder 41, D / a conversion circuits 21 and 2
2) is connected, and the output signal of the integrator I4 is added to the adder 31.
Is supplied to an integrator I5 similar to the integrator I1 via an adder 36 similar to, and a circuit 80 similar to the circuit 70 is connected after the integrator I5, and an output signal of the circuit 80 is output from the differentiator 8
After being differentiated by 1, the circuit 7 is added by the adder 82.
It is added to the output signal of 0 and becomes a digital output.

As described above, in the ΔΣ A / D converter, the S / N characteristic is improved as the number of stages of the integrator is increased, but when the number of stages is increased, the phase is rotated and the feedback loop becomes unstable ( Oscillates). To solve this, MAS
An H-type ΔΣA / D converter has been proposed. MASH type Δ
The ΣA / D converter uses two sets of primary ΔΣA / D converters, inputs an analog input signal to the first-stage ΔΣA / D,
The output terminal of the first-stage integrator is connected to the second-stage analog input terminal, the digital outputs of the respective ΔΣ A / D converters are appropriately processed and added, and the MASH type ΔΣ A / D converters are connected. It is used as a digital output signal. With this configuration, the S / N characteristics are equivalent to those of the double ΔΣ type A / D converter, and the two sets of ΔΣ type A / D converters are each a primary ΔΣ A / D converter. It consists of
Instability which is a problem in the high-order ΔΣ A / D converter can be solved. Note that the description of the MASH type ΔΣ A / D converter itself can be found in the above-mentioned References P43 to P44, FIG.
7 are described.

The MASH type ΔΣA / D converter may be applied to a triple or more (third or more) MASH type ΔΣA / D converter.

The above embodiments do not depend on the processes such as bipolar transistors and MOS transistors, and the integrators I1 to I5 are CR integrators, switched capacitor integrators and the like. May be adopted.

In the above embodiment, the analog output of the D / A conversion circuit is shown as a voltage output, but it may be considered that the analog output of the D / A conversion circuit is a current output.

Furthermore, in the above embodiment, the clock duty is 50%, but it may be considered that the clock duty is other than 50%. Also,
The filter order is not limited to the illustrated first order and second order.

[0059]

According to the invention of claim 1 or 2, the oversampling rate of the ΔΣ A / D converter can be effectively increased by the interleave method.
High S / N and wide band input can be achieved. Therefore, when integrating the ΔΣ A / D converter into an integrated circuit, it is not necessary to use an expensive high-speed device process.
This has the effect of reducing the cost of the converter.

According to the invention of claim 3, the D-FF is
And a D / A conversion circuit are configured in plural, and the D-FF and the D / A conversion circuit belonging to one set operate with clocks of the same phase, and the respective sets have different clocks. The operation has an effect that an unstable operation such as oscillation can be avoided when a high-order loop filter is used.

[Brief description of drawings]

1 is a diagram showing a ΔΣ type A / D converter according to an embodiment of the present invention, and FIG. 1 (1) is a circuit diagram thereof, and FIG.
(2) is the timing chart.

FIG. 2 is a diagram showing a circuit example in which the D / A conversion circuits 21 and 22 are modified to embody an integrator I1 and an adder 31 in the embodiment shown in FIG.

FIG. 3 is a circuit diagram of the embodiment shown in FIG.
It is a figure which shows the circuit example which deformed a.

FIG. 4 is a diagram showing an example in which the comparator and D-FF in the embodiment shown in FIG. 1 (1) have multiple bits.

FIG. 5 is a circuit diagram showing a modified example of the comparator in the above embodiment.

FIG. 6 is a circuit diagram showing a case where the embodiment shown in FIG. 1 is operated with four-phase clocks.

7 is a block diagram showing an example of a case where the embodiment shown in FIG. 1 is applied to a two-stage integration type ΔΣ A / D converter.

FIG. 8 is a dual MASH type ΔΣA / embodiment shown in FIG.
It is a block diagram which shows an example at the time of applying to a D converter.

FIG. 9 is a block diagram showing an example of a conventional ΔΣ A / D converter.

[Explanation of symbols]

 11-14, 11a-14a ... D-FF, 21-24, 21a-24a ... D / A conversion circuit, 31-36, 41, 82 ... Adder, I1-I5 ... Integrator, CMP1-CMP4, CMP1a ... Comparator, 211, 221, ... AND circuit.

Claims (3)

[Claims] 1. An integrator, a comparator, a D-FF, and a D / FF.
In a ΔΣ A / D converter having an A conversion circuit, N comparators (N is an integer of 2 or more) are provided, N D-FFs are provided, and N D / A conversion circuits are provided. An output terminal of the integrator is connected to each input terminal of the N comparators, and an output terminal of each comparator is connected to each of the N D / FFs via each of the N D-FFs.
Connected to each input terminal of the A conversion circuit,
A signal obtained by adding all the output signals of the A / A conversion circuit and the analog input signal of the ΔΣ type A / D converter is applied to the input terminal of the integrator, and the output signal of each D-FF is changed to the Δ
A ΔΣ type A / D converter characterized in that it is a digital output signal of the Σ type A / D converter, and each of the N D-FFs is operated by clocks having different phases. 2. An integrator, a comparator, a D-FF and a D /
In a ΔΣ type A / D converter having an A conversion circuit, one comparator is provided, N D-FFs are provided (N is an integer of 2 or more), and N D / A conversion circuits are provided. The output terminal of the integrator is connected to the input terminal of the comparator, and the output terminal of the comparator is the N number of D
-Connected to the respective input terminals of the N D / A conversion circuits via the respective FFs, and all the output signals of the D / A conversion circuits and the analog inputs of the ΔΣ A / D converter. The signal added with the signal is applied to the input terminal of the integrator, and the output signal of each D-FF is added to the ΔΣ type A / D.
A ΔΣ type A / D converter characterized in that it is a digital output signal of the converter, and each of the N D-FFs is operated by clocks having different phases. 3. The D-FF according to claim 1 or 2, wherein N sets each having one D-FF and one D / A conversion circuit are formed, and the D- belonging to one set is D-FF.
The FF and the D / A conversion circuit operate with clocks having the same phase, and each of the N sets is operated with clocks having different phases.
Type A / D converter.