JPH08227944A - Nonvolatile memory and fabrication thereof - Google Patents

Abstract

PURPOSE: To obtain a nonvolatile memory having a floating gate electrode in which the performance is enhanced by enhancing the durability and reliability of oxide film underlying the floating gate electrode. CONSTITUTION: A channel region 4 is provided closely to a drain junction region between source and drain impurity diffusion region 10, 11 of second conductivity type formed, through a predetermined interval, in the surface layer of the major surface of a semiconductor substrate of first conductivity type on such plane as a part of at least surface has crystal orientation different from that of the major surface. Furthermore, an inclining part comprising a surface having crystal orientation different from that of the major surface of semiconductor substrate is provided and the source impurity diffusion region 10 is disposed relatively above the drain impurity diffusion region 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory and its manufacturing method. More specifically, the present invention relates to a nonvolatile memory having an electrically writable / erasable floating gate electrode and a method for manufacturing the same. Further, the present invention relates to a nonvolatile memory having an ultrafine floating gate electrode and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, various types of electrically writable / erasable nonvolatile semiconductor memory devices and devices for realizing them have been proposed. Among them, as one of the devices that have received the most attention recently, a floating gate electrode is provided in the gate insulating film under the control gate electrode, and a high voltage is applied between the source impurity diffusion region and the drain impurity diffusion region. In addition, a device using so-called hot electron injection in which hot carriers generated by applying a high voltage to the control gate electrode is attracted by the electric field of the control gate electrode and injected into the floating gate electrode can be mentioned. For example, as one of the devices having a typical structure, one that has recently attracted particular attention is US Pat.
Nonvolatile memories such as those described in 963,825 and JP-A-61-127179 are known. A typical structure of this nonvolatile memory is shown in FIGS.

34 to 36 show a nonvolatile memory in which
FIG. 3 is a cross-sectional structural view of a single memory cell called a self-aligned type having the simplest structure. At a practical level,
Although it has a more complicated structure, this figure will be described as an example here for the sake of simplicity. In the figure 101
Is a P-type semiconductor substrate, 102 is a second gate insulating film, 103
Is a first gate insulating film, 104 is a first polysilicon layer (floating gate electrode), 105 is a third gate insulating film, 1
06 is the second polysilicon layer (control gate electrode), 10
Reference numeral 7 is a source region (N ⁺ -type impurity diffusion region), 108 is a drain region (N ⁺ -type impurity diffusion region), and 109 is an element isolation oxide film (LOCOS).

That is, this structure is called a self-aligned type because the floating gate electrode 104 and the control gate electrode 10 are
6 is formed in a self-aligned manner in the channel length direction. The source region 107 is formed of an LDD (lightly doped diff) in order to improve the withstand voltage during an erase operation.
(usion) or DDD (double doped diffusion) structure is known (LDD type in FIG. 35, FIG. 36).
Shows the DDD type).

The operating principle and characteristics of this nonvolatile memory will be briefly described. That is, writing is performed in the drain region 108.
And a high voltage is applied to the control gate electrode 106, and carriers generated by avalanche breakdown are attracted by the control gate electrode 106 in the region near the drain junction in the channel,
It is performed by accumulating in the floating gate electrode 104.
Erasure is performed by applying a high voltage to the source region with the control gate electrode 106 grounded, and discharging the accumulated charge in the floating gate electrode 104 by using Fowler-Nordheim (FN) tunnel injection. . At this time, since the charge is discharged through the first gate insulating film 103 which is thinner than the second gate insulating film 102, Fowler-Nordheim tunneling is likely to occur. Also,
By increasing the thickness of the second gate insulating film 102,
Accidental erasure by the Read Disturb mode from the drain side during reading is prevented.

Next, the method of manufacturing the above-mentioned device will be described.
Explain. First, on the P-type silicon substrate 101, the bag
Grow 1000 Å oxide film. Then this bag
A silicon nitride film to serve as an oxidation stop film is formed on the fa-oxide film by 3
Deposit 000Å. Next, on this silicon nitride film,
An element isolation oxide film is formed to isolate the element region into islands.
A photoresist pattern that opens only in the area
I do. The silicon nitride film is formed using this pattern as a mask.
By selectively removing the
An open silicon nitride film pattern is formed. Next
Then, after removing the resist pattern, the silicon nitride
Using the film pattern as a mask to form a channel stopper
Boron implantation energy 40 KeV, dose 5 × 10
¹³ions / cm² Ion implantation under the conditions of field-doped layer
To form Next, perform wet oxidation at 1000 ° C.,
Grow a silicon oxide film on the exposed surface of the P-type silicon substrate
An element isolation oxide film 109 is formed. At that time, the fee
The boron atoms in the doped layer are activated and redistributed.
As a result, an inversion prevention layer is formed under the element isolation oxide film 109.
It is formed.

Then, dry etching is performed to remove the silicon nitride film pattern. Further, wet etching with ammonium fluoride is performed to remove the buffer oxide film. After that, thermal oxidation is performed to grow the second gate insulating film 102 to 20 nm on the exposed surface of the P-type silicon substrate. Next, a resist is applied on the entire surface, and a photoresist pattern is formed by photoetching, in which only the region to be the gate insulating film on the source region side is opened. Using this as a mask, a part of the second gate insulating film 102 is etched. Remove with acid etc.
After removing the photoresist pattern, thermal oxidation is subsequently performed to form the first gate insulating film 103. At this time, since the second gate insulating film 102 is subjected to additional oxidation, the second gate insulating film 102 having a large film thickness is formed.

Here, the film thickness of the first gate insulating film 103 is 10 as in the case of the gate insulating film of a normal nonvolatile memory.
The thickness is controlled to about nm. Second gate insulating film 102
Has a thickness of 25 to 35 nm. Then, a polycrystalline silicon film is formed on the entire surface by CVD (Chemical Vapor Deposition) 1500
Å Grow. An n-type impurity such as phosphorus is introduced into the polycrystalline silicon film by thermal diffusion or ion implantation, and then the polycrystalline silicon film is etched using a resist pattern to form the floating gate electrode 104. After removing the resist pattern, the surface of the floating gate electrode 104 is oxidized to form an interlayer insulating film made of a silicon oxide film with a thickness of about 20 to 30 nm. Next, in order to form the control gate electrode 106, a polycrystalline silicon film of about 2500 Å is formed on the entire surface of the substrate by CVD or the like. Like the floating gate electrode 104, phosphorus is added to the polycrystalline silicon film. Subsequently, for example, by CVD, a thickness of 15
A silicon oxide film of about 00Å is formed.

Then, the silicon oxide film and the polycrystalline silicon film are continuously patterned by etching using a mask made of a resist film to form a control gate electrode 106. At this time, in the channel length direction, the floating gate electrode 104 protruding from the lower portion of the control gate electrode 106 is etched to realize a self-aligned arrangement. Next, after removing the resist, an oxide film is formed on the entire surface, and As is ion-implanted with low energy using the control gate electrode 106 and the like and the floating gate electrode 104 as a mask to form a region where a source region is to be formed. A low concentration diffusion layer is formed. Next, after vapor-depositing an oxide film on the entire surface by the CVD method, the CVD silicon oxide film is etched back by reactive ion etching to form sidewalls on the side surfaces of the control gate electrode 106 and the floating gate electrode 104. As using the control gate electrode 106, the floating gate electrode 104 and the side wheels thereof as a mask.
Implantation energy 40 KeV, dose 5 × 10 ¹⁵ ions
Ion implantation under the condition of / cm ² and thermal acid annealing for source,
A drain region (107, 108) is formed. After that, an interlayer insulating film is formed, contact holes are formed and metallization is performed in accordance with a usual process, and a passivation film is formed, whereby a nonvolatile memory having the most basic structure is completed.

As described above, by forming the gate insulating film below the floating gate to be thin on the source side, FN tunneling is likely to occur during erasing. Also, since the oxide film on the drain side is thick, it is possible to prevent erroneous erasing from the drain side during reading and writing.

[0011]

As described above, in the non-volatile memory, since charges are frequently transferred through the extremely thin oxide film located under the floating gate electrode, how efficiently carriers are transferred. Greatly contributes to device speedup. Moreover, it is no exaggeration to say that the durability and reliability of the non-volatile memory depend on how the thin oxide film is formed. However, the conventional structure and manufacturing method as described above have the following problems.

That is, in the conventional structure, the thin oxide film located under the floating gate electrode and the charges related to the injection proceed almost completely in the horizontal direction, so that carrier injection hardly occurs. Also, during manufacturing,
The step of forming a thin oxide film under the floating gate electrode includes a step of forming a first gate insulating film, a step of applying a photoresist, a step of exposing / patterning the photoresist, and a first gate using the photoresist pattern as a mask. It consists of multiple steps such as the step of etching a part of the insulating film, the step of removing the photoresist, and the step of forming the second gate insulating film, and it is necessary to form a highly accurate and thin oxide film with good reproducibility. Was extremely difficult. Further, since there is a step of bringing the gate insulating film into close contact with the organic resist, it is difficult to prevent contamination. In addition, since a part of the first gate insulating film is removed and then additional oxidation is performed, edge stress is likely to occur at the silicon interface in the boundary region between the first gate insulating film and the second gate insulating film, and the region is removed. Before discussing the durability and reliability such as the dielectric breakdown of the oxide film formed on the substrate, it was extremely difficult to secure the yield.

Further, in US Pat. Nos. 4,964,080 and 5,049,515, a control gate electrode is close to a channel region (vertical region) via an insulating film to form a select gate electrode. A non-volatile memory of select gate structure is described. However, these non-volatile memories have a problem that high integration is difficult as compared with the non-volatile memories in which the control gate electrode and the floating gate electrode are formed in a self-aligned manner as described above.

Therefore, the inventor of the present invention has found a semiconductor device in an EEPROM having a floating gate electrode, in which durability and reliability of an oxide film under the floating gate electrode can be increased and performance can be improved, and a manufacturing method thereof. The present invention has been reached.

[0015]

Thus, according to the present invention, the semiconductor substrate of the first conductivity type and the surface layer of the main surface of the semiconductor substrate are formed at regular intervals, and at least one of them is formed. Is provided between the source impurity diffusion region and the drain impurity diffusion region of the second conductivity type, a part of the surface of which is formed on a surface having a crystal plane orientation different from the main surface. A channel region, a gate insulating film provided on the channel region, a floating gate electrode provided on the gate insulating film, and an interlayer insulating film so that at least a part of the floating gate electrode is laminated thereon. An inclined portion having a control gate electrode, the channel region being in contact with the drain impurity diffusion region, and having a crystal plane orientation different from the main surface of the semiconductor substrate. Has the non-volatile memory source impurity diffusion region is characterized by being provided relatively above the drain impurity diffusion regions is provided.

The first insulating film formed on the semiconductor substrate of the first or second conductivity type, the semiconductor thin film formed on the first insulating film, and the surface of the main surface of the semiconductor thin film. A channel region provided between the source impurity diffusion region and the drain impurity diffusion region of the first or second conductivity type formed at a constant interval in the layer, and a gate insulating film provided on the channel region, A floating gate electrode provided on the gate insulating film, a control gate electrode provided via an interlayer insulating film so that at least a part of the floating gate electrode is laminated on the floating gate electrode, and the channel region has an inclined portion, There is also provided a thin film transistor characterized in that the source impurity diffusion region is provided above or below the drain impurity diffusion region.

Further, a step of forming an element isolation oxide film in a predetermined region of one main surface of the semiconductor substrate of the first conductivity type, and a second conductivity type low oxide film in at least a region where the Fowler-Nordheim tunnel occurs in the active region. A step of forming a high concentration impurity diffusion region; a step of forming a gate insulating film on the active region in which the low concentration impurity diffusion region is formed; and a floating gate electrode controlling the low concentration impurity diffusion region and the floating gate electrode. A step of forming so as to overlap with an area determined according to a capacitance with the gate electrode, a step of forming an interlayer insulating film on the floating gate electrode, and a step of laminating at least a part of the floating gate electrode. A step of forming a patterned control gate electrode, and a step of implanting a high concentration of second conductivity type impurities into the active region using the control gate electrode and the floating gate electrode as a mask. Method of fabricating a non-volatile memory comprising a step of forming a region and the drain region is also provided.

Further, a step of forming an element isolation oxide film on a predetermined region of one main surface of the first conductivity type semiconductor substrate, and an oxide film formation at the time of forming the element isolation oxide film on the predetermined region of the element isolation oxide film. A step of etching and removing the blocking film and the photoresist to form an opening in the element isolation oxide film; a step of removing the oxide film formation blocking film and the photoresist; and a step of forming the element isolation oxide film in the opening. Is a step of forming a second oxide film having a different etching rate, a step of etching away a thin region of the element isolation oxide film to expose a part of the semiconductor substrate to be an active region, and a gate on the exposed region. A step of forming an insulating film, a step of forming a floating gate electrode on the gate insulating film, a step of forming a planarizing film on the entire surface so that the surface is flat at least on the active region, and the planarizing film. Etching under the condition that the planarization film remains on the floating gate electrode on the sloped region and the surface of the floating gate electrode other than on the sloped region is exposed, and the planarization remaining on the floating gate electrode on the sloped region And a step of etching the floating gate electrode using the film as a mask.

Further, a step of covering at least a part of the first electrode with an insulating film and forming a first interlayer film in a region other than the region covered with the insulating film, the insulating film is removed, and the insulating film is removed. A second interlayer film that is thinner than the first interlayer film in a region where the first interlayer film is formed, and at least the second interlayer film is formed on the first electrode through the first interlayer film and the second interlayer film. And a step of forming a second electrode so as to cover the non-volatile memory.

The nonvolatile memory of the present invention can be used as a flash memory. As the semiconductor substrate used in the present invention, a material normally used for a non-volatile memory can be used. As such a substrate, silicon, G
aAs etc. are mentioned. Further, this substrate is p-type or n-type.
It is possible to use a substrate in which impurities of a conductivity type of a type are included in advance. Examples of such impurities include boron as a p-type impurity and P and As as an n-type impurity. In addition,
When the first conductivity type is p-type, the second conductivity type is n-type,
When the first conductivity type is n-type, the second conductivity type is p-type.
It is also preferable to use a substrate from which harmful impurities and defects have been removed by gettering in advance. Further, the substrate is provided with an inclined portion, and the height of the inclined portion is 100 to 50.
00Å and the width is preferably 200 to 8000Å. Further, this height is adjusted so that the resolution of the exposure does not decrease. The smaller the height, the better.

The surface layer of the substrate is provided with a source impurity diffusion region (hereinafter referred to as a source region) and a drain impurity diffusion region (hereinafter referred to as a drain region), and the source region is relatively more than the drain region. It is a feature of the present invention that it is provided above. Further, a channel region is provided between the source region and the drain region of the second conductivity type. By disposing the drain region up to the inclined portion, a short channel device can be formed. An impurity having a conductivity type opposite to that of the substrate is implanted into the source region and the drain region, and the impurity concentration is preferably 10 ¹⁹ to 10 ²¹ ions / cm ³ . Further, a region having a higher substrate concentration than that of the bulk and the same conductivity type can be provided in the vicinity of the drain region. By providing this region, the generation efficiency of hot electrons is improved, and the writing speed can be increased. Further, the channel region is formed to have a sufficient depth that is not affected by the profile when forming another impurity region. As such a depth, Rp 0.1 to 0.4 μm is preferable.

Further, on this substrate, a floating gate electrode and a control gate electrode are laminated in this order so as to straddle the source region and the drain region. Further, a gate insulating film is provided between the substrate and the floating gate electrode, and between the floating gate electrode and the control gate electrode. Here, as a material used for each gate electrode, a known material can be used, and examples thereof include polysilicon. Further, the concentration and conductivity type of the impurities may be changed by diffusion or ion implantation on the entire surface of the floating gate electrode or locally. Furthermore,
The thickness of each of the floating gate electrode and the control gate electrode is preferably 3000 to 5000Å.

Further, as the material used for the gate insulating film, known materials can be used, and examples thereof include a film made of silicon oxide, silicon nitride, tantalum, a dielectric substance and the like. Also, oxide film-nitride film-oxide film (ONO
Structure). Further, the gate insulating film is formed thinner by the interlayer film between the control gate electrode and the floating gate electrode, and is selected so as not to be substantially related to the trap. That is, after dry O ₂ oxidation, argon (A
r) and ammonia (NH ₃ ) in an atmosphere of 1
Nitriding is performed at a high temperature of 000 ° C. or higher for about 10 to 30 minutes. As a result, moisture and OH radicals can be reduced from the gate insulating film and traps can be reduced. Here, the insulating film between the substrate and the floating gate electrode is preferably thinner on the source region side than on the drain region side. By making the source region side thinner than the drain region side, Fowler-Nordheim tunneling can easily occur on the source region side and the breakdown voltage on the drain region side can be improved. Hereinafter, the thin gate insulating film on the source region side is referred to as a first gate insulating film, and the thick gate insulating film on the drain side is referred to as a second gate insulating film. First
The thickness of the gate insulating film and the thickness of the second gate insulating film are preferably 70 to 100Å and 100 to 200Å, respectively.

The thickness of the gate insulating film between the floating gate electrode and the control gate electrode (hereinafter, this insulating film is referred to as a third gate insulating film) is preferably 150 to 300Å. This third gate insulating film is formed in order to improve the drawing efficiency.
It is also possible to make the drain region side thin and the source region side thick. A SiN film may be used as one layer of the insulating film in order to reduce charge leakage. Thereby, it is possible to prevent erroneous erasure such as internal photo emission.

The non-volatile memory of the present invention is constituted by the above-mentioned constitutional requirements. Here, the source region has an LDD structure, D, as shown in FIGS.
DD structure, PLDD (Profiled Lightly Doped Diffusi)
on) structure or DI (Double Implanted) -LDD structure. By forming the above structure on the source region side, the width of the depletion layer can be widened and the breakdown voltage can be improved. The reason why the above structure is not formed on the drain region side is to increase the electric field strength by making the junction concentration gradient steep in the drain region.

In the case of the LDD structure, the second region is formed on the channel region side.
The structure is such that a conductive type low concentration region is further formed, and the impurity concentration of this LDD low concentration region is 10 ¹⁷ to 10 10.
¹⁸ ions / cm ³ is preferred. Furthermore, the low-concentration region may be formed so as to cover a part or the whole of the end portion on the drain region side, and it is also possible to partially cover the lower portion of the source region (FIGS. 2B to 2C). See c)).

Further, in the case of the DDD structure, a low concentration region is formed so as to cover the source region, and the impurity concentration of this DDD low concentration region is 10 ¹⁸ to 10 ¹⁹ ions.
/ cm ³ is preferable (see FIG. 2 (a)). It should be noted that the DDD structure has an advantage that punch-through is less likely to occur than the LDD structure. Further, in the case of the PLDD structure, an impurity region is further formed so as to cover the LDD low concentration region and the source region in the LDD structure, and the impurity concentration of this PLDD low concentration region is 10 ¹⁷ to 1 1.
0 ¹⁹ ions / cm ³ is preferable (see FIG. 2 (d)).

In the case of the DI-LDD structure, the first conductivity type impurity region is formed on the channel region side, and the second conductivity type low concentration region is further formed on the surface layer of the impurity region on the source region side. (See FIG. 2E). The impurity concentration of the first conductivity type impurity region is 10 ¹⁶ to
10 ¹⁸ ions / cm ³ is preferable, and the impurity concentration of the second conductivity type low concentration region is preferably 10 ¹⁸ to 10 ²⁰ ions / cm ³ .

With the above structure, the withstand voltage of the drain region can be made lower than that of the source region, and the withstand voltage during the erase operation can be improved, which is preferable. Further, it is desirable to disperse the low-concentration region and the damaged region of 1 to 9 × 10 ¹⁴ ions / cm ² of the ion implantation profile for forming the source region later so as not to overlap in each implantation.
For example, in order to prevent the damaged region from overlapping in the silicon immediately below the blocking film edge, a gentle sidewall spacer may be extended on the blocking film sidewall and injected through it. This sidewall spacer can be easily formed by using a two-layer film having different etching rates and anisotropic etching.

Further, in the above description, the one used for the two-layer polycrystalline silicon structure has been described as an example, but it may be applied to one using the three-layer polycrystalline silicon structure, for example, one having an erase gate. . Further, instead of the element isolation oxide film, the element isolation can be performed by the gate electrode. In addition, a buried diffusion layer (bit line, etc.) under the element isolation oxide film
Can also be provided.

The method of manufacturing the nonvolatile memory of the present invention will be described below. First, a buffer oxide film having a film thickness of 1000 Å or more is formed on a semiconductor substrate having a desired conductivity type by a thermal oxidation method or the like. This buffer oxide film is provided in order to obtain a reproducible bird's beak length, to suppress the generation of dislocations and slips in this region of the silicon substrate, and to relieve the stress of the oxidation prevention film to be formed later. . The quality and thickness of this buffer oxide film depends on the shape of the inclined region and the crystalline state inside the silicon substrate in the hot electron generation region. Therefore, the quality and thickness of the buffer oxide film are consistent with the total process and device operation. In consideration of this, the conditions are empirically determined and determined. A photoresist or the like is applied on the buffer oxide film to form a pattern in which only the element formation planned region is opened.

Next, impurities are implanted into the semiconductor substrate to form a channel dope layer. Examples of the impurity material to be implanted include boron and the like when it is a p-type impurity, and phosphorus and the like when it is an n-type impurity. The implantation conditions are such that the implantation is performed to a sufficient depth so as not to be affected by the tail of the profile of the subsequent ion implantation, so the dose amount is 10 ¹² -1.
0 ¹³ ions / cm ² and implantation energy of 40 to 200 KeV are preferable. This injection amount is
It is extremely important because it depends on this concentration.

Next, the resist is removed and an oxidation prevention film having a film thickness of 700 to 1000 Å is formed by the CVD method or the like.
It is preferable to use a silicon nitride film as the oxidation prevention film. Next, the oxidation prevention film in the portion where the element isolation region is to be formed is selectively removed by etching using photoresist or the like. After removing the resist etc., SOG (spin on gra
ss) _{film, TEOS (Si (OC 2 H} 5) 4) film, PCVD · TEO
S / SOG / PCVD / TEOS film coating method, PC
The layers are stacked by a method such as the VD method, and sidewall spacers are formed on the sidewalls of the oxidation prevention film. PCVD / TEOS
The film is formed from Si (OC ₂ H ₅ ) ₄ and O ₂ . Next, in order to form the field dope layer, the implantation energy of 100 to
Impurities are implanted at 150 KeV and a dose of 10 ¹³ to 10 ¹⁴ ions / cm ² . As the impurities, known substances can be used. Further, since the sidewall spacers limit the implantation of impurities, the field dope layer can be formed only in a desired region.

Next, an element isolation oxide film is formed in a thickness of 1000 to 110.
It is formed by a method such as thermal oxidation at 0 ° C. (so-called locos method) or CVD method. By forming this element isolation oxide film,
The field dope layer is activated and redistributed to form an inversion prevention layer below the element isolation oxide film. The layout design is made so that the main part of the element does not come to the corner edge portion of the element isolation oxide film.

Next, a part of the element isolation oxide film is removed by anisotropic etching such as RIE using a resist mask. Further, the anisotropic etching is switched to isotropic etching using hydrofluoric acid or the like, and the element isolation oxide film under the oxidation prevention film is etched by a predetermined amount. Next, SOG on the entire surface
Use a method such as coating a film to obtain a film thickness of 4000 to 8000Å
To deposit. This film may be subjected to an etch-back treatment if necessary.

Next, the oxidation prevention film is removed by etching using hydrofluoric acid or the like, and the SO formed on the oxidation prevention film is removed.
Lift off the G film. After that, the oxide films at the ends of the buffer oxide film and the element isolation oxide film are removed. The removal method is
Although known methods can be used, it is not preferable to use an etchant that affects the silicon interface, and dry etching is not suitable. As a preferable etching method, for example, wet etching using HF can be used.

Since the sloped portion formed by oxidation has a gentler shape than the slope formed by etching or the like, the step coverage is improved, and the floating gate electrode or the like formed on the upper portion later is improved. Stress can be reduced, and reliability in miniaturizing the device can be improved. In addition, oxidation has the advantage that damage to the silicon interface is less than that of etching, and a stable device can be manufactured. In addition, the length of the bird's beak that influences the size of the inclined portion can be easily controlled by controlling the film thickness of the buffer oxide film, and the fine dimension can be easily adjusted.

Next, the resist and the like are removed, and the first and second
A gate insulating film is formed. When an oxide film is used for the insulating film, it can be formed by thermal oxidation. The oxidation method is determined in consideration of the type of device and the consistency between processes, and examples thereof include oxidation by dry O ₂ and pyrogenic oxidation. The oxidation temperature is 850 to 950 ° C., which is a relatively low temperature. Further, it is particularly preferable to perform the oxidation with dry O _{2 at} about 900 ° C. This is because the oxide film formed by dry O ₂ (which may be pyrogenic to reduce the trap level) has the largest activation energy and is easy to control, exhibits excellent dielectric breakdown voltage characteristics, and has a threshold value. This is because it has many advantages such as not shifting and not increasing the trap density in the oxide film. Although the exposed substrate is oxidized by this oxidation, the film thickness of the oxide film in the sloped portion where the element isolation oxide film is removed becomes thicker than the oxide film in the buffer oxide film portion. Here, the insulating film in the inclined portion is the second gate insulating film, and the oxide film in the buffer oxide film portion is the first gate insulating film. In this way, oxide films having different thicknesses can be formed in a single oxidation process.

It is also possible to pre-inject a material such as argon, which is inactive and promotes thermal oxidation, into the region where the first gate insulating film is to be formed, without or in combination with the above-mentioned implantation. Further, Si may be ion-implanted into the region where the first gate insulating film is formed to weaken the bonding force of the Si crystal. This Si ion implantation is also effective in suppressing the diffusion of impurities in the buffer oxide film into Si. After forming the insulating film, annealing may be performed in an atmosphere such as H ₂ in order to adjust the impurity concentration in the insulating film. Further, since oxidation is performed at a relatively low temperature, high interfacial fixed charges are generated in the insulating film, but this can be reduced by annealing in an inert atmosphere of N ₂ , Ar or the like. Further, a better film can be formed by sacrificing the formation region before forming the first gate insulating film and the second gate insulating film.

Next, polycrystalline silicon or the like is laminated on the entire surface by the CVD method or the like, and etching is performed to form a floating gate electrode at a desired position. In addition, H
A TO film and a second laminated film formed by thermal oxidation of the TO film may be used.
Next, after removing the SOG film by a known etching method, impurities are implanted by using the floating gate electrode as a mask to form source / drain regions. The implantation conditions are implantation energy of 30 to 80 KeV and dose of 10 ¹⁵ to 10 ¹⁶ ions.
/ cm ² is preferable. The n ⁺ implantation amount into the floating gate electrode is conditioned so as to adjust the interface potential barrier between the polycrystalline silicon / implanted oxide film according to the area of the oxide film for charge injection. Design rules such as sheet resistance values of the source region and the drain region are matched with the adjustment of the interface potential barrier. In this implantation, since the source region is formed through the gate insulating film, it can be formed shallower than the drain region. Here, a deeper channel region can be provided by implanting Si ions into the inclined portion of the channel region layer through the floating gate electrode.

Next, the floating gate electrode is oxidized or the like to form a third gate insulating film. A control gate electrode is formed by stacking polycrystalline silicon or the like on the entire surface and etching it. Further, an oxide film is formed by oxidizing the entire surface, and then a sidewall spacer is formed on the side wall of the control gate electrode on the source region side by using a resist or the like, and the floating gate electrode is isotropically etched. By side-etching, the overlap between the control gate electrode and the floating gate electrode can be controlled.

After that, according to a normal process, the interlayer insulating film is formed.
Are stacked, contact holes are opened, and metallization is performed.
To form a passivation film.
Form a non-volatile memory with a self-aligned structure.
Can be made. As an interlayer insulating film, PCVD.T
An EOS / SOG / PCVD TEOS film can be used.
Further, a PCVD / TEOS film is deposited on the SOG film.
Before the SOG film surface is O ₂If hit with plasma, SOG film
Can improve the adhesion between PCVD and TEOS film
Wear.

When forming an LDD structure, after the floating and control gate electrodes are etched in a self-aligned manner,
By masking the drain region with a resist or the like and implanting impurities by tilt rotation (implantation angle 50 to 70 °)
Can be realized. The implantation conditions at that time are as follows: implantation energy 40 to 80 KeV, dose amount 10 ¹⁴ to 10 ¹⁶ ions.
/ cm ² is preferable.

When forming a DDD structure, ³¹ P
^This can be achieved by implanting ⁷⁵ As ⁺ with a high concentration after implanting ⁺ with a low concentration. The implantation conditions at that time are as follows: implantation energy 30 to 80 KeV, dose amount 1
It is preferably 0 ¹⁴ to 10 ¹⁶ ions / cm ² . Furthermore, P
In the case of forming the LDD structure, it can be realized by rotational implantation in which the implantation angle is changed stepwise and the implantation energy is changed stepwise. The implantation conditions at that time are: implantation energy 20 to 100 KeV, implantation angle 30 to
It is preferable that the angle is 70 ° and the dose amount is 10 ¹³ to 10 ¹⁶ ions / cm ² . Further, it is desirable that the implantation conditions are divided so that the peak concentration of the profile is about 10 ¹⁹ to 10 ²¹ ions / cm ³ and that a sufficient cooling period is provided between the implantations. For example, in the case of As, 80 KeV and 2 ×
10 ¹⁵ ions / cm ² , 40 KeV and 1.5 × 10 ¹⁵ ions / c
Implantation may be performed at m ² , 20 KeV, and 7 × 10 ¹⁴ ions / cm ² .

When forming a DI-LDD structure
Is used as a mask on the semiconductor substrate with the floating gate electrode as a mask.
Implantation energy of 20 to 60 KeV and dose of 10¹²
-10 ¹⁴ions / cm²Inject in a degree. Then oxidize the entire surface
A film is formed and acid is formed by RIE (Reactive Ion Etching) method.
Etching back the oxide film, gate insulating film and floating gate electrode
Sidewall spacers are formed on both sides of the pole. The
Mask sidewall spacers and floating gate electrodes
As the substrate, arsenic or the like is implanted with an implantation energy of 20 to 60K.
eV, dose 10¹⁴-10¹⁶ions / cm²Inject in a degree
It After this, a thickness of 50 is obtained by the CVD (chemical vapor deposition) method.
A SiN layer of about 00Å is formed. Then on the SiN layer
The SiN layer is flattened by applying a resist.
Further, the drain region side is masked from the gate electrode, and Si
Etching the N layer and the resist at the same etching rate
The SiN layer and the resist until the surface of the gate electrode is exposed.
Etch back the strike. Then wet the SiN layer
The upper part of the sidewall spacer (3 /
Selective etching until about 8) is exposed. Next
While leaving the SiN layer on the semiconductor active region,
Selectively remove only the id wall spacer,
Exposing the semiconductor substrate. And the gate electrode and Si
With the N layer as a mask, boron or the like is implanted into the exposed portion.
Gee 70-100 KeV, Dose 10¹²-10¹⁴ions
/cm²DI-LDD structure is formed by injection
Is done.

Furthermore, in addition to the above-mentioned method, JP-A-5-9051
The oblique ion implantation method described in Japanese Patent No. 9 may be used.
That is, by setting the implantation angle to 30 to 60 ° and implanting ions at a predetermined implantation energy and dose amount, DI-
LDD structures can be formed. In the above description of the manufacturing method of the present invention, a process utilizing the dose dependency of the substrate of the gate insulating film was proposed, but the manufacturing method of the present invention is not limited to this, Needless to say, it can be created by the same manufacturing method.
However, in that case, further cleaning and automation, and very strict process control will be obligatory. For example, since the low-concentration impurity diffusion layer 12 on the source region side in the manufacturing method of the present invention is formed by oblique ion implantation, the concentration of the portion overlapping the floating gate electrode is not uniform, and the desired area is not required. Was extremely difficult to control. In addition, the side surface of the floating gate electrode and the gate insulating film directly below the floating gate electrode are irradiated with high energy of ions, resulting in a decrease in breakdown voltage and Fowler-Nordheim.
There is a problem that the erase operation becomes unstable due to the tunnel effect. As a coping method, the low concentration impurity diffusion layer 12 may be formed before forming the gate insulating film.

That is, FIGS. 21A to 21C and FIG.
As shown in (a) to (c) and FIGS. 23 (a) to (c), after exposing the surface of the substrate in FIG. 15, the exposed surface is thermally oxidized to form a sacrificial oxide film 13 of about 300 Å. (Also serves as an oxide film before implantation) is formed (see FIG. 21A). Next, a photoresist pattern 14 serving as an LDD region forming mask is formed (see FIG. 21B).

Then, the photoresist pattern 14 is formed.
Ions such as arsenic are implanted to form a low-concentration impurity diffusion region by using the as a mask (see FIG. 21C).
Further, the photoresist pattern 14 and the sacrificial oxide film 13
Are removed by etching (see FIG. 22A). Next, a gate insulating film is formed (see FIG. 22B), and the floating gate electrode 7 is etched by matching the edge of the source region side with the region where the high-concentration source region is formed (see FIG. 22C). .

Next, the SOG is removed, and ion implantation is performed to form the source region and the drain region (FIG. 2).
3 (a)). Further, the control gate electrode 9 is formed, but at this time, the low concentration impurity diffusion layer 12 and the floating gate electrode 7 are formed.
The position of the edge of the control gate electrode 9 on the source region side is determined so as to determine the overlapping area with (FIG. 23B).
reference).

As a result, the low concentration impurity diffusion layer 12
The area of the overlapping portion between the floating gate electrode 7 and the floating gate electrode 7 is determined. Here, the overlap may be about 0.2 μm below the floating gate electrode 7 (see FIG. 23C). In the present application, the coupling ratio [C4 / (C4 + C3 + C2 + C1 + C
5)] is, for example, 0.5 to 0.8. After C4 is determined, the capacity of the overlapping portion is determined.

Further, in the present invention, since the offset gate is not adopted, and the bulk in which the channel dope layer is formed may be used to form the erasing gate insulating film with high accuracy. Next, the electrically coupled state of the nonvolatile memory of the present invention will be described with reference to FIGS. V in the figure
se is the erase voltage to the source region 10, Vfg is the potential of the floating gate electrode 7, C4 is the parasitic capacitance between the control gate electrode 9 and the floating gate electrode 7, and C3 is between the floating gate electrode 7 and the substrate 37. Capacitance, C2 is floating gate electrode 7 and substrate 38
, And C1 is the capacitance between the floating gate electrode 7 and the drain region 11. Here, the film thickness of the first insulating film 5 is d
When it is 1, the electric field Ee at the time of erasing in the first insulating film 5 is expressed by the following formula (I).

Ee = Vse (C5 + C4 + C3 + C2) / d1 (C5 + C4 + C3 + C2 + C1) (I) To erase by utilizing the tunnel effect, it is necessary to control d2 to an appropriate thickness. From this, if the area between the first insulating film 5 and the source region 10 cannot be controlled to be small, C1 becomes extremely large and Ee becomes small. Therefore, in the present invention, in order to obtain the desired Ee,
It is possible to provide a simple method for manufacturing a non-volatile memory in which the above capacity can be optimally selected and a constant yield can be secured.

On the other hand, when the film thickness of the second insulating film 6 at the pinch-off point is d2 and the write voltage to the control gate electrode 9 is Vgw, the voltage of the floating gate electrode 7 that contributes to drawing hot carriers in the second insulating film. Vfg is represented by the following formula (II). Vfg = Vgw (C4 / (C5 + C4 + C3 + C2 + C1)) (II) In the present invention, the characteristics such as the area, film thickness, and film quality of each region forming C1 to C4 can be appropriately set, and manufacturing variations can be eliminated. be able to. Therefore, even if the memory becomes fine, the characteristics of writing and erasing can be maintained.

Further, since C2 is formed by the substrate 38, the second insulating film 6 and the floating gate electrode 7, by increasing C2 in the above formula (I), C1
It is possible to mitigate the effects caused by the increase in Furthermore, the present inventor has found that the nonvolatile memory having the tilted channel has the following problems.

That is, since the floating gate electrode is formed by photolithography, it is necessary to allow for an alignment margin. Therefore, in the nonvolatile memory having the tilted channel, it is difficult to align the floating gate electrode with the tilted portion, and there is a problem that the area of the memory element cannot be reduced. Further, in the above-mentioned nonvolatile memory having the tilted channel, since the control gate electrode is formed on the tilted floating gate electrode, the area of the region where the floating gate electrode and the control gate electrode are stacked can be reproduced with good reproducibility. It was difficult to stack the control gate electrode while adjusting.

This means that it is difficult to control the coupling capacitance between the control gate electrode and the floating gate electrode and the capacitance between the source region and the floating gate electrode to desired values. . Therefore, the inventor of the present invention has also found a structure of a tilted channel type nonvolatile memory capable of reducing the size of a memory cell and a manufacturing method thereof.

Further, even in the floating gate electrode formed in the channel region having the inclined portion, the non-volatile memory which can make the coupling capacitance ratio between the control gate electrode and the floating gate electrode constant has been found. The nonvolatile memory and the manufacturing method thereof are described above, but the manufacturing can be performed in the same manner as the manufacturing method up to the step of determining the position of the end portion of the floating gate electrode on the drain region side.

However, the side wall spacer used for forming the field dope layer may or may not be formed. That is, even if the field dope layer is formed in the active region, in the case of the nonvolatile memory having the fine floating gate electrode as in the present invention, it is unlikely that the field dope layer approaches the vicinity of the channel region. Therefore, even if the sidewall spacers are not formed, the concentration of the impurity ions derived from the field dope layer existing in the active region is low, and the high concentration impurity ions used in the subsequent formation of the source region and the drain region completely counter the impurity ions. Be doped. Therefore, the formation can be omitted.

The conductivity type of the impurity ions for forming the field dope layer is opposite to that of the impurity ions for forming the drain region. Therefore, if the depth of the field dope layer and the depth of the junction of the drain region are matched, the expansion of the depletion layer in the drain region can be suppressed.
As a result, the electric field can be concentrated in the channel region, so that the generation of hot carriers at the pinch-off point can be promoted.

After the position of the end of the floating gate electrode on the drain region side is determined, a silicon nitride film or the like is deposited on the entire surface by the PCDV method to a thickness of 4000 to 8000Å. By forming a thin base oxide film on the surface of the substrate before depositing the silicon nitride film, the stress of the silicon nitride film can be relaxed. However, if the underlying oxide film is thick, the thickness of the gate insulating film becomes uneven at the end portion on the drain region side, which is not preferable. Next, the element isolation region and the opening formed in the element isolation region are masked with a photoresist or the like to remove the silicon nitride film.

After removing the mask, impurity ions are implanted into the substrate below the edge portion of the element isolation oxide film. By this implantation, the impurity ion concentration gradient can be formed in the inclined channel region. Here, the concentration gradient is a gradient in which the concentration of impurity ions increases from the source region toward the pinch-off point. In order to obtain the concentration gradient, it is preferable to use impurity ions having a small diffusion coefficient (for example, boron ions).

Next, the first and second gate insulating films are formed. The forming method can be performed in the same manner as the above manufacturing method. Next, polycrystalline silicon or the like is laminated on the entire surface by the CVD method or the like. Then, an SOG film is applied so that the polycrystalline silicon existing in the step portion formed by the silicon nitride film is exposed. After removing the exposed polycrystalline silicon, a flat layer is repeatedly formed one or more times while etching back a film having a good step coverage such as a CVD silicon oxide film.

Next, anisotropic etching is performed with the end point being the point at which the polycrystalline silicon layer is exposed. Here, a film having a good step coverage remains on the polycrystalline silicon. Using this film as a mask, polycrystalline silicon is subjected to anisotropic reactive etching to form a floating gate electrode.
The etchant used for this etching is preferably one that selectively etches polycrystalline silicon and silicon oxide. Examples of the etchant include hydrogen bromide and the like.

Next, impurity ions are implanted using the floating gate electrode and the silicon nitride film formed by the PCVD method as a mask. The implantation conditions can be the same as the conditions for forming the LDD structure in the above manufacturing method. The implant for the LDD structure shifts toward the channel due to the subsequent oxidation process on the floating gate electrode. Therefore, it is desirable to implant impurity ions having a high diffusion coefficient in anticipation of the shift amount. The area of the F-N region is determined by the correlation between the amount of impurity ion diffusion in the lateral (channel) direction of the LDD structure after the completion of all steps and the amount of shift in the channel direction due to the oxidation of the sidewall of the floating gate electrode. To be done.

Next, after removing the silicon nitride film by PCVD by a known method, the entire surface of the substrate is oxidized to form an interlayer insulating film. After that, impurity ions are implanted using the floating gate electrode as a mask to form a source region and a drain region. The injection conditions can be the same as the conditions in the manufacturing method. US Pat. No. 5,23
If the multi-step implantation method described in No. 8,858 is used, a source region and a drain region having more stable characteristics can be formed.

Next, a nitride film is formed on the entire surface and isotropic and anisotropic etching is performed to form a nitride film sidewall spacer for preventing oxidation on the sidewall of the floating gate electrode. Then, the entire surface of the substrate is oxidized to a thickness of 1000 to 30.
It is possible to form a floating gate electrode having a 00 Å interlayer insulating film on the top. By adjusting the thickness of the interlayer insulating film, the capacitive coupling between the floating gate electrode and the control gate electrode can be made dominant by the coupling on the side wall of the floating gate electrode on the drain region side. Further, the thermal oxidation condition at this time determines the shift amount of the side wall of the floating gate electrode on the source region side in the channel direction, and also determines the lateral diffusion amount of impurities in the LDD region on the source region side. To do. This oxidation amount also improves the step coverage of the word line, so it would be better to form a thick interlayer insulating film, but the floating gate electrode would also reduce the channel width by that amount, and the device design rule Careful attention should be paid to the setting of process conditions.

The thick interlayer insulating film on the floating gate electrode may be formed by oxidizing the entire surface of the substrate before removing the silicon nitride film by PCVD in order to shorten the process. Since the interlayer insulating film formed by this method has a thick insulating film on the side wall of the floating gate electrode on the source region side, a sufficient offset between the source region and the floating gate electrode can be secured. As a result, the breakdown voltage of the non-volatile memory can be improved.

Next, the nitride film side wall spacers are removed, and the thin oxide film on the side walls of the floating gate electrode is removed.
After that, an interlayer insulating film having a desired thickness is formed by thermal oxidation or the like. Incidentally, if the side wall of the floating gate electrode is sacrificial-oxidized in this step, the reliability of the interlayer insulating film can be improved. After that, polycrystalline silicon is deposited on the entire surface, and a control gate electrode having a desired shape can be formed through known steps.

It is preferable to form the control gate electrode as follows, because the step coverage of the control gate electrode is improved and the capacitive coupling between the control gate electrode and the floating gate electrode is more reliable. That is, polycrystalline silicon is deposited on the entire surface,
Sidewall spacers are formed on the sidewalls of the floating gate electrode using isotropic and anisotropic etching. By removing the oxide film formed on the sidewall spacers and depositing polycrystalline silicon by is-situ, a control gate electrode electrically connected to the sidewall spacers can be formed.

Further, in order to reduce the sheet resistance of polycrystalline silicon on the control gate electrode, impurity ions may be implanted and a refractory metal silicide may be formed on the control gate electrode. The implantation condition is the implantation energy of about 20 ke.
v, P, and the dose amount is 5 × 10 ¹⁵ to 8 × 10 ¹⁵ / cm ² . The ratio of refractory metal to silicon in the silicide is preferably 1/3. Examples of the refractory metal include W and Ti.

After that, the nonvolatile memory is formed through the same steps as the manufacturing method.

[0072]

According to the nonvolatile memory of the present invention, the semiconductor substrate of the first conductivity type and the surface layer of the main surface of the semiconductor substrate are formed at a constant interval, and at least one of the surfaces has a part thereof. A second conductivity type source impurity diffusion region and a drain impurity diffusion region formed on a surface having a crystal plane orientation different from the main surface; a channel region provided between the source impurity diffusion region and the drain impurity diffusion region; A gate insulating film provided on the channel region, a floating gate electrode provided on the gate insulating film, and a control gate electrode provided at least partially on the floating gate electrode via an interlayer insulating film are provided. However, the channel region has an inclined portion that is in contact with the drain impurity diffusion region and has a surface having a crystal plane orientation different from the main surface of the semiconductor substrate. Since the object diffusion region is provided relatively above the drain impurity diffusion region, the channel length can be made substantially longer, the area is small, the writing and erasing speeds are fast, Provided is a nonvolatile memory that prevents erroneous erasure during reading, is excellent in mass production and miniaturization, and has excellent durability for frequent writing / erasing and reading.

In the present invention, the drain avalanche hot carrier injection mechanism shown in FIG. 37 (a) is used as the hot electron injection mechanism. It is not certain whether such an injection mechanism is provided, but it is conceivable that hot electrons are injected by, for example, a substrate hot electron injection (FIG. 37 (b)), secondary collision ionization hot electron injection (FIG. 38) mechanism, or the like. Needless to say, it can be applied to a single power supply and a lower bias voltage by changing the injection mechanism.

Further, in the method for manufacturing a nonvolatile memory of the present invention, a step of forming an element isolation insulating film in a predetermined region of one main surface of the first conductivity type semiconductor substrate, and at least Fowler-Nordheim. Second in the area where the tunnel occurs
Forming a conductive type low concentration impurity diffusion region; forming a gate insulating film on the active region in which the low concentration impurity diffusion region is formed; and floating gate electrode floating with the low concentration impurity diffusion region. A step of forming the gate electrode and the control gate electrode so as to overlap with each other in an area determined according to a capacitance, a step of forming an interlayer insulating film on the floating gate electrode, and the floating gate electrode and at least a part thereof. Forming a control gate electrode patterned in a stacked form, and using the control gate electrode and the floating gate electrode as a mask, impurities of the second conductivity type are implanted at a high concentration into the active region to form a source region and a drain region. Since it includes the steps, the gate oxide film is not damaged and the breakdown voltage is not lowered when the low-concentration impurity diffusion region is formed. A plan view of the memory cell of the present invention is shown in FIG. 39. Since the double diffusion is not used for forming the source region, the area of the source region can be reduced.

According to the nonvolatile memory and the manufacturing method of the present invention in which the floating gate electrode is present on the sloped portion of the channel region, the floating gate electrode conventionally formed by photoetching is removed from the bird's beak portion at the LOCOS end. Thus, the floating gate can be formed by etching the polycrystalline silicon by RIE using the insulating film selectively formed in the inclined region formed as a mask. Therefore, the cell area can be reduced as compared with the conventional nonvolatile memory. Further, in the operation of the nonvolatile memory of the present invention, if the ion implantation energy of channel doping is adjusted so that Rp (implantation depth) comes to the pinch-off point at the time of writing, the writing efficiency is improved. The coupling capacitance ratio between the control gate electrode and the tilted floating gate electrode is mostly determined by the capacitive coupling area between the side wall of the control gate and the floating gate, so the area can be made constant by controlling the thickness and width of the floating gate electrode. can do. Therefore, even if the floating gate electrode is inclined, the variation of the coupling capacitance ratio with the control gate electrode hardly occurs.

[0076]

EXAMPLES The present invention will be described in more detail with reference to examples below, but the present invention is not limited to the following examples, and various modifications can be made based on the technical idea of the present invention described above. is there. Example 1 A case where a flash memory cell transistor and a manufacturing method thereof according to the present invention is applied to a self-aligned flash memory cell transistor will be described with reference to the drawings.

FIG. 1 is a sectional view of a single cell in the flash memory of the present invention. In the figure, 1 is a P-type semiconductor substrate, 2 is a field dope layer, 3 is an element isolation oxide film (L
OCOS). Reference numeral 4 is a channel region, 5 is a first gate insulating film, 6 is a second gate insulating film formed on the inclined portion and using the channel region 4 as a material, 7 is a first polysilicon layer (floating gate electrode), 8 is a third gate insulating film, 9 is a second polysilicon layer (control gate electrode), 1
Reference numeral 0 is a source region (N ⁺ -type impurity region), 11 is a drain region (N ⁺ -type impurity region), and 12 is an LDD region for improving the withstand voltage during an erase operation.

The operating principle of the flash memory of this embodiment is the same as that of the conventional example, but the second gate insulating film 6 is a bird's beak formed by bird's beak of an element isolation oxide film.
It is formed on the beak length inclined part (about 0.6 to 0.8 μm),
An important feature is that the second gate insulating film 6 is formed on the channel region 4 which is controlled in the silicon substrate 1 in advance with high precision. That is, writing can be performed by applying a high voltage to the drain region 11 and the control gate electrode 9, and attracting the generated hot carriers by the control gate electrode 9 to accumulate them in the floating gate electrode 7. For erasing, a high voltage is applied to the source region with the control gate electrode 9 grounded (or negative bias),
This can be performed by discharging the accumulated charge in the floating gate electrode 7 using FN tunnel injection. At this time, charges are discharged through the thin first gate insulating film 5. Further, since the drain region 11 is originally formed in a region where an element isolation oxide film is formed, carrier charges are directed from the upper side to the lower drain region 11 and travel to the second gate insulating film 6 at a constant angle. It will be.

Therefore, the charges are more likely to jump into the second gate insulating film 6 as compared with the conventional structure in which the charges proceed almost horizontally to the semiconductor surface. Therefore,
The efficiency of drawing hot carriers into the floating gate electrode 7 can be improved. On the other hand, since the structure is such that the charges are extremely unlikely to jump into the first gate insulating film 5, the LDD region 12 ensures the breakdown voltage of the edge portion in the channel length direction to prevent the occurrence of avalanche breakdown on the source side. It becomes possible to suppress. Therefore, restrictions on the thickness of the gate insulating film, the erase voltage, and the write voltage are relaxed, and a flexible and high-performance device can be realized.

Further, by making the second gate insulating film thick and the first gate insulating film thin, basic operations that are repeatedly performed such as writing to the floating gate electrode by the electric field of the control gate electrode and erasing by the electric field of the source region. Can be improved over the conventional flash memory. Furthermore, the basic operation can be further improved by adjusting the film characteristics of the gate insulating film and the capacitive coupling between each electrode or the source / drain region and the gate insulating film.

Further, since the first gate insulating film is thinner than the second gate insulating film during writing, the channel region under the first gate insulating film is inverted more strongly than the channel region under the second gate insulating film. Therefore, since the channel becomes narrower under the thick oxide film region, electrons easily move under the floating gate electrode, and writing can be easily performed.

A method of manufacturing the device shown in FIG. 1 will be described. 6 to 20 are cross-sectional views of a single cell for explaining the method of manufacturing the self-aligned nonvolatile semiconductor memory device of the present invention. First, as shown in FIG. 6, a buffer oxide film 22 of 1000 Å was grown on a P-type silicon substrate 1 whose surface oxygen concentration was sufficiently lowered by gettering or the like.
Reproducible bird's beak length
ngth), in order to suppress the occurrence of dislocations and slips in this region of the silicon substrate and to alleviate the stress of 10 ¹⁰ dyn / cm ² of the silicon nitride film to be formed later, 1000 Å or more. It is preferable to have an underlying oxide film. In this example, a bird's beak length of 0.8 micron was formed. Then, a photoresist pattern 23 having an opening only in the element formation region was formed on the buffer oxide film 22.

Then, as shown in FIG. 7, boron is added at a dose of 5 × 10 ¹² ions / cm ² and an implantation energy of 100 KeV.
Then, the channel dope layer 24 was formed by implanting to a sufficient depth (Rp 0.3 μm or more) so as not to be affected by the tail of the boron high concentration implantation profile. This ion implantation needs to be performed in an extremely clean apparatus and environment, and an apparatus that does not sputter heavy ions was used.

Then, as shown in FIG. 8, the photoresist pattern was removed, and a silicon nitride film serving as an oxidation-preventing film was deposited by 1000 liters. Then, on this silicon nitride film, a photoresist pattern 26 was formed in which only an area where an element isolation oxide film for isolating the element area into an island shape is formed is opened. By selectively removing the silicon nitride film using the pattern 26 as a mask, a silicon nitride film pattern 25 in which an element isolation oxide film formation portion is opened
Was formed.

Next, as shown in FIG. 9, after removing the resist pattern 26 by etching, SOG is formed on the entire surface.
The silicon nitride film pattern 25 is formed by applying a film.
A side wall spacer 27 for limiting the passage of ion implantation was formed on the side wall of the opening. Subsequently, boron for forming a channel stopper is implanted with an implantation energy of 40 KeV,
Ion implantation was performed under the condition of a dose amount of 5 × 10 ¹³ ions / cm ² to form the field dope layer 28.

Then, as shown in FIG. 10, wet oxidation at 1000 ° C. was performed to grow a silicon oxide film on the exposed surface of the substrate 1 to form an element isolation oxide film 29. that time,
The boron atoms of the field dope layer 28 were activated and redistributed to form an inversion prevention layer 30 under the element isolation oxide film 29. Next, after forming a resist pattern 214 as shown in FIG.
Using the silicon nitride film 25 as a mask and anisotropic etching, part of the element isolation oxide film 29 was removed.

Next, as shown in FIG. 12, isotropic etching was performed to etch the element isolation oxide film 29 under the silicon nitride film 25 by a predetermined amount. Further, as shown in FIG. 13, the SOG film 215 was applied while being appropriately etched back to be deposited with a thickness of 6000 Å. Next, as shown in FIG. 14, the SOG film formed thereon was lifted off by etching the silicon nitride film 25.

Then, as shown in FIG. 15, the end portions of the buffer oxide film 22 and the element isolation oxide film 29 were removed. Thereafter, as shown in FIG. 16, the entire surface was thermally oxidized at 900 ° C. to form the first gate insulating film 5 and the second gate insulating film 6. Next, as shown in FIG. 17, a polysilicon layer was deposited on the entire surface to a thickness of 1500Å, and the polysilicon layer was etched using a resist pattern to form the floating gate electrode 7.

Then, as shown in FIG. 18, LOCOS
Using the oxide film 22 and the floating gate electrode 7 as a mask, impurities were implanted at a high concentration to form the source region 10 and the drain region 11. At this time, since the source region 10 is formed by implanting impurities through the gate insulating film 5, the source region 10 is formed shallower than the drain region 11. Furthermore,
Even if part of the floating gate electrode (for example, the drain side) is masked by ion implantation and ion implantation is performed again to partially differ the dose amount of the floating gate electrode and increase the dose amount of the source and drain regions. Good.

Further, as shown in FIG. 19, the surface of the floating gate electrode 7 was oxidized to form a third gate insulating film 8.
Then, a polysilicon layer was formed on the entire surface, the polysilicon layer was etched using a resist pattern, and a control gate electrode 9 was formed through an oxidation step. Further, in order to reduce the sheet resistance of polycrystalline silicon on the control gate electrode,
Arsenic is also used for the control gate electrode at 40 KeV and the dose is 3 × 1.
Ion implantation at 0 ¹⁵ / cm ² and DC at the control gate electrode
The refractory metal silicide layer may be formed by sputtering or the like. The composition ratio (M / Si) of the refractory metal and silicon in the silicide was set to about 1/3.

After that, as shown in FIG. 20, the ends of the control gate electrode 9 and the floating gate electrode 7 were aligned in a self-aligned manner, and the entire surface was oxidized. Next, impurities were injected from an oblique direction while rotating the substrate to form the LDD structure 12 under the floating gate electrode 7 on the source region side. After that, an interlayer insulating film 43 is formed according to a normal process, a contact hole is formed and a metallization 44 is performed, and a passivation film (not disclosed) is formed.
A flash memory having a self-aligned structure using the present invention is completed (see FIG. 1).

A plan view of the flash memory shown in FIG. 1 is shown in FIG. In the figure, 15 is a Fowler-Nordheim tunnel region, 16 is a control gate line, and 17 is a floating gate electrode and a channel region. In the above flash memory, the surface impurity concentration of the source region overlapping the gate electrode is 10 ¹⁸ io in the LDD low concentration region when the gate insulating film has a thickness of 60 to 100 Å.
ns / cm ³ or less, and the high-concentration region is preferably 10 ¹⁹ ions / cm ³ or more. This is to suppress an increase in leak current due to the Zener phenomenon in the impurity diffusion layer immediately below the gate electrode when using a thin gate insulating film as in the present invention.

Further, the operating method of the present invention will be described with reference to FIGS. 24 (a), 24 (b) and 25. Note that FIG.
25A and 25B, 1 is a P-type semiconductor substrate, 4
Is a channel region, 5 is a first gate insulating film, 6 is a second gate insulating film formed on a sloped portion and using the substrate of the sloped portion as a material, 7 is a floating gate electrode, and 8 is a third gate insulating film. Film, 9 is a control gate electrode, 10 is a source region, 1
Reference numeral 1 is a drain region, 12 is an LDD structure for improving the withstand voltage during an erase operation, and 13 is a depletion layer.

In FIGS. 24A, 24B, and 25, the traveling direction of electrons accelerated in the channel region from the source region to the drain region is the shape of the channel region at the time of entering the inclined portion. Turn to. Therefore, the progress in the substrate is distorted (not accurately stated, but dislocation composite defect portion is distorted due to edge stress at the time of element isolation oxide film formation) and the edge of the depletion layer of the drain region is formed at this inclined portion. The generation of hot electrons is promoted by the synergistic effect with the high electric field generated by the overlapping of the portions.

In the cell provided with the source region relatively above the drain region, the gate insulating film on the drain region side has a sloped portion ((111) plane of the silicon substrate when a (100) silicon substrate is used. (Approx.) Is formed as a material, so that the drain region side inclined portion is formed thicker than the source region side in the same thermal oxidation step. Therefore, it is easier to take measures against erroneous erasing at the time of reading, as compared with the device having the drain region above. That is, in order to increase the thickness of the gate insulating film on the drain region side, it is possible to omit the forming step, which is the most difficult in practical level, of forming the impurity layer.

Further, in view of the use of a single power source and the reduction of the applied voltage, the advantages of the devices shown in FIGS. 24 (a) and 24 (b) and FIG. Description will be made by taking the writing of the type as an example. First, positive voltages Vd and Vcg are applied to the drain region and the control gate electrode, respectively.
Is applied. At this time, assuming that the substrate and the source region have the same potential and Vs = 0, the current Id flowing in the channel region can be approximated by the following equation.

[0097]

[Equation 1]

Here, d1 is the thickness of the gate insulating film in the planar channel region, d2 is the thickness of the gate insulating film in the inclined channel region, εox is its conductivity, μn is the mobility of electrons, and 11 is the planar channel region. The execution channel length, W is the channel width. For convenience, it is assumed that the conductivity of the gate insulating film in the planar channel region and the conductivity of the gate insulating film in the inclined channel region are about the same.

Vt is a threshold voltage for the floating gate electrode and depends on the execution channel length 1. Vf is the potential of the floating gate electrode and is represented by the following equation.

[0100]

[Equation 2]

Here, Cfs is the capacitance between the floating gate electrode and the source region, Cfssl is the capacitance between the floating gate electrode and the inclined channel region, Cfss2 is the capacitance between the floating gate electrode and the planar channel region, and Cfd is the floating gate electrode and the drain. The capacitance between regions, Cfc, is the capacitance between the floating gate electrode and the control gate electrode. Qf is the source current
This is the amount of charge in the floating gate electrode generated by the injection of electrons, which are accelerated by the electric field between the drain regions and obtain sufficient energy, into the floating gate electrode. Qf is determined depending on the rate γ of hot carriers injected into the gate insulating film. ΓI for channel current Id
The time integral of d is

[0102]

(Equation 3)

It is represented by At this time, the electric field strength in the gate insulating film is

[0104]

[Equation 4]

Since it is given by, the time integral is approximated by the following equation.

[0106]

(Equation 5)

Where

[0108]

(Equation 6)

Where S1 is the sum of the area of the effective channel length ([l1 + l2] × W) and the area where the floating gate electrode and the source region overlap each other. By integrating this, the write time Tw of this transistor is

[0110]

(Equation 7)

It becomes a function of Cff1 and Cff2 are film thickness d
Since it is determined by making 1 and d2 different or by setting l1 + l2 to the optimum value, adjusting this value makes it easier to adjust the writing time than the conventional structure. Further, as described above, the current in the channel region is bent, so that the injection efficiency in that portion is improved.

Next, three basic operations of this device, ie, writing, erasing and reading, will be specifically described. First, the write operation will be described. When the source region is connected to ground, 5 V is applied to the drain region, and 12 V is applied to the control gate electrode, a high electric field flows from the source region to the drain region, and the silicon surface near the drain region. Generate electrons that can cross the energy barrier to the insulating film. In the structure of the present invention, since the source region is formed in a region relatively higher than the drain region, the high field electrons are directed to the insulating film near the drain region at a constant angle. Therefore, the electrons are easily attracted by the electric field of the control gate electrode, and the writing performance is improved.

The erase operation can be carried out in the same manner as in the conventional case, and when an erase voltage is applied, an electric field is emitted from the floating gate electrode to the source region side. Since the insulating film near the source region is thinned to about 10 nm,
The erasing speed can be increased. The extraction amount of the electrons is adjusted to an appropriate value by the control circuit, and the threshold value of the cell is determined.

During a read operation, a read operation can be performed by applying a voltage of 5 V to the drain region and the control gate electrode and checking the presence / absence of a current flowing from the drain region. At that time, most of the gate insulating film is covered with the thick gate insulating film, and the thinned erasing insulating film near the source region is formed at an angle at which F-N tunneling does not easily occur. Also, erroneous erasure can be prevented even by applying a voltage to the drain region for a long time by reading.

Even in a device in which the floating gate electrode extends over the drain region through the insulating film, the control gate electrode does not exist over the drain region, so erroneous erasing does not pose a problem. However, in that case, the condition is that the insulating film is formed thicker than the gate insulating film. Embodiment 2 FIG. 26 is a schematic sectional view of a flash memory of the present invention. In this flash memory, the surface area of the upper part of the floating gate electrode on the drain region side is made larger than the surface area of the upper part on the source region side in order to efficiently take in hot carriers generated in the vicinity of the drain region into the floating gate electrode.

This flash memory was manufactured in the same manner as in Example 1 except that it was manufactured as follows. That is, a floating gate electrode is formed and an oxide film is formed thereon. Next, a resist pattern having an opening is formed on the floating gate electrode on the drain region side, and reactive ion etching is performed using this pattern as a mask to remove the oxide film in the opening. Next, after depositing polysilicon on the entire surface, etching back is performed by anisotropic etching to remove the polysilicon deposited other than the sidewall portion of the opening of the oxide film. Further, by removing the oxide film, a floating gate electrode having a protrusion is formed. Example 3 FIG. 27 shows an example in which element isolation by one element isolation oxide film is replaced by element isolation by the gate electrode 51. The third gate insulating film was formed so that the drain region side was thin and the source region side was thick. In this flash memory, the pulling efficiency by the control gate electrode could be improved.

In FIG. 28, element isolation is realized by the gate 53. In the manufacturing process of this device, after removing the LOCOS oxide film, the floating gate electrode and the element isolation gate are formed in the same process, and the source region and the drain region are formed by using the floating gate electrode and the element isolation gate as a mask. With such a configuration, conduction between adjacent source regions can be flexibly realized by the element isolation gate 53. The element isolation gate may be realized by the floating gate electrode and the control gate electrode. Thereby, the degree of element isolation can be set by changing the amount of charges accumulated in the floating gate electrode in advance.

Example 4 FIG. 29 is similar to that of FIG. 29 in that instead of changing the film thickness of the first and second gate insulating films, phosphorus, which is an impurity, is selectively injected to form insulating films having different dielectric constants. This is an example in which an effect is produced. In this embodiment, the first gate insulating film 65 has a dielectric constant of 3.9, and the second gate insulating film 66 has a dielectric constant of 3.5.

Embodiment 5 Furthermore, as shown in FIG. 30, the element of FIG. 1 can be formed in the well 45. The conductivity type of this well may be either the same conductivity type as the substrate or the opposite conductivity type. Example 6 Further, as shown in FIG. 31, the device of FIG.
(For example, the impurity is phosphorus and the dose is 1 × 10 ¹² to 1 ×.
10 ¹³ / cm ² ) and the P well 47 (for example, boron as an impurity and a dose amount of 1 × 10 ¹³ to 1 × 10 ¹⁴ / cm ² ) can be formed in a double well. By doing so, the potential of each well can be controlled independently, and the voltage of the control gate electrode can be lowered by applying a negative bias to the P well.

Embodiment 7 As shown in FIG. 32, the flash memories of the present invention can be arranged in a matrix. 32 is NO
It is an R type memory cell array. Reference numeral 84 in the drawing denotes a storage site in which the flash memory of the present invention is arranged. Reference numeral 85 is a row address line, and a row address decoder 86
Is a signal line wired from. A column address line 87 is a signal line wired from the column address decoder 88. Reference numeral 89 is an erase line, which is a signal line wired from the source decoder 90.

Embodiment 8 The present invention will be further described with reference to FIG. First, at the time of writing, the threshold voltage of the cell 1-a, which has already been programmed, is 5V (the impact ionized hot electrons are injected into the floating gate electrode, so that the threshold value of the cell is increased from 1V to 5V. Means that the word line WL1 is 0 V (not selected),
It is assumed that 12V (selection) is applied to WL2 for writing to the cell 1-b and 6V is supplied to BLa.

At this time, between the drain of the cell 1-a and the floating gate electrode, the sum of 6V applied to BLa and the voltage of the electric charge for increasing the threshold value stored in the floating gate electrode from 1V to 5V (for example, 6 + 4V) will be applied. That is, the already written cell 1-a
Means that, when writing to 1-b, a voltage close to 10 V (actually, slightly reduced due to the relationship of each capacitance) is applied between the drain and the floating gate electrode.

In the flash memory of the present invention in which the drain is the bit line, some cells receive a voltage close to 10 V, which is the same number of times as the number of cells connected to the bit line, between the drain and the floating gate electrode. On the other hand, each of these cells receives a voltage of 13 V during erasing, and the charges are erased. Comparing the voltage applied between the drain and the floating gate electrode at the time of writing in the cell 1-a with the voltage applied between the source and the floating gate electrode at the time of erasing, it is hard to say that there is a very large difference. This causes a problem that the stored contents of the cell are lost when writing to another cell commonly connected to the drain. However, since the mechanism of charge erasing of the device of the present invention uses Fowler-Nordheim tunneling, if the barrier height (voltage difference) cannot be increased, the tunnel distance (gate insulating film thickness) is increased. do it.

That is, in order to prevent erasing easily during erasing and prevent erroneous erasing during writing, cells are formed so that the gate insulating film on the drain side is thick and the source side is thin, and the mirror image is based on the drain. They may be arranged symmetrically and connected to form a memory cell matrix. Embodiment 9 The present invention can be applied to a thin film transistor as shown in FIG.

That is, an inclined portion is formed on the P-type silicon substrate 1 having an impurity concentration of about 10 ¹⁵ / cm ³ , and SiO ₂ (insulating film) 48 of about 5000 Å is grown. Next, amorphous silicon 49 of about 400 Å is formed, and the arsenic impurity concentration of the source / drain regions (10, 11) is 10 ²¹ / c.
m ³ and the boron impurity concentration in the channel region is 4 × 10
Ions are implanted so that the dose is about ¹⁶ / cm ³ .

The gate insulating film is formed by vapor phase epitaxy to 200Å
Approximately 2000 liters of polysilicon floating gate electrode 7 was formed so that the phosphorus impurity concentration was approximately 10 ²⁰ to 10 ²¹ / cm ³ . Next, an interlayer insulating film having a thickness of about 150 Å is formed, and a polysilicon control gate electrode 9 having a thickness of about 3,000 Å is formed to form a thin film transistor as shown in FIG.

It is desirable that the phosphorus impurity concentration of the control gate electrode 9 is higher than that of the floating gate electrode 7 for speeding up. By applying the structure of the present invention to a thin film transistor, the parasitic capacitance of the bit line can be reduced and the junction leakage current can be reduced. Example 10 FIG. 41 is a sectional view of a nonvolatile memory cell according to an example of the present invention. 301 is a P-type semiconductor substrate, 302 is a field dope layer, and 303 is an element isolation oxide film (LOC).
OS). 304 is a channel region, 305 is a gate insulating film, 306 is a first polysilicon layer (floating gate electrode), 307 is an interlayer insulating film, 308 is a second polysilicon layer (control gate electrode), and 309 is a source region ( N + type impurity regions) and 310 are drain regions (N + impurity regions).

The manufacturing method of the present invention will be described with reference to FIG. First, a buffer oxide film 312 of 1000 Å was grown on a P-type silicon substrate 311 whose surface oxygen concentration and crystal defects were sufficiently reduced by gettering or the like. Then, 1000 Å of silicon nitride film 313 to be an oxidation prevention film was deposited. Next, a photoresist pattern 314 was formed on the silicon nitride film 313 so as to isolate the element region into islands, and only the region where the element isolation oxide film was formed was opened.
Using this pattern as a mask, the silicon nitride film 31 is formed.
A pattern of 3 was formed (see FIG. 42 (a)).

Next, after removing the resist pattern 314 by etching, SOG is applied to the entire surface to form a sidewall spacer (not shown) for limiting ion implantation passage on the sidewall of the pattern made of the silicon nitride film 313. Formed. Next, boron implantation energy for channel stopper formation is 40 Kev, implantation amount is 5 ×.
Implantation was performed under the condition of 10 ¹³ / cm ² to form a field dope layer.

Next, the substrate 31 is subjected to wet oxidation at 1000 ° C.
A silicon oxide film was grown on the exposed surface of No. 1 to form an element isolation oxide film 315. At this time, the boron atoms in the field dope layer were activated and redistributed to form an inversion prevention layer 316 under the element isolation oxide film 315 (FIG. 42).
(C)). Next, after forming a resist pattern, anisotropic etching is performed using the resist pattern 317 and the silicon nitride film 313 as a mask to form the element isolation oxide film 31.
A part of No. 5 was removed (see FIG. 43 (a)).

Next, isotropic etching is performed to remove a predetermined amount of the bird's beak oxide film under the silicon nitride film 313 (determine the position of the end of the predetermined floating gate electrode on the drain region side).
It was etched (see FIG. 43 (b)). Further, after removing the silicon nitride film 313 by etching, plasma is formed on the entire surface.
A CVD nitride film was deposited at 5000Å. Furthermore, the element isolation region 31
5 and the element isolation region opening 318 were covered with a photoresist to remove the buffer oxide film and the plasma CVD nitride film on the oxide film at the end of the bird's beak (see FIG. 43 (c)).

In this state, the dose of boron (5 × 10 ¹²
/ Cm ² ), with an implantation energy of 100 Kev, the oxide film 31 is formed on the substrate of the edge (bird's beak oxide film) of the element isolation oxide film
By performing ion implantation through No. 5, a concentration gradient was formed in the inclined channel region (see FIG. 44 (a)). Then, the edge portions of the buffer oxide film and the element isolation oxide film were removed. After that, the entire surface was thermally oxidized at 900 ° C. to form a gate oxide film 319. This gate oxide film was thinly formed on the source region side, and a thin oxide film in the Fowler-Nordheim tunnel region was formed (see FIG. 44 (b)).

Next, a polycrystalline silicon layer 320 is formed on the entire surface to a thickness of
After depositing 1500 Å and applying SOG321, as shown in FIG. 44 (c), only the polycrystalline silicon in the step portion was exposed, and the unnecessary polycrystalline silicon in the exposed portion was removed. The CVD oxide film 322 having good step coverage was deposited flatly by repeating the etch back at least once (FIG. 4).
5 (a)). Then, anisotropic etching was performed, and the time point when the surface of the polycrystalline silicon layer 320 was exposed was set as the etching end point. At this time, the CVD oxide film 323 remains on the polysilicon layer formed on the channel slope portion (see FIG. 45B). Next, the surface of the polycrystalline silicon 3 is exposed by anisotropic reactive etching with a large selection ratio between polysilicon such as hydrogen bromide and an oxide film.
20 was selectively etched to form a floating gate electrode 324 (see FIG. 45 (c)).

Next, using the floating gate electrode 324 and the CVD oxide film 322 as a mask, phosphorus was spin-implanted at a low concentration and low energy to form an N ⁻ diffusion layer 325 (FIG. 46).
(See (a)). Surfaces of the floating gate electrode 324 and the exposed portion of the substrate were oxidized to form an interlayer insulating film 326. After that, using the floating gate electrode 324 as a mask, a high concentration of A
Then, s was injected to form a source region and a drain region 327 (see FIG. 46B).

Next, a nitride film was formed on the entire surface, and the nitride film was isotropically and anisotropically etched to form a nitride film sidewall for preventing oxidation on the sidewall of the floating gate electrode. After forming an interlayer insulating film of 1000 liters or more on the upper surface of the floating gate through an oxidation process, the nitride film sidewall was removed. After that, etching treatment was performed until the thin oxide film on the side wall was sufficiently over-etched, and after performing pretreatment, a thin interlayer insulating film was accurately formed on the side surface of the floating gate electrode. If sacrificial oxidation is performed at this time, reliability is improved.

Next, polycrystalline silicon is deposited on the entire surface to form a control gate electrode 328 (word line) (FIG. 46).
(C)). Further, in order to reduce the sheet resistance of the polycrystalline silicon of the control gate electrode 328, arsenic of 40 Kev and a dose of 3 × 10 ¹⁵ / cm ^{2 are also} implanted into the control gate, and a refractory metal silicide is deposited on the control gate electrode 328. Formed. The composition ratio (M / Si) of the refractory metal and silicon in the silicide was set to about 1/3.

After the entire surface is oxidized, an interlayer insulating film is formed according to a general process, contact holes are opened and metallization is performed, and the film is protected by a passivation film to obtain a gradient having an ultrafine floating gate electrode according to the present invention. A nonvolatile memory device having a channel structure has been completed.

[0138]

According to the nonvolatile memory of the present invention, the semiconductor substrate of the first conductivity type and the surface layer of the main surface of the semiconductor substrate are formed at a constant interval, and at least one of the surfaces is partially formed. A source impurity diffusion region and a drain impurity diffusion region of the second conductivity type formed on a surface having a crystal plane orientation different from the main surface, and a channel region provided between the source impurity diffusion region and the drain impurity diffusion region. , A gate insulating film provided on the channel region, a floating gate electrode provided on the gate insulating film, and a control gate electrode provided via an interlayer insulating film so that at least a part of the floating gate electrode is laminated thereon. The channel region has an inclined portion that is in contact with the drain impurity diffusion region and has a crystal plane orientation different from the main surface of the semiconductor substrate. Since scan impurity diffusion region is characterized by being provided relatively above the drain impurity diffusion regions can take substantially channel length long. Therefore, there is an advantage that punch-through is less likely to occur than in the case of the same two-dimensional design rule.

Further, according to the present invention, the area is small,
It is possible to realize a nonvolatile memory which has a high writing and erasing speed and which can prevent erroneous erasure during reading. Also, because it is excellent in mass production and miniaturization, and has outstanding durability for frequent writing / erasing and reading, it can be used as an image processing memory that frequently executes simple calculations of large amounts of data, and as a magnetic memory. As a device that replaces memory, its industrial value is immense.

The method of manufacturing a non-volatile memory according to the present invention comprises a step of forming an element isolation insulating film in a predetermined region on one main surface of a semiconductor substrate of the first conductivity type, and a step of forming at least Fowler-Nordheim. Second in the area where the tunnel occurs
Forming a conductive type low concentration impurity diffusion region; forming a gate insulating film on the active region in which the low concentration impurity diffusion region is formed; and floating gate electrode floating with the low concentration impurity diffusion region. A step of forming the gate electrode and the control gate electrode so as to overlap with each other in an area determined according to a capacitance, a step of forming an interlayer insulating film on the floating gate electrode, and the floating gate electrode and at least a part thereof. Forming a control gate electrode patterned in a stacked form, and using the control gate electrode and the floating gate electrode as a mask, impurities of the second conductivity type are implanted at a high concentration into the active region to form a source region and a drain region. Since it includes a process, it is possible to form a highly accurate and thin insulating film with good reproducibility, and to manufacture a nonvolatile memory with high durability and reliability. That.

In the nonvolatile memory of the present invention in which the floating gate electrode exists in the inclined portion of the channel region, the floating gate electrode can be made into an extremely small structure without using photoetching, and the size of the memory cell can be greatly reduced. Yes, it is excellent in quantity production. According to the method for manufacturing a nonvolatile memory described above, it is possible to form a fine floating gate electrode with high accuracy with good reproducibility, and it is possible to manufacture a nonvolatile memory having high durability and reliability.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view of a nonvolatile memory of the present invention.

FIG. 2 is a schematic cross-sectional view of a nonvolatile memory of the present invention.

FIG. 3 is a diagram for explaining an electrically coupled state of the nonvolatile memory of the present invention.

FIG. 4 is a diagram for explaining an electrically coupled state of the nonvolatile memory of the present invention.

FIG. 5 is a diagram for explaining an electrically coupled state of the nonvolatile memory of the present invention.

FIG. 6 is a schematic cross-sectional view showing a part of the manufacturing process of the nonvolatile memory of the present invention.

FIG. 7 is a schematic cross-sectional view showing a part of the manufacturing process of the nonvolatile memory of the present invention.

FIG. 8 is a schematic cross-sectional view showing a part of the manufacturing process of the nonvolatile memory of the present invention.

FIG. 9 is a schematic cross-sectional view showing a part of the manufacturing process of the nonvolatile memory of the present invention.

FIG. 10 is a schematic cross-sectional view showing a part of the manufacturing process of the nonvolatile memory of the present invention.

FIG. 11 is a schematic cross-sectional view showing a part of the manufacturing process of the nonvolatile memory of the present invention.

FIG. 12 is a schematic cross-sectional view showing a part of the manufacturing process of the nonvolatile memory of the present invention.

FIG. 13 is a schematic cross-sectional view showing a part of the manufacturing process of the nonvolatile memory of the present invention.

FIG. 14 is a schematic cross-sectional view showing a part of the manufacturing process of the nonvolatile memory of the present invention.

FIG. 15 is a schematic cross-sectional view showing a part of the manufacturing process of the nonvolatile memory of the present invention.

FIG. 16 is a schematic cross-sectional view showing a part of the manufacturing process of the nonvolatile memory of the present invention.

FIG. 17 is a schematic cross-sectional view showing a part of the manufacturing process of the nonvolatile memory of the present invention.

FIG. 18 is a schematic cross-sectional view showing a part of the manufacturing process of the nonvolatile memory of the present invention.

FIG. 19 is a schematic cross-sectional view showing a part of the manufacturing process of the nonvolatile memory of the present invention.

FIG. 20 is a schematic cross-sectional view showing a part of the manufacturing process of the nonvolatile memory of the present invention.

FIG. 21 is a schematic cross-sectional view showing a part of the manufacturing process of the nonvolatile memory of the present invention.

FIG. 22 is a schematic cross-sectional view showing a part of the manufacturing process of the nonvolatile memory of the present invention.

FIG. 23 is a schematic cross-sectional view showing a part of the manufacturing process of the nonvolatile memory of the present invention.

24A is a schematic cross-sectional view of the nonvolatile memory of the present invention, and FIG. 24B is an enlarged view of a portion A of FIG.

FIG. 25 is a diagram further enlarging an inclined portion of the channel region of the nonvolatile memory of FIG. 24.

FIG. 26 is a schematic cross-sectional view of the nonvolatile memory of the present invention.

FIG. 27 is a schematic cross-sectional view of the nonvolatile memory of the present invention.

FIG. 28 is a schematic cross-sectional view of the nonvolatile memory of the present invention.

FIG. 29 is a schematic cross-sectional view of the nonvolatile memory of the present invention.

FIG. 30 is a schematic cross-sectional view of the nonvolatile memory of the present invention.

FIG. 31 is a schematic cross-sectional view of the nonvolatile memory of the present invention.

FIG. 32 is a wiring diagram when the nonvolatile memories of the present invention are arranged in a matrix.

FIG. 33 is a wiring diagram when the nonvolatile memories of the present invention are arranged in a matrix.

FIG. 34 is a schematic cross-sectional view of a conventional nonvolatile memory.

FIG. 35 is a schematic cross-sectional view of a conventional nonvolatile memory.

FIG. 36 is a schematic cross-sectional view of a conventional nonvolatile memory.

FIG. 37 is a schematic view of a hot electron injection mechanism of the nonvolatile memory of the present invention.

FIG. 38 is a schematic view of a hot electron injection mechanism of the nonvolatile memory of the present invention.

39 is a plan view of the non-volatile memory of FIG. 1. FIG.

FIG. 40 is a schematic cross-sectional view of the nonvolatile memory of the present invention.

FIG. 41 is a schematic cross-sectional view of the nonvolatile memory of the present invention.

FIG. 42 is a schematic cross-sectional view showing a part of the manufacturing process of the nonvolatile memory of the present invention.

FIG. 43 is a schematic cross-sectional view showing a part of the manufacturing process of the nonvolatile memory of the present invention.

FIG. 44 is a schematic cross-sectional view showing a part of the manufacturing process of the nonvolatile memory of the present invention.

FIG. 45 is a schematic cross-sectional view showing a part of the manufacturing process of the nonvolatile memory of the present invention.

FIG. 46 is a schematic cross-sectional view showing a part of the manufacturing process of the nonvolatile memory of the present invention.

[Explanation of symbols]

1, 301, 311 P-type semiconductor substrate 2, 302 Field dope layer 3, 29, 302, 315 Device isolation oxide film (LOCO
S) 4,104 channel region 5,65 first gate insulating film 6,66 second gate insulating film 7,306,324 first polysilicon layer (floating gate electrode) 8 third gate insulating film 9,308, 328 Second polysilicon layer (control gate electrode) 10, 309 Source region (N ⁺ type impurity diffusion region) 11, 310 Drain region (N ⁺ impurity diffusion region) 12 LDD region 13 Sacrificial oxide film 14, 23, 26, 314, 317 photoresist pattern 15 Fowler-Nordheim tunnel region 16 control gate line 17 floating gate electrode and channel region 22, 312 buffer oxide film 24 channel dope layer 27 side wall spacer 28, 303 field dope layer 30, 316 inversion prevention layer 43 326 Interlayer insulation film 44 Metallization 45 well 46 N well 47 P well 48 Oxide film 49 Amorphous silicon 51 Gate electrode 53 Gate 84 Storage site 85 Row address line 86 Row address decoder 87 Column address line 88 Column address decoder 89 Erase line 90 Source decoder 214 Resist Patterns 215, 321 SOG film 313 Silicon nitride film 318 Element isolation region opening 319 Gate oxide film 320 Polycrystalline silicon 322, 323 CVD oxide film 325 N ^- diffusion layer 327 Source region and drain region

Claims (9)

[Claims] 1. A crystal plane formed between a semiconductor substrate of the first conductivity type and a surface layer of a main surface of the semiconductor substrate at a constant interval, and at least one of surfaces of which is partially different from the main surface. A second conductivity type source impurity diffusion region and a drain impurity diffusion region formed on a surface having an orientation, a channel region provided between the source impurity diffusion region and the drain impurity diffusion region, and a channel region provided on the channel region. A gate insulating film, a floating gate electrode provided on the gate insulating film, and a control gate electrode provided via an interlayer insulating film so that at least a part of the floating gate electrode is laminated on the floating gate electrode, and the channel region is The drain impurity diffusion region is in contact with the drain impurity diffusion region, and the source impurity diffusion region is a drain region. A nonvolatile memory, which is provided relatively above an impurity diffusion region. 2. The nonvolatile memory according to claim 1, wherein the source impurity diffusion region has a higher junction breakdown voltage than the drain impurity diffusion region. 3. A plurality of memories are arranged, and two memories adjacent to each other share a drain region of each other,
The nonvolatile memory according to claim 1, which has a mirror image symmetry relationship with the drain region as a base point. 4. The non-volatile memory according to claim 1, wherein the control gate electrode is provided on the side wall of the floating gate electrode via an interlayer insulating film so that at least a part thereof is capacitively coupled. 5. A first insulating film formed on a semiconductor substrate of the first or second conductivity type, a semiconductor thin film formed on the first insulating film, and a surface of a main surface of the semiconductor thin film. A channel region provided between the source impurity diffusion region and the drain impurity diffusion region of the first or second conductivity type formed at a constant interval in the layer, and a gate insulating film provided on the channel region, A floating gate electrode provided on the gate insulating film, a control gate electrode provided via an interlayer insulating film so that at least a part of the floating gate electrode is laminated on the floating gate electrode, and the channel region has an inclined portion, A thin film transistor, wherein the source impurity diffusion region is provided relatively above or below the drain impurity diffusion region. 6. A step of forming an element isolation insulating film in a predetermined region of one main surface of a semiconductor substrate of the first conductivity type, and a second conductivity type low-resistance film in at least a region where the Fowler-Nordheim tunnel occurs in the active region. A step of forming a high concentration impurity diffusion region; a step of forming a gate insulating film on the active region in which the low concentration impurity diffusion region is formed; and a floating gate electrode controlling the low concentration impurity diffusion region and the floating gate electrode. A step of forming so as to overlap with an area determined according to a capacitance with the gate electrode, a step of forming an interlayer insulating film on the floating gate electrode, and a step of laminating at least a part of the floating gate electrode. Forming a patterned control gate electrode, and implanting a high concentration of a second conductivity type impurity into the active region using the control gate electrode and the floating gate electrode as a mask to form a source region And a step of forming a drain region, a method for manufacturing a non-volatile memory. 7. An element isolation oxide film is formed by an oxidation treatment so as to extend over a part of the element isolation region and the active region, and the element isolation oxide film on the active region is removed. 7. A hot electron is generated at a portion where a region where the crystal is disturbed by the edge stress generated in 1) and the end of the drain impurity diffusion region on the channel region side are in contact with each other, and the hot electron is injected into the floating gate electrode. 6. The manufacturing method of 6. 8. A step of forming an element isolation oxide film on a predetermined region of one main surface of a semiconductor substrate of the first conductivity type, and an oxide film formation at the time of forming the element isolation oxide film on the predetermined region of the element isolation oxide film. A step of etching and removing the blocking film and the photoresist to form an opening in the element isolation oxide film; a step of removing the oxide film formation blocking film and the photoresist; and a step of forming the element isolation oxide film in the opening. Is a step of forming a second oxide film having a different etching rate, a step of etching away a thin region of the element isolation oxide film to expose a part of the semiconductor substrate to be an active region, and a gate on the exposed region. A step of forming an insulating film, a step of forming a floating gate electrode on the gate insulating film, a step of forming a planarizing film on the entire surface so that the surface is flat at least on the active region, and the planarizing film. Tilt Etching under the condition that the flattening film remains on the floating gate electrode on the region and the surface of the floating gate electrode other than on the inclined region is exposed, and the flattening film left on the floating gate electrode on the inclined region And a step of etching the floating gate electrode by using the mask as a mask. 9. A step of covering at least a part of the first electrode with an insulating film and forming a first interlayer film in a region other than the region covered with the insulating film, the insulating film is removed, and the insulating film is removed. A second interlayer film that is thinner than the first interlayer film in a region where the first interlayer film is formed, and at least the second interlayer film is formed on the first electrode through the first interlayer film and the second interlayer film. And a step of forming a second electrode so as to cover the non-volatile memory.