JPH0822411A - Image memory initializing device - Google Patents

Abstract

PURPOSE:To provide the image memory initializing device which can perform initialization without loading a CPU. CONSTITUTION:The device is equipped with an image processing part 2 which processes image data stored in an image memory 6 as specified according to an indication from a CPU and outputs the processed data, and an input DMA control part 3 and an output DMA control part 4 which read the image data out of the image memory 6, send the data to the image processing part 2, and writes the processed data in the image memory 6. Then the input DMA control part 3 and output DMA control part 4 writes initialization data 6a, stored in a specific storage area in advance, in an initialization area in the image memory 6 according to an initialization indication from the CPU.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image memory initialization device for initializing an image memory from an image processing device via a data bus based on an instruction from a CPU.

[0002]

2. Description of the Related Art When image data read from an original is displayed on a display device via an image processing device or recorded by a printer device, it is stored in an image memory capable of storing at least one screen of image data. The image data is temporarily stored, processed by the image processing device, and then transferred to the display device or the printer device.

In this image processing apparatus, an initialization process for temporarily clearing the image memory is performed before the processing of one screen is completed and the processing of the next screen is started. In order to clear the image memory, it is common for the CPU to write predetermined clear data (for example, "0" or "F") in the necessary area of the image memory, but this causes a large load on the CPU. Will be given.

Conventionally, in clearing the image memory, the CPU
JP-A-2-84357 and JP-A-3-105438 are disclosed from the viewpoint of reducing the load of
When clearing the image memory, the image processing device reads the image data from the image memory and then writes the clear data. This eliminates the need for a memory clear dedicated access cycle especially in the CPU.

[0005]

However, in clearing these image memories, when the necessary area of the image memory needs to be cleared after the start-up processing at the time of power-on is completed, the CPU saves the area. A corresponding amount of clear data must be read and accessed. During this time, the CPU is devoted to read access to the image memory and cannot perform other processing. Also,
Even when the size of the image data to be handled becomes larger than the size of the immediately preceding image data, it is necessary for the CPU to read and access the clear data for the portion exceeding the storage area of the immediately preceding image data to clear the contents. In particular, when the resolution of image data to be handled is increased and the number of gradations is increased to increase the capacity of the image memory, such a method cannot sufficiently reduce the load on the CPU, resulting in a delay in processing speed.

[0006]

SUMMARY OF THE INVENTION The present invention is an image memory initialization device which has been made to solve such problems. That is, the image memory initialization device of the present invention is
An image processing unit that performs a predetermined process on the image data stored in the image memory based on an instruction from U and outputs the processed data, and an image processing unit that reads the image data from the image memory and sends the image data to the image processing unit. A direct memory access control means for writing data to the image memory, and the direct memory access control means stores initialization data stored in a predetermined storage area in advance in the image memory based on an initialization instruction from the CPU. The writing process is performed in the initialization area of the.

[0007]

According to the present invention, when the image memory is initialized, the direct memory access control means sets the address of the predetermined storage area in which the initialization data is written from the CPU,
An initialization instruction including a size to be initialized and a write address in the image memory to be initialized is given. The direct memory access control means reads a predetermined amount of initialization data according to the initialization instruction from the CPU by an amount corresponding to the initialization size, and writes the read amount of the initialization data sequentially from the write start address in the image memory. Perform processing. That is, the CPU only gives the initialization instruction, the predetermined address and the size to the direct memory access control section, and the actual initialization processing is performed by the direct memory access control means.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an image memory initialization device of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram illustrating an image memory initialization device of the present invention, FIG. 2 is an internal configuration diagram of an input DMA, and FIG. 3 is a flowchart illustrating an image memory initialization method. The DMA here indicates direct memory access.

The image memory initialization device in this embodiment is configured as an image processing device 1 as shown in FIG.
The image memory 6 connected to the image processing apparatus 1 via the data bus 5 and capable of storing image data for at least one screen is initialized. The image processing apparatus 1 internally includes an image processing unit 2, an input DMA control unit 3 that performs a process of reading a predetermined amount of initialization data 6 a and sending the initialization data 6 a to the image processing unit 2, and a predetermined amount of initial data via the image processing unit 2. The output DMA control unit 4 is provided for performing processing for writing the encoded data 6a into the image memory 6.

Normally, the image processing apparatus 1 reads the image data from the image memory 6 in which the image data of an original or the like is stored via the data bus 5, and the image processing unit 2 performs a predetermined image processing. After that, the processed data is written in the image memory 6 again via the data bus 5. When accessing image data, a CPU (not shown) uses an input DMA
The control unit 3 is provided with a read start address ASS and a size parameter indicating the size of data to be fetched. The size parameter is composed of, for example, the number N of pixels in one line and the number L of lines included in one screen.

The read end address ASE is easily determined from the read start address ASS and the size parameter. The input DMA control unit 3 sequentially increments the internal address counter to the read end address ASE based on the read start address ASS given from the CPU, and the image data stored at each address is transferred to the data bus 5. It is taken in through the image processing apparatus 1 side via.

Further, the output DMA control unit 4 is provided with a write start address ADS from the CPU which indicates from which address in the image memory 6 the processed data subjected to the image processing by the image processing unit 2 is to be written. The output DMA control unit 4 determines the write start address ADS given by the CPU.
Based on the above, the internal address counter is sequentially incremented, and the processed data is written to each address in the image memory 6.

If the image processing is to output the sequential processing result like the compression encoding of the image data, the output DM
The address counter in the A control unit 4 sequentially increments the address from the write start address ADS and writes the processed data, but the image processing performs coordinate conversion like image rotation to calculate the output destination address. If it is accompanied, the write start address ADS is given to the image processing unit 2. In this case, it is not necessary to provide the output DMA controller 4 with an address counter.

Next, an image memory initialization method using such an image memory initialization device will be described with reference to FIG. In the following description, reference numerals not shown in FIG. 3 refer to FIG. First, prior to the initialization of the image memory 6, the CPU writes the initialization data 6a at an arbitrary address AMC of the image memory 6 (step S
1). The initialization data 6a may be, for example, "0" or "F" for clearing the image memory 6, or may be data for forming a background with a predetermined pattern or character string, and the size thereof is large. It only has to be 1 to several bytes. The initialization data 6a can be written in any address of the image memory 6, but it is particularly desirable to write it in the top address or the bottom address.

Next, the CPU gives an instruction to the input DMA control section 3 to set the read start address ASS to the address AMC in which the initialization data is written (step S).
2) Further, the output DMA control unit 4 is instructed to set the write start address ADS to the start address of the area to be initialized (step S3). The CPU also gives the size parameter MSIZE of the area to be initialized on the image memory 6 to the input DMA controller 3 (step S4).

The CPU sets the memory initialization mode signal CMOD to "H (high level)" for the input DMA control unit 3 after performing each of the steps S1 to S4.
The initialization mode is designated (step S5), and then the image processing unit 2 is activated (step S6). C
The PU does not need to be involved in the initialization process after each designation and activation of the image processing unit 2, and is released.

The memory initialization mode signal CMOD is "H".
As a result, the input DMA control unit 3 reads data from the pre-specified read start address CSS, that is, the address AMC in which the initialization data 6a in the image memory 6 is stored, and the initialization data 6a is transferred to the data bus 5 A process of importing the image data into the image processing apparatus 1 side via the
7). Then, the internal address counter is incremented to count the read data amount (step S8), and a predetermined image processing is performed (step S9).

Then, the initialization data 6a output from the image processing unit 2 is sequentially written from the write start address ADS designated in advance via the output DMA control unit 4, that is, the head address of the area to be initialized in the image memory 6. Go out (step S10). The input DMA control unit 3 repeats the read processing of the initialization data 6a until the read data amount reaches the size parameter MSIZE designated in advance (step S11). As a result, the initialization data 6a is sequentially written in the image memory 6, and the CP
A predetermined area counted from the write start address ADS designated by U is initialized.

The input DMA controller 3 counts the read data amount by using the address counter 31 as shown in FIG. That is, the address counter 31
Is a one-shot pulse signal RSTT indicating the start of reading image data for one screen (for example, one page) is loaded into the counter at the read start address VSS, and the read clock is read when the memory initialization mode signal CMOD is at a low level. It is a counter circuit that performs an increment operation by RDCK.

Enable terminal E of the address counter 31
NB is a terminal for controlling the count operation, and the memory initialization mode signal CMOD is connected to this terminal.
The count operation is performed by inputting a low level signal to the enable terminal ENB, and the count operation is prohibited by inputting a high level signal. That is, in normal image data reading, the memory initialization mode signal C
The MOD is at a low level, the count operation is performed, and the read address RADD output from the address counter 31 is sequentially incremented from the read start address AS S.

Further, the address counter 31 is provided with a read data amount counter 32 and a comparison circuit 33 for determining whether or not a required amount of image data has been fetched. The read data amount counter 32 is cleared at the start of reading one screen of image data, and then counts the data amount corresponding to one read by the read clock RDCK.

The output from the read data amount counter 32 is compared with the total data amount MSIZE converted by the size parameter by the comparison circuit 33, and the read end signal REND is asserted when the two match. . Upon initialization, when the memory initialization mode signal CMOD becomes high level, the count operation by the address counter 31 is prohibited, and the read address RADD as its output remains fixed at the read start address AS S. As a result, at the time of the memory initialization operation, the image processing apparatus 1 causes the image memory 6 to receive the address A
The initialization data 6a can be continuously read from SS, that is, the address AMC, until the total data amount MSIZE matches.

In the image memory initialization device, the address counter of the input DMA control unit 3 described above repeatedly performs steps S7 to S11 shown in FIG.
Initialize a predetermined area inside. Then, the initialization data 6a
The read end signal REND is asserted at the stage where the read data amount of MSIZE matches the read data amount (step S1).
2) The initialization process ends.

When the next initialization process is performed, steps S1 to S12 are sequentially performed again. In addition,
As described above, the initialization data 6a may be written in each initialization process because it is a small value of 1 to several bytes. However, for example, when the electronic device including the image processing apparatus 1 is powered on. The startup process may be performed only once, and in this case, steps S2 to S12 are repeated in the initialization process. by this,
Further, the load on the CPU can be reduced.

In the image memory initialization device according to the embodiment described above, the image processing unit 2 performs rotation processing, resolution conversion,
Alternatively, it is suitable when performing mapping such as enlargement or reduction to the same space as the input image data, and after the initialization data 6a is fetched from the input DMA control unit 3 to the image processing unit 2 and processed, the final image is obtained. The image data on the memory 6 is written in the initialization data 6a. On the other hand, in the case where the image processing unit 2 converts the input data into a predetermined code by a compression process, a decompression process, or the like and performs mapping to a space different from the input image data, the input DMA control unit 3 The result of processing the image data taken in from the image processing unit 2 is not always the desired initialization data 6a.

Therefore, another example that can be applied to an image processing apparatus that maps input image data to different spaces will be described with reference to the block diagram of FIG. That is, in the image processing device 1 ′ of the image memory initialization device shown in FIG. 4, in addition to the input DMA control unit 3 and the output DMA control unit 4, an image processing unit 2 ′ that maps input image data to a space different from that. And a selector 21 are provided.

The selector 21 selects the image data processed by the image processing section 2'or the image data fetched from the input DMA control section 3 based on the memory initialization mode signal CMOD and outputs it to the output DMA control section 4. Is.
That is, when the memory initialization mode signal CMOD is set to the high level and the initialization operation is designated, the initialization data 6a is continuously read from the input DMA control unit 3 as described above. At this time, the input D is selected by the selector 21.
The initialization data 6a read from the MA control unit 3 is directly sent to the output DMA control unit 4.

The initialization data 6a read from the input DMA control unit 3 is fetched until it becomes equal to the total data amount MSIZE, and sent to the output DMA control unit 4 via the selector 21. As a result, even when the image processing unit 2 ′ performs a process of mapping the input image data to a different space, the initialization data 6a is sent to the output DMA control unit 4 as it is, and the predetermined area in the image memory 6 is sent. Will be able to be initialized.

Further, in this embodiment, the initialization data 6
Although the example in which a is written in a part of the image memory 6 has been shown, the present invention is not limited to this, and the initialization data 6a can be stored in a register (not shown) provided inside the image processing apparatus 1, for example.
May be written. As a result, the initialization data 6a can be directly taken into the image processing apparatus 1 without the intervention of the input DMA controller 3 during the initialization operation, and the initialization process can be speeded up. Further, in any of the embodiments, the circuit scale required to be added for the initialization operation can be reduced, so that the CPU can be downsized.

[0030]

As described above, the image memory initialization device of the present invention has the following effects. That is, the CPU only has to give a predetermined instruction to initialize the image memory, and no load is applied during the initialization operation. Therefore, it is possible to perform other processing during the initialization operation, and it is possible to speed up the image processing.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating an image memory initialization device of the present invention.

FIG. 2 is a configuration diagram of an address counter of an input DMA control unit.

FIG. 3 is a flowchart illustrating an image memory initialization method.

FIG. 4 is a block diagram illustrating another embodiment.

[Explanation of symbols]

 1 Image Processing Device 2 Image Processing Unit 3 Input DMA Control Unit 4 Output DMA Control Unit 5 Data Bus 6 Image Memory 6a Initialization Data

Claims (1)

[Claims] 1. An image processing unit that performs a predetermined process on image data stored in an image memory based on an instruction from a CPU and outputs the processed data, and the image data is read from the image memory to output the image. An image memory initialization device comprising a direct memory access control means for sending the processed data to the image memory and transmitting the processed data to the image memory, wherein the direct memory access control means is the CPU.
An image memory initialization apparatus, which performs a process of writing initialization data stored in a predetermined storage area in advance to an initialization area in the image memory based on an initialization instruction from the.