JPH08223006A - Method and device for adjusting delay time - Google Patents

Abstract

PURPOSE: To provide a delay time adjustment method/device which can easily adjust the delay time to a desired signal propagation delay time. CONSTITUTION: This adjustment method/device is provided with a variable delay circuit 16 which is placed between the 1st and 2nd positions of a signal propagation path, a reference signal source 11 which supplies a repetitive reference pulse signal of a cycle equal to the desired signal propagation delay time to the 1st position, the timing coincidence detection circuits 20 and 22 which detect the coincidence of the signal state transition timing between the 1st and 2nd positions, and the adjustment means 24 and 26 which monitor the outputs of both circuits 20 and 22 and control the circuit 16 to secure the coincidence of the signal state transition timing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay time adjusting method and a delay time adjusting apparatus capable of adjusting a signal propagation delay time of a circuit to a desired value.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing an example of a conventional delay adjusting method. The signal source 10 repeatedly generates a pulse signal, and the output pulse signal is supplied to the first logic circuit 12 and also to the second logic circuit 14 via the variable delay circuit 16. In this case, it may be necessary for the delay time between the signals supplied to the first logic circuit 12 and the second logic circuit 14 to fall within a predetermined range. Therefore, the oscilloscope 18 is connected to the signal input end of the first logic circuit 12 and the second logic circuit 12.
The signal input terminal of the logic circuit 14 is connected via a probe. The first channel CH1 of the oscilloscope 18 measures the signal at the signal input end of the first logic circuit 12, and the second channel CH2 measures the signal at the signal input end of the second logic circuit 14. By observing this measurement result on the screen and adjusting the variable delay circuit 16, the signal propagation delay time between the first and second logic circuits can be adjusted to a desired value.

[0003]

However, for example, when the desired delay time is in the range of 50 ns ± 1 ns,
The time display scale of the oscilloscope 18 is, for example, 1 ns.
/ Accurate adjustment cannot be performed without adjusting below the scale. However, since the rising time of the signal of channel 1 and the rising time of the signal of channel 2 are separated by 50 ns,
If the scale of the time axis display of the screen is set to about 1 ns / scale, only the time range of about 10 ns can be displayed on the screen, and it is impossible to display the rising edges of the two waveforms at the same time.

An object of the present invention is to provide a delay adjusting method and a delay adjusting device which can easily adjust a desired signal propagation delay time.

[0005]

The delay adjusting method of the present invention is
A method for adjusting a propagation delay time of a signal from a first position to a second position of a signal propagation path, wherein a variable delay circuit is provided between the first position and the second position, and a desired delay time is provided at the first position. A repetitive reference pulse signal having a period equal to, and measuring the signal waveforms at the first and second positions based on the trigger event of the signal at the first position,
And the variable delay circuit is adjusted so that the edge portions of the two signal waveforms at the second position coincide with each other.

The delay adjusting device of the present invention comprises a variable delay circuit provided between a first position and a second position of a signal propagation path, and a repetition reference having a cycle equal to a desired signal propagation delay time at the first position. A reference signal source for supplying a pulse signal,
A timing coincidence detection circuit that detects coincidence of the timings of the state transitions of the signals at the first position and the second position, and the variable delay circuit that monitors the output of the timing coincidence detection circuit and makes the timings of the state transitions coincide. And adjusting means for adjusting.

[0007]

FIG. 1 is a block diagram showing the configuration of an embodiment of the delay adjusting method of the present invention. In the delay adjusting method of the present invention, the reference signal source 11 generates a repetitive reference signal having a cycle equal to the desired delay time and supplies the reference signal to the first logic circuit 12. This reference signal is supplied to the second logic circuit 14 via the variable delay circuit 16. Similar to the conventional example of FIG. 3, the oscilloscope 18 is connected to the signal input terminals of the first and second logic circuits 12 and 14 to observe the signals of the respective parts. The reference signal source 11 is a highly accurate signal source based on a crystal oscillator, and if the delay time is adjusted to be equal to the cycle Td of the output signal of the reference signal source 11, a desired signal propagation delay time can be obtained. . The oscilloscope 18 starts sweeping in response to the trigger event of the channel 1 signal and displays the channel 1 and channel 2 signals on the screen.
In this way, as shown in FIG. 1, the first edge of the second cycle of the waveform of channel 1 and the first edge of the waveform of channel 2
The first edge of the cycle is displayed at the time position where the edges almost coincide. After that, the variable delay circuit 16 is simply adjusted so that the edges of both waveforms completely match. In this way, the edges to be matched can be matched on the time axis of the screen, so even if the time axis display scale is set to 1 ns or less, for example, the problem of the prior art does not occur, and adjustment with high accuracy is possible. You can In the oscilloscope 18, it is desirable to use the so-called delayed sweep measurement mode in order to display the edge of the waveform to be matched at the center of the screen.

FIG. 2 is a block diagram showing the configuration of an embodiment of the delay adjusting apparatus according to the present invention. Elements corresponding to those in FIG. 1 have the same reference numerals. In this example,
Computer (CPU) 2 without using oscilloscope
4 automatically adjusts. The signal input terminal of the first logic circuit 12 is connected to the D input terminal of the D flip-flop 20,
The signal input terminal of the second logic circuit 14 is connected to the clock input terminal of the D flip-flop 20. The Q output terminal of the D flip-flop 20 is connected to the set terminal S of the latch 22, and the Q output terminal of the latch 22 is the CPU 2
4 is connected. Further, the CPU 24 uses the latch 22.
In this configuration, a reset signal is supplied to the reset terminal R of. Further, the CPU 24 supplies the delay control data to the DAC (digital / analog converter) 26, and supplies the delay control signal converted into the analog control voltage to the variable delay circuit 16. In this case, it is desirable that the variable delay circuit 16 is capable of adjusting the delay time with high resolution.
Although it is preferable to use the variable delay circuit disclosed in the publication of No. 38574, any conventional voltage-controlled variable delay circuit can be used as long as it meets the design specifications.

In FIG. 2, D flip-flop 20
The length of the signal path from the D input end to the connection point of the signal input end of the first logic circuit 12 is from the connection point of the signal input end of the second logic circuit 14 to the clock input end of the D flip-flop 20. It is approximately equal to the length of the signal path. That is, the D flip-flop 20 has two logic circuits 1
This is because it is detected that signal state transitions at the signal input terminals 2 and 14 occur simultaneously. That is, the D flip-flop outputs the logic 0 as the Q output when the transition of the logic state, that is, the edge is supplied to the clock input when the logic state of the D input is logic 0. On the other hand, D
When an edge of the signal is supplied to the clock input terminal when the logic state of the input terminal is logic 1, an output of logic 1 is generated at the Q output terminal. The output logic state of the D flip-flop 20 is stored in the latch 22, and the CPU 24 monitors it. In this way, the D flip-flop 20 and the latch 22 form a timing coincidence detection circuit. CP
U24 is the first if the output of latch 22 is a logic zero.
It is determined that the signal edge reaches the signal input terminal of the second logic circuit before the edge of the signal supplied to the signal input terminal of the logic circuit. Therefore, since the delay time of the variable delay circuit 16 is shorter than the desired value, the delay control data is adjusted and the latch 22
Adjust the delay time gradually while monitoring the logic state of. When the logic output of the latch 22 changes to logic 1, it corresponds to the detection of coincidence between two signal edges.

Contrary to the above, the CPU 24 has the latch 22.
When the logic 1 is first detected as the logic output of, the delay control data is adjusted to gradually decrease the delay time of the variable delay circuit 16. Then, when the logic output of the latch 22 changes to logic 0, the coincidence of the edges of both signal waveforms is detected. In this way, the reference signal source 11 supplies a repetitive reference signal having a cycle equal to the desired delay time to the signal input terminal of the logic circuit 12, and the reference signal is supplied to the second logic circuit 14 via the variable delay circuit 16. The signal is supplied to the signal input end, and the state transition time (edge) at the signal input end of these two logic circuits 12 and 14 is detected by the CPU 2.
It is possible to accurately and automatically set the delay time of the variable delay circuit to a desired value by automatically matching the delay time with 4.

The preferred embodiment of the present invention has been described above.
It will be apparent to those skilled in the art that the present invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the gist of the present invention.

[0012]

The variable delay circuit is provided between the signal input terminals of the two circuits, and the reference signal having the period equal to the desired delay time is supplied to the first signal input terminal, so that the delay time can be accurately measured. It became possible to adjust.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of another embodiment of the present invention.

FIG. 3 is a block diagram showing an example of a system configuration of a conventional delay time adjusting method.

[Explanation of symbols]

 11 Reference Signal Source 12 First Logic Circuit 14 Second Logic Circuit 16 Variable Delay Circuit 18 Oscilloscope 20 D Flip Flop 22 Latch 24 Computer (CPU) 26 Digital to Analog Converter (DAC)

Claims (2)

[Claims] 1. A method for adjusting a signal propagation delay time from a first position to a second position of a signal propagation path, wherein a variable delay circuit is provided between the first and second positions, The position is provided with a repeating reference pulse signal having a period equal to a desired delay time, the signal waveforms of the first and second positions are measured based on a trigger event of the signal of the first position, and the first and second positions are measured. A delay time adjusting method for a circuit, wherein the variable delay circuit is adjusted so that the edge portions of two signal waveforms at two positions coincide with each other. 2. A variable delay circuit provided between a first position and a second position of a signal propagation path, and a reference for supplying the first position with a repeating reference pulse signal having a cycle equal to a desired signal propagation delay time. A signal source, a timing coincidence detection circuit for detecting coincidence of the state transition timings of the signals at the first position and the second position, and an output of the timing coincidence detection circuit are monitored so that the state transition timings coincide. A delay time adjusting device comprising: an adjusting unit that adjusts the variable delay circuit.