JPH0821660B2 - Lead frame manufacturing method - Google Patents
Lead frame manufacturing methodInfo
- Publication number
- JPH0821660B2 JPH0821660B2 JP2126493A JP12649390A JPH0821660B2 JP H0821660 B2 JPH0821660 B2 JP H0821660B2 JP 2126493 A JP2126493 A JP 2126493A JP 12649390 A JP12649390 A JP 12649390A JP H0821660 B2 JPH0821660 B2 JP H0821660B2
- Authority
- JP
- Japan
- Prior art keywords
- element mounting
- semiconductor element
- tip
- lead frame
- heat treatment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7825—Means for applying energy, e.g. heating means
- H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/78301—Capillary
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8512—Aligning
- H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
- H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
- H01L2224/8518—Translational movements
- H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
Landscapes
- Perforating, Stamping-Out Or Severing By Means Other Than Cutting (AREA)
- Punching Or Piercing (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔発明の目的〕 （産業上の利用分野） 本発明は、リードフレームの製造方法に係り、特にそ
のインナーリード先端部の形状の改善に関する。DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Field of Industrial Application) The present invention relates to a method of manufacturing a lead frame, and more particularly to improvement of the shape of the inner lead tip.
（従来の技術） 半導体装置用リードフレームは、フォトエッチング法
またはプレス加工のいずれかの方法によって、金属帯状
材料の形状加工を行い形成される。(Prior Art) A lead frame for a semiconductor device is formed by shaping a metal strip-shaped material by either a photoetching method or a press working method.
最近のリードフレームでは、インナーリード先端部の
板厚よりもリードピッチが狭くなる傾向にあり、例え
ば、板厚0.15mmに対し、0.1〜0.12mmの幅で打ち抜きを
行わなければならないこともある。In recent lead frames, the lead pitch tends to be narrower than the thickness of the inner lead tip portion, and for example, punching may have to be performed with a width of 0.1 to 0.12 mm for a thickness of 0.15 mm.
このため、インナーリード先端が第３図に示すように
跳ね上がり、インナーリード先端と半導体チップのボン
ディングパッドとを電気的に接続するワイヤボンディン
グに際し、ボンディングマシンのキャピラリでインナー
リード先端をプレート上に押し付けながらワイヤの接続
を行わねばならなず、ボンディングミスが極めて発生し
易い状態となっていた。Therefore, the tip of the inner lead jumps up as shown in FIG. 3, and at the time of wire bonding for electrically connecting the tip of the inner lead and the bonding pad of the semiconductor chip, the tip of the inner lead is pressed against the plate by the capillary of the bonding machine. Since wires had to be connected, a bonding error was very likely to occur.
インナーリード先端の変形防止対策としては、ポリイ
ミドテープなどの絶縁性のテープを貼着することにより
インナーリード間を橋絡し、位置関係を保持するという
方法が提案されているが、インナーリードの先端は保持
できないため、十分な対策とはなっていないという問題
があった。As a measure to prevent deformation of the inner lead tips, a method has been proposed in which an insulating tape such as a polyimide tape is attached to bridge the inner leads to maintain the positional relationship. There is a problem that it is not a sufficient measure because it cannot be maintained.
そこで、インナーリード先端部の位置ずれを防ぐため
に、隣接するインナーリードの先端を連結する連結部を
残して形状加工を行い、インナーリード相互間の接続の
ためのテーピング工程、熱処理あるいは鍍金処理などの
処理工程を経た後、最後にこの連結部を除去する方法が
提案されている。Therefore, in order to prevent displacement of the inner lead tips, shape processing is performed by leaving the connecting portion that connects the tips of the adjacent inner leads, and taping process for connecting the inner leads to each other, heat treatment or plating treatment is performed. A method has been proposed in which the connection is finally removed after the treatment process.
この方法は通常次のような工程で行われる。 This method is usually performed in the following steps.
例えば、従来、まず、第４図（ａ）に示すように、第
１の順送り金型を用いて半導体素子搭載ステージ52とな
る領域に向かって収斂する複数の第１の打ち抜き部5Aを
形成し、インナーリード51の側面を形成すると共に、半
導体素子搭載ステージ52を支持するサポートバー53を形
成する。For example, conventionally, first, as shown in FIG. 4 (a), first, a plurality of first punched portions 5A that converge toward an area to be the semiconductor element mounting stage 52 are formed using a first progressive die. A side surface of the inner lead 51 is formed, and a support bar 53 that supports the semiconductor element mounting stage 52 is formed.
この後、この複数の第１の打ち抜き部5Aの先端から、
インナーリード51先端5Fの連結部（タイバー54）となる
領域分の所定の間隔をおいて、第２の打ち抜き部5Bを形
成する。Then, from the tips of the plurality of first punched portions 5A,
The second punched-out portion 5B is formed at a predetermined interval corresponding to a region serving as a connecting portion (tie bar 54) of the tip 5F of the inner lead 51.
そして、コイニング工程を経て、このインナーリード
51の先端5Fをタイバー54で一体的に連結した状態で、熱
処理するおよび鍍金処理等の所定の処理を行う。Then, through the coining process, this inner lead
With the tip 5F of 51 being integrally connected by a tie bar 54, a predetermined treatment such as heat treatment and plating treatment is performed.
そしてさらに、第４図（ｂ）に示すように、第２の順
送り金型を用いて第３の打ち抜き部5Dを形成し、前記サ
ポートバーに直交して設けられたタイバー54を切除し、
インナーリード51の先端5Fを形成し、分割形成し、リー
ドフレームが完成される。Further, as shown in FIG. 4 (b), a third punched portion 5D is formed using the second progressive die, and the tie bar 54 provided orthogonal to the support bar is cut off,
The tip 5F of the inner lead 51 is formed and divided to form a lead frame.
この方法では、第２の打ち抜き領域を形成して、半導
体素子搭載ステージ52とインナーリード先端のタイバー
54とを分離した後、ボンディングに必要な有効平坦幅を
確保するためコイニングがなされるが、コイニングによ
るインナーリード先端の伸びの分は第２の打ち抜き領域
に吸収され、インナーリード先端が半導体素子搭載ステ
ージ52側に移動するのみである。In this method, the second punched area is formed, and the semiconductor element mounting stage 52 and the tie bar at the tip of the inner lead are formed.
After separating from 54, coining is performed to secure the effective flat width required for bonding, but the amount of elongation of the inner lead tip due to coining is absorbed in the second punching area, and the inner lead tip is mounted with a semiconductor element. It only moves to the stage 52 side.
この状態で、熱処理をすると熱処理に必要な長手方向
へのテンションにより連結部（タイバー）54が変形し、
結果インナーリードが変形することになる。When heat treatment is performed in this state, the connecting portion (tie bar) 54 is deformed by the tension in the longitudinal direction required for heat treatment,
As a result, the inner leads are deformed.
（発明が解決しようとする課題） このように従来のリードフレームでは、連結片を除去
した際にインナーリード先端が不安定となり、ワイヤボ
ンディング時に支障をきたすという問題があった。(Problems to be Solved by the Invention) As described above, the conventional lead frame has a problem that the tip of the inner lead becomes unstable when the connecting piece is removed, which causes a problem during wire bonding.
また、インナーリード先端のコイニングは、ワイヤボ
ンディングに必要な有効平坦幅を得るためのもので、コ
イニング量が深ければ、潰された余肉分だけインナーリ
ードに延びが生じ、これによってパッドが下方に変位す
ることになり、変位量が大きければ熱処理工程や後のめ
っき工程における障害となる。The coining at the tip of the inner lead is to obtain an effective flat width required for wire bonding.If the coining depth is deep, the inner lead extends by the crushed extra thickness, which causes the pad to move downward. If the amount of displacement is large, it becomes an obstacle in the heat treatment process and the subsequent plating process.
本発明は、前記実情に鑑みてなされたもので、上記問
題点を解決し、高精度でボンディング性に優れ、高品質
でかつ低コストのリードフレームを提供することを目的
とする。The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a lead frame that solves the above problems and has high accuracy, excellent bonding properties, high quality, and low cost.
（課題を解決するための手段） そこで本発明の方法では、連結片を残して成型し、熱
処理を行ったのち、コイニングを行うようにしている。(Means for Solving the Problem) Therefore, in the method of the present invention, coining is carried out after molding with the connecting piece left and heat treatment.
すなわち、本発明の方法では、半導体素子搭載部と、
前記半導体素子搭載部を支持するサポートバーと、前記
半導体素子搭載部を取り囲むように配設された複数のイ
ンナーリードと、インナーリードそれぞれに連続した複
数のアウターリードとを備えたリードフレームを順送り
金型を用いて形状加工する方法において、各インナーリ
ードの先端部が互いにつながると共に、サポートバーに
おける半導体素子搭載部に接続する部分と半導体素子搭
載部とにもつながるように、インナーリード相互間の打
ち抜きを行う工程と、材料内部の残留歪みを除去すべく
熱処理を行う熱処理工程と、インナーリード先端部にコ
イニングを行いボンディング領域を形成する第２の成形
工程と、各インナーリード先端部が互いに分離するとと
もに、サポートバーにおける半導体素子搭載部に接続す
る部分および前記半導体素子搭載部からも分離するよう
に打ち抜きを行う第３の成形工程とを含む。That is, in the method of the present invention, the semiconductor element mounting portion,
A lead frame including a support bar that supports the semiconductor element mounting portion, a plurality of inner leads arranged so as to surround the semiconductor element mounting portion, and a plurality of outer leads that are continuous with the inner leads are sequentially fed. In the method of shape processing using a mold, punching between inner leads so that the tips of each inner lead are connected to each other and also to the part connected to the semiconductor element mounting part of the support bar and the semiconductor element mounting part. And a heat treatment step of performing a heat treatment to remove residual strain inside the material, a second molding step of coining the inner lead tip to form a bonding region, and the inner lead tips are separated from each other. Along with the part connected to the semiconductor element mounting part in the support bar and the above And a third molding step for punching as well separated from the conductive element mounting portion.
望ましくは、前記熱処理工程後、前記第２の成形工程
に先立ち、前記インナーリード先端部と前記半導体素子
搭載部との間に貫通孔を形成する貫通孔形成工程を含
み、前記第３の成形工程では、この貫通孔を含むように
分離して打ち抜きを行う。Desirably, after the heat treatment step and prior to the second molding step, a through hole forming step of forming a through hole between the inner lead tip portion and the semiconductor element mounting portion is included, and the third molding step is included. Then, punching is performed separately so as to include the through hole.
（作用） 上記方法によれば、コイニングに先立ち熱処理を行う
ようにしているため、焼鈍におけるテンションに耐え得
る引っ張り強度を有する状態で熱処理を行うことがで
き、熱処理中において変形をうけたりすることなく良好
な状態を維持することができる。(Operation) According to the above method, since the heat treatment is performed before the coining, the heat treatment can be performed in a state having a tensile strength that can withstand the tension during annealing, without being deformed during the heat treatment. A good state can be maintained.
そして、この熱処理後にコイニングを行うが、多少パ
ッドが変位しても弾性変形範囲内であり、パッドの成型
と共にインナーリードを分離すれば、この変位は解消す
る。Then, although coining is performed after this heat treatment, even if the pad is displaced to some extent, it is within the elastic deformation range, and this displacement can be eliminated by separating the inner lead together with the molding of the pad.
（実施例） 以下、本発明実施例のリードフレームの製造方法につ
いて、図面を参照しつつ詳細に説明する。(Example) Hereinafter, a method for manufacturing a lead frame according to an example of the present invention will be described in detail with reference to the drawings.
第１図（ａ）乃至第１図（ｄ）は、リードフレームの
製造工程を示す図である。1 (a) to 1 (d) are views showing the manufacturing process of the lead frame.
まず、第１図（ａ）に示すように、スタンピング法に
より、銅を主成分とする帯状材料を、所望の形状のイン
ナーリード、アウターリード、ダムバーなどの抜き型を
具備した第１の順送り金型（図示せず）に装着し、プレ
ス加工を行なうことにより、半導体素子搭載部11となる
領域に向かって収斂する複数の第１の打ち抜き部A1を形
成し、インナーリード12の側面を形成すると共に、半導
体素子搭載部11を支持するサポートバー15ならびにアウ
ターリード13を形成する。このとき、この複数の第１の
打ち抜き部A1の先端から、インナーリード12の先端の連
結部（タイバー17）となる領域分の所定の間隔をおい
て、半導体素子搭載部11が存在している。First, as shown in FIG. 1 (a), a first progressive metal stamping method is used to form a strip-shaped material containing copper as a main component into a die having a desired shape such as inner leads, outer leads, and dam bars. By mounting on a mold (not shown) and performing press working, a plurality of first punched-out portions A1 that converge toward a region to be the semiconductor element mounting portion 11 are formed, and side surfaces of the inner leads 12 are formed. At the same time, a support bar 15 and an outer lead 13 that support the semiconductor element mounting portion 11 are formed. At this time, the semiconductor element mounting portion 11 is present at a predetermined distance from the tips of the plurality of first punched portions A1 for a region serving as a connecting portion (tie bar 17) at the tips of the inner leads 12. .
この状態で熱処理を行う。 Heat treatment is performed in this state.
そして、第１図（ｂ）および第１図（ｃ）に示すよう
に、コイニングパンチを用いてインナーリード先端部の
コイニングを行う。12sはコイニング領域を示す。第１
図（ｃ）はコイニング領域を示す断面図である。Then, as shown in FIGS. 1 (b) and 1 (c), coining of the tip portion of the inner lead is performed using a coining punch. 12s indicates a coining area. First
FIG. 6C is a sectional view showing the coining region.
そして、このインナーリード12の先端12sをタイバー1
7で半導体素子搭載部11に一体的に連結した状態のま
ま、パラジウムめっき処理等の所定の処理を行う。Then, attach the tip 12s of the inner lead 12 to the tie bar 1
A predetermined process such as a palladium plating process is performed while the semiconductor device mounting portion 11 is integrally connected at 7.
そしてさらに、第２の順送り金型を用いて、タイバー
17を切除し、インナーリード12の先端面を形成して、イ
ンナーリード12相互間を分割形成し、第１図（ｄ）に示
すようなリードフレームが完成される。Then, using the second progressive die, the tie bar
17 is cut off to form the tip surfaces of the inner leads 12 and the inner leads 12 are separated from each other to form a lead frame as shown in FIG. 1 (d).
このようにして形成されたリードフレームによれば、
インナーリード先端は、常に安定した状態でワイヤボン
ディングを行うことができ、歩留まりが大幅に向上す
る。According to the lead frame formed in this way,
The tip of the inner lead can always be wire-bonded in a stable state, and the yield is greatly improved.
なお、前記実施例では、インナーリード側縁の打ち抜
きおよび熱処理の後、そのままの状態でコイニグを行う
ようにしたが、インナーリード先端とパッドとの間を打
ち抜きを行うに先立ち、インナーリード先端とパッド周
縁との間の少なくとも一部に貫通孔を形成し、コイニン
グによる延びをこの貫通孔で吸収するようにしても良
い。In the above-mentioned embodiment, after the side edges of the inner leads are punched and the heat treatment is performed, the coining is performed as it is. However, prior to punching between the inner leads tips and the pads, the inner leads tips and the pads are A through hole may be formed at least at a part between the periphery and the extension by coining may be absorbed by the through hole.
次に、本発明の第２の実施例としてこのリードフレー
ムの製造方法について説明する。Next, a method of manufacturing this lead frame will be described as a second embodiment of the present invention.
まず、第２図（ａ）および第２図（ｂ）に示すよう
に、銅を主成分とする帯状材料を、所望の形状のインナ
ーリード（先端面を除く）１、タイバー２、アウターリ
ード３などの抜き型を具備した順送り金型に装着し、プ
レス加工を行なうことにより、第１の打ち抜き領域A1を
順次形成し、インナーリードの先端面を残してインナー
リード部12をパターニングする。First, as shown in FIGS. 2 (a) and 2 (b), a strip-shaped material containing copper as a main component is used to form an inner lead (excluding the tip surface) 1, a tie bar 2, and an outer lead 3 each having a desired shape. The first punched area A1 is sequentially formed by mounting on a progressive die having a punching die such as the above, and press working is performed, and the inner lead portion 12 is patterned while leaving the tip surface of the inner lead.
この後、この状態で熱処理を行う。 Then, heat treatment is performed in this state.
そして第２図（ｃ）に示すように、ダイパッド形成領
域11sとインナーリード先端との間に貫通孔ｈを形成す
る。Then, as shown in FIG. 2C, a through hole h is formed between the die pad formation region 11s and the inner lead tip.
さらに、第２図（ｄ）および第２図（ｅ）に示すよう
に、コイニングパンチを用いてインナーリード先端部の
コイニングを行う。12sはコイニング領域を示す。第２
図（ｅ）はコイニング領域を示す断面図である。Further, as shown in FIGS. 2 (d) and 2 (e), coining of the tip of the inner lead is performed using a coining punch. 12s indicates a coining area. Second
FIG. 6E is a sectional view showing the coining region.
そして、このインナーリード12の先端12sをタイバー1
7で半導体素子搭載部11に一体的に連結した状態のま
ま、めっき工程やテーピング工程等の所定の処理を行
う。Then, attach the tip 12s of the inner lead 12 to the tie bar 1
A predetermined process such as a plating process and a taping process is performed while the semiconductor device mounting portion 11 is integrally connected at 7.
そして、第２図（ｆ）に示すように、前記第２図
（ａ）の成型工程で残されたインナーリード端部の第２
の打ち抜き領域A2（キャビテイ領域）を打ち抜き、ダイ
パッド11とインナーリード先端とを分離し、リードフレ
ームの形状加工が終了する。Then, as shown in FIG. 2 (f), a second inner lead end portion left in the molding step of FIG. 2 (a) is formed.
The punching area A2 (cavity area) is punched out, the die pad 11 and the inner lead tip are separated, and the lead frame shape processing is completed.
このようにして形成されたリードフレームは、前記第
１の実施例による効果に加えてコイニング工程における
材料の延びによる変形も、この貫通孔が逃げ口となって
防止することができ、この後、インナーリード先端とパ
ッドとの間を打ち抜きを行うようにすれば、インナーリ
ードの長さも高精度に制御することが可能となる。In addition to the effect of the first embodiment, the lead frame formed in this manner can prevent deformation due to the extension of the material in the coining step, in which the through hole serves as an escape port. By punching between the tip of the inner lead and the pad, the length of the inner lead can be controlled with high precision.
このリードフレームは、素子チップの搭載、ワイヤボ
ンディング、樹脂封止などの工程を経て半導体素子とし
て完成されるが、インナーリード位置が高精度に維持さ
れているためボンディング性が良好である。Although this lead frame is completed as a semiconductor element through steps such as mounting of element chips, wire bonding, and resin sealing, the inner lead position is maintained with high accuracy, and thus the bonding property is good.
なお、この貫通孔の位置及び形状については、実施例
に限定されることなく適宜変形可能である。また、第２
の打ち抜き領域に近い形状の貫通孔を形成しておくよう
にし、凹部形成後は、インナーリードの長さをそろえる
程度に打ち抜きを行うようにしても良い。The position and shape of the through hole are not limited to the embodiment and can be modified as appropriate. Also, the second
It is also possible to form a through-hole having a shape close to the punching area, and punching is performed to the extent that the lengths of the inner leads are made uniform after the recess is formed.
また、前記実施例では、リードフレーム材料として銅
を用いたが、銅に限定されることなく、他の材料を用い
てもよいことは言うまでもない。Further, although copper is used as the lead frame material in the above embodiment, it is needless to say that the material is not limited to copper and other materials may be used.
さらにまた、熱処理前にインナーリードの捩じれを矯
正するための軽い平打ち工程含むようにしてもよい。Furthermore, before the heat treatment, a light flat staking step for correcting the twist of the inner leads may be included.
以上説明してきたように、本発明のリードフレームの
製造方法によれば、コイニングに先立ち熱処理を行うよ
うにしているため、焼鈍におけるテンションに耐え得る
引っ張り強度を有する状態で熱処理を行うことができ、
熱処理中において変形をうけたりすることなく良好な状
態を維持することができ、高精度で信頼性の高いリード
フレームを得ることが可能となる。As described above, according to the lead frame manufacturing method of the present invention, since the heat treatment is performed prior to coining, the heat treatment can be performed in a state having a tensile strength that can withstand the tension during annealing,
A good state can be maintained without being deformed during the heat treatment, and a highly accurate and highly reliable lead frame can be obtained.
第１図（ａ）乃至第１図（ｄ）は本発明の第１の実施例
のリードフレームの製造方法を示す図、第２図（ａ）乃
至第２図（ｆ）は本発明の第２の実施例のリードフレー
ムの製造方法を示す図、第３図は従来例のリードフレー
ムの先端部を示す図、第４図（ａ）および第４図（ｂ）
は従来例のリードフレームの製造工程を示す図である。 51……インナーリード、52……半導体素子搭載ステー
ジ、53……サポートバー、54……タイバー、5A……第１
の打ち抜き部、5F……先端、5B……第２の打ち抜き部、
5D……第３の打ち抜き部、11……半導体素子搭載部、12
……インナーリード、12s……インナーリード先端、13
……アウターリード、14……ダムバー、15……サポート
バー、16……サイドバー、17……タイバー。1 (a) to 1 (d) are views showing a method of manufacturing a lead frame according to the first embodiment of the present invention, and FIGS. 2 (a) to 2 (f) are views showing the present invention. FIG. 3 is a diagram showing a method of manufacturing a lead frame of the second embodiment, FIG. 3 is a diagram showing a tip portion of a lead frame of a conventional example, FIGS.
FIG. 6 is a diagram showing a manufacturing process of a conventional lead frame. 51 …… Inner lead, 52 …… Semiconductor element mounting stage, 53 …… Support bar, 54 …… Tie bar, 5A …… First
Punched part, 5F …… tip, 5B …… second punched part,
5D: Third punching part, 11: Semiconductor element mounting part, 12
…… Inner lead, 12s …… Inner lead tip, 13
Outer leads, 14 dambars, 15 support bars, 16 sidebars, 17 tie bars.
Claims (2)
部を支持するサポートバーと、前記半導体素子搭載部を
取り囲むように配設された複数のインナーリードと、イ
ンナーリードそれぞれに連続した複数のアウターリード
とを備えたリードフレームを順送り金型を用いて形状加
工する方法において、 各インナーリードの先端部が互いにつながると共に、サ
ポートバーにおける半導体素子搭載部に接続する部分と
半導体素子搭載部とにもつながるように、インナーリー
ド相互間の打ち抜きを行う工程と、 材料内部の残留歪みを除去すべく熱処理を行う熱処理工
程と、 インナーリード先端部にコイニングを行いボンディング
領域を形成する第２の成形工程と、 各インナーリード先端部が互いに分離するとともに、サ
ポートバーにおける半導体素子搭載部に接続する部分お
よび前記半導体素子搭載部からも分離するように打ち抜
きを行う第３の成形工程とを含むことを特徴とするリー
ドフレームの製造方法。1. A semiconductor element mounting portion, a support bar for supporting the semiconductor element mounting portion, a plurality of inner leads arranged so as to surround the semiconductor element mounting portion, and a plurality of continuous inner leads. In a method of shaping a lead frame having outer leads using a progressive die, the tip portions of the inner leads are connected to each other, and the support bar is connected to the semiconductor element mounting portion and the semiconductor element mounting portion. So as to connect with each other, a step of punching between inner leads, a heat treatment step of performing heat treatment to remove residual strain inside the material, and a second molding step of coining the tip of the inner leads to form a bonding area. And the tips of the inner leads are separated from each other, and the semiconductor A method of manufacturing a lead frame, comprising: a part connected to the element mounting part and a third molding step in which punching is performed so as to be separated from the semiconductor element mounting part.
先立ち、 前記インナーリード先端部と前記半導体素子搭載部との
間に貫通孔を形成する貫通孔形成工程を含み、 前記第３の成形工程では、この貫通孔を含むように分離
して打ち抜き行う工程であることを特徴とする請求項
（１）記載のリードフレームの製造方法。2. A step of forming a through hole between the tip of the inner lead and the semiconductor element mounting portion after the heat treatment step and prior to the second molding step. The method of manufacturing a lead frame according to claim (1), wherein the molding step is a step in which the through hole is separated and punched.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2126493A JPH0821660B2 (en) | 1990-05-16 | 1990-05-16 | Lead frame manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2126493A JPH0821660B2 (en) | 1990-05-16 | 1990-05-16 | Lead frame manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0425053A JPH0425053A (en) | 1992-01-28 |
| JPH0821660B2 true JPH0821660B2 (en) | 1996-03-04 |
Family
ID=14936575
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2126493A Expired - Fee Related JPH0821660B2 (en) | 1990-05-16 | 1990-05-16 | Lead frame manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0821660B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007225021A (en) * | 2006-02-23 | 2007-09-06 | Kayaba Ind Co Ltd | Shock absorber |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56164565A (en) * | 1980-05-22 | 1981-12-17 | Yasukawa Seiki Kk | Lead frame and manufacture thereof |
| JPS56165526A (en) * | 1980-05-26 | 1981-12-19 | Toshiba Corp | Coining method |
| JPS5788938A (en) * | 1980-11-20 | 1982-06-03 | Toyota Motor Corp | Method for hot coining |
| JPS60103653A (en) * | 1983-11-10 | 1985-06-07 | Nec Corp | Manufacture of semiconductor device |
-
1990
- 1990-05-16 JP JP2126493A patent/JPH0821660B2/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56164565A (en) * | 1980-05-22 | 1981-12-17 | Yasukawa Seiki Kk | Lead frame and manufacture thereof |
| JPS56165526A (en) * | 1980-05-26 | 1981-12-19 | Toshiba Corp | Coining method |
| JPS5788938A (en) * | 1980-11-20 | 1982-06-03 | Toyota Motor Corp | Method for hot coining |
| JPS60103653A (en) * | 1983-11-10 | 1985-06-07 | Nec Corp | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0425053A (en) | 1992-01-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20040124506A1 (en) | Semiconductor device and a method of manufacturing the same | |
| US20080122048A1 (en) | Stamped leadframe and method of manufacture thereof | |
| US5202577A (en) | Leadframe having a particular dam bar | |
| JPH05144992A (en) | Semiconductor device and its production, lead frame used for semiconductor production and its production | |
| KR100568225B1 (en) | Lead Frame and method for fabricating semiconductor package using the same | |
| US6780679B2 (en) | Semiconductor device and method of manufacturing the same | |
| KR100252737B1 (en) | Resin-sealed semiconductor device and its manufacture | |
| KR100192870B1 (en) | Lead frame | |
| JP2008113021A (en) | Manufacturing method of semiconductor device | |
| JPH0821660B2 (en) | Lead frame manufacturing method | |
| JP2528192B2 (en) | Semiconductor device | |
| JP3805767B2 (en) | Lead frame manufacturing method and semiconductor device manufacturing method using the same | |
| JP7057727B2 (en) | Lead frames and semiconductor devices | |
| JP4111499B2 (en) | Lead frame | |
| JPS63250849A (en) | Lead frame excellent in wire bonding property | |
| JPH0821656B2 (en) | Lead frame manufacturing method | |
| JPH0828449B2 (en) | Lead frame manufacturing method | |
| JP2707153B2 (en) | Lead frame manufacturing method | |
| JPS5812452Y2 (en) | semiconductor equipment | |
| JPS63308359A (en) | Manufacture of lead frame | |
| JP2504860B2 (en) | Manufacturing method of lead frame | |
| JPH02202046A (en) | Lead frame and manufacture of semiconductor device using same | |
| JPH10209361A (en) | Multiple lead frame | |
| JP2006216979A (en) | Manufacturing method for semiconductor device | |
| JPH01133340A (en) | Lead frame and manufacture thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080304 Year of fee payment: 12 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090304 Year of fee payment: 13 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090304 Year of fee payment: 13 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100304 Year of fee payment: 14 |
|
| LAPS | Cancellation because of no payment of annual fees |