JPH0821571B2 - Fine pattern formation method - Google Patents
Fine pattern formation methodInfo
- Publication number
- JPH0821571B2 JPH0821571B2 JP59277298A JP27729884A JPH0821571B2 JP H0821571 B2 JPH0821571 B2 JP H0821571B2 JP 59277298 A JP59277298 A JP 59277298A JP 27729884 A JP27729884 A JP 27729884A JP H0821571 B2 JPH0821571 B2 JP H0821571B2
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- substrate
- film
- mask
- fine pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 title claims description 15
- 230000007261 regionalization Effects 0.000 title description 2
- 239000000758 substrate Substances 0.000 claims description 23
- 239000000463 material Substances 0.000 claims description 7
- 238000007687 exposure technique Methods 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 238000005530 etching Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000001020 plasma etching Methods 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Description
【発明の詳細な説明】 ＜産業上の利用分野＞ 本発明は半導体素子形成においてマスク材により被覆
されていない領域をエッチングし、微細パターン形成す
る方法に関するものである。The present invention relates to a method for forming a fine pattern by etching a region not covered with a mask material in forming a semiconductor element.
＜従来技術とその問題点＞ 近来、半導体デバイスの高集積化にともない微細パタ
ーン形成はリソグラフィー技術とドライエッチング技術
の向上により著しい進歩をとげている。たとえばジャー
ナル・オブ・バキューム・サイエンス・アンド・テクノ
ロジー（J.Vac.Sci.technol.）15巻1978年319〜326ペー
ジにおいては四弗化炭素ガスにより反応性スパッタエッ
チングによりマスクパターン幅に変化を生じない垂直断
面形状を有するシリコン酸化膜パターン形成が可能なこ
とが報告されている。前例のみならず、反応性スパッタ
エッチングにおいてはエッチングガスとエッチング条件
を適当に選ぶことで、シリコン酸化膜に限らず、絶縁
体，半導体，金属などがマスク寸法に一致して加工可能
である。一方、リソグラフィー技術は、従来の光投影露
光方法に代り、紫外光縮小投影露光,X線露光，電子線露
光技術の開発には解像度はサブミクロン寸法まで可能と
なっている。<Conventional Technology and Its Problems> Recently, with the high integration of semiconductor devices, fine pattern formation has made remarkable progress by improving lithography technology and dry etching technology. For example, in Journal of Vacuum Science and Technology (J.Vac.Sci.technol.) Vol. It has been reported that it is possible to form a silicon oxide film pattern having no vertical cross-sectional shape. Not only in the previous example, but in reactive sputter etching, by properly selecting the etching gas and etching conditions, not only the silicon oxide film, but also insulators, semiconductors, metals, etc. can be processed according to the mask size. On the other hand, the lithography technology is capable of submicron resolution in the development of ultraviolet light reduction projection exposure, X-ray exposure, and electron beam exposure technology instead of the conventional light projection exposure method.
しかし前記露光技術により得られる微細パターンは孤
立パターンにおけるものであり、パターンが近接したり
交差したりする複雑なパターンにおいては問題を生じ
る。たとえば、紫外光縮小投影露光法により第２図
（ａ）に示すマスクパターンを基板上に転写する場合、
第２図（ｂ）に示すようにようにパターンが交差する部
分では近接効果により転写されたレジストパターン角部
で丸みを生じる。However, the fine pattern obtained by the exposure technique is an isolated pattern, which causes a problem in a complicated pattern in which the patterns are close to each other or intersect each other. For example, when the mask pattern shown in FIG. 2 (a) is transferred onto a substrate by the ultraviolet light reduction projection exposure method,
As shown in FIG. 2 (b), the corners of the transferred resist pattern are rounded by the proximity effect at the portions where the patterns intersect.
このような現象は光露光に限ったものでなく、Ｘ線露
光，電子線露光においても程度の差はあれ、避けられな
い問題である。レジストパターンが第２図のごとき形状
であれば異方性エッチングを用いればレジストパターン
どうりにエッチングされることになり、微細半導体素子
形成に対し支障となる。この支障とはたとえば次のよう
なものである。Si（100）単結晶基板上にSiO2等の絶縁
膜を形成し、この絶縁膜を上記のような従来方法で絶縁
膜側壁を（100）方向に向くようにパターニングすると
角部で丸みを生じる。このあとSiの気相選択エピタキシ
ャル成長を行うと、丸みのために角部が完全にはSiで埋
まらずファセットとよばれる斜面がかなり大きく形成さ
れてしまう。エピ成長したSi膜に半導体素子を形成する
とこのファセットで配線が断線したりする支障が生じ
る。Such a phenomenon is not limited to light exposure, and is an unavoidable problem to some extent in X-ray exposure and electron beam exposure. If the resist pattern has a shape as shown in FIG. 2, if anisotropic etching is used, the resist pattern is etched as if it were a resist pattern, which hinders formation of a fine semiconductor device. This obstacle is, for example, as follows. When an insulating film such as SiO 2 is formed on a Si (100) single crystal substrate and this insulating film is patterned by the conventional method so that the side wall of the insulating film faces the (100) direction, the corners are rounded. . When vapor phase selective epitaxial growth of Si is performed after this, the corners are not completely filled with Si due to roundness, and a slope called a facet is formed to be considerably large. When a semiconductor element is formed on the epitaxially grown Si film, this facet causes troubles such as disconnection of wiring.
＜発明の目的＞ 本発明は、半導体素子形成における微細パターン加工
する際、パターン交差部における丸みをなくし、角型形
状を有する微細パターン形成方法を提供することにあ
る。<Object of the Invention> The present invention is to provide a method for forming a fine pattern having a square shape by eliminating the roundness at the pattern crossing portion when the fine pattern is processed in forming a semiconductor element.
＜発明の構成＞ 本発明によれば基板上あるいは基板上に堆積された膜
上に露光技術を用いてマスクパターンを形成し、前記マ
スクパターンによって被覆されていない基板あるいは基
板上に堆積された膜を異方性エッチングするパターン形
成方法において、はじめに、第一のマスク材により直線
パターンを形成し、次いで前記直線パターンと交差する
第２のマスク材からなる直線パターンを形成し、次いで
前記基板あるいは基板上に堆積された膜を異方性エッチ
ングすると交差パターンが得られる。<Constitution of the Invention> According to the present invention, a mask pattern is formed on a substrate or a film deposited on the substrate by using an exposure technique, and the substrate not covered with the mask pattern or the film deposited on the substrate. In the pattern forming method of anisotropic etching, first, a linear pattern is formed by a first mask material, then a linear pattern is formed by a second mask material intersecting the linear pattern, and then the substrate or the substrate is formed. Anisotropic etching of the deposited film yields a cross pattern.
＜構成の詳細な説明＞ 本発明は以下の構成をとることにより従来技術の問題
点を解決した。すなわち、基板あるいは基板上に堆積さ
れた膜を異方性エッチングする際にパターン交差部に丸
みを生じさせたくない領域ではマスクパターン形成工程
を複数回行なう。はじめに第一のマスク材による直線パ
ターンを形成し、次いで前記パターンと交差する第２の
マスク材からなるパターンを形成する。つまり一回の露
光工程においては直線パターンしか露光しないので露光
における近接効果が防止できる。次に第一と第２のマス
クを用いて基板あるいは基板上に堆積された膜を反応性
イオンエッチング法により異方性エッチングすることで
パターン交差部に丸みの生じない角型パターン形成が可
能となる。このようにして、パターンが微細化した場合
でも、所望の交差パターンが得られる。<Detailed Description of Configuration> The present invention has solved the problems of the prior art by adopting the following configuration. That is, the mask pattern forming step is performed a plurality of times in a region where it is not desired to make the pattern intersection round when anisotropically etching the substrate or the film deposited on the substrate. First, a linear pattern is formed by the first mask material, and then a pattern made of a second mask material that intersects the pattern is formed. That is, since only a linear pattern is exposed in one exposure process, the proximity effect in exposure can be prevented. Then, the substrate or the film deposited on the substrate is anisotropically etched by the reactive ion etching method using the first and second masks, thereby making it possible to form a rectangular pattern without rounding at the pattern intersection. Become. In this way, a desired intersecting pattern can be obtained even when the pattern is miniaturized.
＜実施例＞ 以下、本発明の実施例について図面を用いて詳細に説
明する。<Example> Hereinafter, an example of the present invention is described in detail using a drawing.
第１図は本発明の実施例を説明するために、主要な製
造工程における断面あるいは平面構造を示した模式図で
ある。すなわち、（100）面方位のｐ型シリコン基板１
に熱酸化により約２μｍ厚さのシリコン酸化膜２を形成
した後、減圧CVD法により約0.3μｍ厚さの多結晶シリコ
ン膜を堆積し、写真蝕刻法と反応性イオンエッチング法
により第１のマスクとなる多結晶シリコン膜の直線パタ
ーン３を基板の（100）方向と平行に形成すると第１図
（ａ），（ｇ）′の構造を得る。FIG. 1 is a schematic view showing a cross section or a planar structure in a main manufacturing process for explaining an embodiment of the present invention. That is, the p-type silicon substrate 1 having the (100) plane orientation
After forming a silicon oxide film 2 having a thickness of about 2 μm by thermal oxidation, a polycrystalline silicon film having a thickness of about 0.3 μm is deposited by the low pressure CVD method, and the first mask is formed by the photo-etching method and the reactive ion etching method. When the linear pattern 3 of the polycrystalline silicon film to be formed is formed parallel to the (100) direction of the substrate, the structure shown in FIGS. 1 (a) and (g) 'is obtained.
次に、下層有機膜，中間層シリカ塗布膜、および上層
レジストで構成される三層レジストに対して、上層を通
常の写真蝕刻法により前記多結晶シリコン膜パターンと
直交する方向のレジストパターンを形成し、反応性イオ
ンエッチングにより中間層シリカ膜をエッチングし、つ
づいて中間層シリカ膜をマスクに下層有機膜をO2反応性
イオンエッチングで第２のマスクとなる有機膜パターン
４を形成すると第１図（ｂ），（ｈ）′の構造を得る。Next, a resist pattern in a direction orthogonal to the polycrystalline silicon film pattern is formed on the upper layer of a three-layer resist including a lower organic film, an intermediate silica coating film, and an upper resist by a normal photoetching method. Then, the intermediate layer silica film is etched by reactive ion etching, and then the lower layer organic film is formed with the intermediate layer silica film as a mask by O 2 reactive ion etching to form an organic film pattern 4 serving as a second mask. The structures of FIGS. (B) and (h) 'are obtained.
つづいて、第１と第２のマスクを用いて露出したシリ
コン酸化膜を反応性イオンエッチング法により垂直断面
形状を有するSiO2膜パターンを形成し、マスクを除去す
ると第１図（ｃ），（ｉ）′の構造を得る。Subsequently, a SiO 2 film pattern having a vertical cross-sectional shape is formed on the exposed silicon oxide film by the reactive ion etching method using the first and second masks, and the mask is removed. i) ′ structure is obtained.
次にSiH2Cl2とH2から成るガス系にHClガスを約1vol％
程度加え、950℃の温度でシリコン基板にのみ選択的に
シリコンエピタキシャル成長させ、エピタキシャルシリ
コン膜５厚さが２μｍのとき第１図（ｄ）の構造を得
る。本実施例のようにSiO2パターン交差部が直交してい
ると、エピタキシャル層でのファセットの大きさが小さ
くなり、平坦性の良い基板が得られた。また、エピタキ
シャル層のSiO2膜近傍おける積層欠陥密度も低減した。
この後、通常のｎチャネルMOSFETを形成するために、厚
さ200Åのゲート酸化膜６を形成し、次いでイオン注入
によりホウ素を加速エネルギー30keVで1.5×1012cm-2と
100keVで２×1012cm2注入し、次いで減圧CVD法により多
結晶シリコンを4500Å堆積し、反応性イオンエッチング
によりゲート電極７を形成すると第１図（ｅ）の構造を
得る。次いでヒ素を加速エネルギー150keVで５×1015cm
-2イオン注入し、高濃度ｎ型層８を形成し、次いで、ポ
リシコンゲート電極にリンを拡散する。次に、CVDSiO2
膜10を堆積し、コンタクトホールをあけ、アルミ破線11
を行なうと第１図（ｆ）に示すようなｎチャネルMOS FE
Tが得られる。Next, HCl gas was added to the gas system consisting of SiH 2 Cl 2 and H 2 at about 1 vol%.
In addition, the silicon epitaxial growth is selectively performed only on the silicon substrate at a temperature of 950 ° C., and when the thickness of the epitaxial silicon film 5 is 2 μm, the structure of FIG. 1 (d) is obtained. When the SiO 2 pattern intersecting portions were orthogonal to each other as in this example, the facet size in the epitaxial layer was small, and a substrate with good flatness was obtained. Also, the stacking fault density near the SiO 2 film of the epitaxial layer was reduced.
Then, in order to form a normal n-channel MOSFET, a gate oxide film 6 having a thickness of 200 Å is formed, and then boron is ion-implanted at an acceleration energy of 30 keV to 1.5 × 10 12 cm -2 .
After implanting 2 × 10 12 cm 2 at 100 keV, then depositing 4500 Å of polycrystalline silicon by the low pressure CVD method and forming the gate electrode 7 by reactive ion etching, the structure of FIG. 1 (e) is obtained. Then arsenic was accelerated to 150 keV and 5 × 10 15 cm
-2 ion implantation is performed to form a high concentration n-type layer 8, and then phosphorus is diffused into the polysilicon gate electrode. Next, CVD SiO 2
Deposit film 10, open contact holes, dashed aluminum line 11
Then, the n-channel MOS FE as shown in FIG.
You get T.
このように本実施例によれば、エピタキシャル成長時
のファセットの大きさが減少し、平坦性が向上した。さ
らにエピタキシャル成長層の積層欠陥密度が低減したた
めにｎチャネルMOS FET等のデバイスを作成した場合の
製造歩留りが向上した。As described above, according to this example, the size of the facets during the epitaxial growth was reduced, and the flatness was improved. Further, since the stacking fault density of the epitaxial growth layer is reduced, the manufacturing yield when a device such as an n-channel MOS FET is manufactured is improved.
＜発明の効果＞ 本発明を用いることにより、露光の際の近接効果によ
る交差部の丸みを防止し、角型形状を有する微細パター
ン形成が可能となった。<Effects of the Invention> By using the present invention, it is possible to prevent the rounding of the intersection portion due to the proximity effect at the time of exposure and to form a fine pattern having a square shape.
第１図は本発明の実施例におけるMOSFETの製造方法を順
を追って断面構造あるいは平面構造を示す図で、
（ａ），（ｂ），（ｃ），（ｄ），（ｅ），（ｆ）は断
面図、（ｇ′），（ｈ′），（ｉ′）は平面図。第２図
（ａ），（ｂ）はレチクルパターンと従来方法を用いた
レジストパターンとの転写変化を示す模式的平面図であ
る。 図において １……シリコン基板、２……シリコン酸化膜 ３……多結晶シリコン膜パターン（第１のマスク） ４……有機膜パターン（第２のマスク） ５……エピタキシャルシリコン層 ６……ゲート酸化膜、７……ゲート電極 ８……高濃度ｎ型層、９……CVDSiO2膜 10……アルミニウム配線 21……レチクルパターン 22……レジストパターンFIG. 1 is a diagram showing a cross-sectional structure or a planar structure step by step in a MOSFET manufacturing method according to an embodiment of the present invention.
(A), (b), (c), (d), (e), and (f) are sectional views, and (g '), (h'), and (i ') are plan views. FIGS. 2A and 2B are schematic plan views showing transfer changes between the reticle pattern and the resist pattern using the conventional method. In the figure, 1 ... Silicon substrate, 2 ... Silicon oxide film 3 ... Polycrystalline silicon film pattern (first mask) 4 ... Organic film pattern (second mask) 5 ... Epitaxial silicon layer 6 ... Gate Oxide film, 7 ... Gate electrode 8 ... High-concentration n-type layer, 9 ... CVDSiO 2 film 10 ... Aluminum wiring 21 ... Reticle pattern 22 ... Resist pattern
Claims (1)
光技術を用いてマスクパターンを形成し、前記マスクパ
ターンによって被覆されていない基板あるいは基板上に
堆積された膜を異方性エッチングするパターン形成方法
において、はじめに第一のマスク材により直線パターン
を形成し、次いで前記直線パターンと交差にする第二の
マスク材からなる直線パターンを形成し、次いで前記基
板あるいは基板上に堆積された膜を異方性エッチング
し、交差パターンを形成することを特徴とする微細パタ
ーン形成方法。1. A mask pattern is formed on a substrate or a film deposited on the substrate by using an exposure technique, and the substrate not covered by the mask pattern or the film deposited on the substrate is anisotropically etched. In the pattern forming method, first, a linear pattern is formed by a first mask material, then a linear pattern made of a second mask material that intersects with the linear pattern is formed, and then the substrate or a film deposited on the substrate. Is anisotropically etched to form a cross pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59277298A JPH0821571B2 (en) | 1984-12-26 | 1984-12-26 | Fine pattern formation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59277298A JPH0821571B2 (en) | 1984-12-26 | 1984-12-26 | Fine pattern formation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61154037A JPS61154037A (en) | 1986-07-12 |
| JPH0821571B2 true JPH0821571B2 (en) | 1996-03-04 |
Family
ID=17581583
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59277298A Expired - Lifetime JPH0821571B2 (en) | 1984-12-26 | 1984-12-26 | Fine pattern formation method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0821571B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0795543B2 (en) * | 1985-10-29 | 1995-10-11 | ソニー株式会社 | Etching method |
| KR100334577B1 (en) * | 1999-08-06 | 2002-05-03 | 윤종용 | Method of forming a trench in an insulating layer exceeding the photolithographic resolution in a semiconductor manufacturing |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58175830A (en) * | 1982-04-08 | 1983-10-15 | Matsushita Electric Ind Co Ltd | Forming method for pattern |
-
1984
- 1984-12-26 JP JP59277298A patent/JPH0821571B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61154037A (en) | 1986-07-12 |
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