JPH0821571B2 - Fine pattern formation method - Google Patents

Description

The present invention relates to a method for forming a fine pattern by etching a region not covered with a mask material in forming a semiconductor element.

<Conventional Technology and Its Problems> Recently, with the high integration of semiconductor devices, fine pattern formation has made remarkable progress by improving lithography technology and dry etching technology. For example, in Journal of Vacuum Science and Technology (J.Vac.Sci.technol.) Vol. It has been reported that it is possible to form a silicon oxide film pattern having no vertical cross-sectional shape. Not only in the previous example, but in reactive sputter etching, by properly selecting the etching gas and etching conditions, not only the silicon oxide film, but also insulators, semiconductors, metals, etc. can be processed according to the mask size. On the other hand, the lithography technology is capable of submicron resolution in the development of ultraviolet light reduction projection exposure, X-ray exposure, and electron beam exposure technology instead of the conventional light projection exposure method.

However, the fine pattern obtained by the exposure technique is an isolated pattern, which causes a problem in a complicated pattern in which the patterns are close to each other or intersect each other. For example, when the mask pattern shown in FIG. 2 (a) is transferred onto a substrate by the ultraviolet light reduction projection exposure method,
As shown in FIG. 2 (b), the corners of the transferred resist pattern are rounded by the proximity effect at the portions where the patterns intersect.

Such a phenomenon is not limited to light exposure, and is an unavoidable problem to some extent in X-ray exposure and electron beam exposure. If the resist pattern has a shape as shown in FIG. 2, if anisotropic etching is used, the resist pattern is etched as if it were a resist pattern, which hinders formation of a fine semiconductor device. This obstacle is, for example, as follows. When an insulating film such as SiO ₂ is formed on a Si (100) single crystal substrate and this insulating film is patterned by the conventional method so that the side wall of the insulating film faces the (100) direction, the corners are rounded. . When vapor phase selective epitaxial growth of Si is performed after this, the corners are not completely filled with Si due to roundness, and a slope called a facet is formed to be considerably large. When a semiconductor element is formed on the epitaxially grown Si film, this facet causes troubles such as disconnection of wiring.

<Object of the Invention> The present invention is to provide a method for forming a fine pattern having a square shape by eliminating the roundness at the pattern crossing portion when the fine pattern is processed in forming a semiconductor element.

<Constitution of the Invention> According to the present invention, a mask pattern is formed on a substrate or a film deposited on the substrate by using an exposure technique, and the substrate not covered with the mask pattern or the film deposited on the substrate. In the pattern forming method of anisotropic etching, first, a linear pattern is formed by a first mask material, then a linear pattern is formed by a second mask material intersecting the linear pattern, and then the substrate or the substrate is formed. Anisotropic etching of the deposited film yields a cross pattern.

<Detailed Description of Configuration> The present invention has solved the problems of the prior art by adopting the following configuration. That is, the mask pattern forming step is performed a plurality of times in a region where it is not desired to make the pattern intersection round when anisotropically etching the substrate or the film deposited on the substrate. First, a linear pattern is formed by the first mask material, and then a pattern made of a second mask material that intersects the pattern is formed. That is, since only a linear pattern is exposed in one exposure process, the proximity effect in exposure can be prevented. Then, the substrate or the film deposited on the substrate is anisotropically etched by the reactive ion etching method using the first and second masks, thereby making it possible to form a rectangular pattern without rounding at the pattern intersection. Become. In this way, a desired intersecting pattern can be obtained even when the pattern is miniaturized.

<Example> Hereinafter, an example of the present invention is described in detail using a drawing.

FIG. 1 is a schematic view showing a cross section or a planar structure in a main manufacturing process for explaining an embodiment of the present invention. That is, the p-type silicon substrate 1 having the (100) plane orientation
After forming a silicon oxide film 2 having a thickness of about 2 μm by thermal oxidation, a polycrystalline silicon film having a thickness of about 0.3 μm is deposited by the low pressure CVD method, and the first mask is formed by the photo-etching method and the reactive ion etching method. When the linear pattern 3 of the polycrystalline silicon film to be formed is formed parallel to the (100) direction of the substrate, the structure shown in FIGS. 1 (a) and (g) 'is obtained.

Next, a resist pattern in a direction orthogonal to the polycrystalline silicon film pattern is formed on the upper layer of a three-layer resist including a lower organic film, an intermediate silica coating film, and an upper resist by a normal photoetching method. Then, the intermediate layer silica film is etched by reactive ion etching, and then the lower layer organic film is formed with the intermediate layer silica film as a mask by O ₂ reactive ion etching to form an organic film pattern 4 serving as a second mask. The structures of FIGS. (B) and (h) 'are obtained.

Subsequently, a SiO ₂ film pattern having a vertical cross-sectional shape is formed on the exposed silicon oxide film by the reactive ion etching method using the first and second masks, and the mask is removed. i) ′ structure is obtained.

Next, HCl gas was added to the gas system consisting of SiH ₂ Cl ₂ and H ₂ at about 1 vol%.
In addition, the silicon epitaxial growth is selectively performed only on the silicon substrate at a temperature of 950 ° C., and when the thickness of the epitaxial silicon film 5 is 2 μm, the structure of FIG. 1 (d) is obtained. When the SiO ₂ pattern intersecting portions were orthogonal to each other as in this example, the facet size in the epitaxial layer was small, and a substrate with good flatness was obtained. Also, the stacking fault density near the SiO ₂ film of the epitaxial layer was reduced.
Then, in order to form a normal n-channel MOSFET, a gate oxide film 6 having a thickness of 200 Å is formed, and then boron is ion-implanted at an acceleration energy of 30 keV to 1.5 × 10 ¹² cm ^-2 .
After implanting 2 × 10 ¹² cm ² at 100 keV, then depositing 4500 Å of polycrystalline silicon by the low pressure CVD method and forming the gate electrode 7 by reactive ion etching, the structure of FIG. 1 (e) is obtained. Then arsenic was accelerated to 150 keV and 5 × 10 ¹⁵ cm
^-2 ion implantation is performed to form a high concentration n-type layer 8, and then phosphorus is diffused into the polysilicon gate electrode. Next, CVD SiO ₂
Deposit film 10, open contact holes, dashed aluminum line 11
Then, the n-channel MOS FE as shown in FIG.
You get T.

As described above, according to this example, the size of the facets during the epitaxial growth was reduced, and the flatness was improved. Further, since the stacking fault density of the epitaxial growth layer is reduced, the manufacturing yield when a device such as an n-channel MOS FET is manufactured is improved.

<Effects of the Invention> By using the present invention, it is possible to prevent the rounding of the intersection portion due to the proximity effect at the time of exposure and to form a fine pattern having a square shape.

[Brief description of drawings]

FIG. 1 is a diagram showing a cross-sectional structure or a planar structure step by step in a MOSFET manufacturing method according to an embodiment of the present invention.
(A), (b), (c), (d), (e), and (f) are sectional views, and (g '), (h'), and (i ') are plan views. FIGS. 2A and 2B are schematic plan views showing transfer changes between the reticle pattern and the resist pattern using the conventional method. In the figure, 1 ... Silicon substrate, 2 ... Silicon oxide film 3 ... Polycrystalline silicon film pattern (first mask) 4 ... Organic film pattern (second mask) 5 ... Epitaxial silicon layer 6 ... Gate Oxide film, 7 ... Gate electrode 8 ... High-concentration n-type layer, 9 ... CVDSiO ₂ film 10 ... Aluminum wiring 21 ... Reticle pattern 22 ... Resist pattern

Claims (1)

[Claims] 1. A mask pattern is formed on a substrate or a film deposited on the substrate by using an exposure technique, and the substrate not covered by the mask pattern or the film deposited on the substrate is anisotropically etched. In the pattern forming method, first, a linear pattern is formed by a first mask material, then a linear pattern made of a second mask material that intersects with the linear pattern is formed, and then the substrate or a film deposited on the substrate. Is anisotropically etched to form a cross pattern.