JPH08214445A - Circuit breaker - Google Patents

Abstract

PURPOSE: To eliminate the variation in eddy current tripping characteristics owing to variation in the secondary output characteristics of a current transformer for improved noise resistance, by comparing a sampling-value with a characteristic curve predetermined according to the type rated current of the current transformer, and determining its rate to the rated current and thus its level. CONSTITUTION: When a voltage signal corresponding to load current is sampled through an analog-to-digital conversion circuit 36, the digital voltage signal is compared with a characteristic curve predetermined according to the type and rated current of current transformers 25a, 25b, 25c. Its rate to the rated current is determined from the characteristic curve. If the characteristic curve deviates from a theoretical characteristic curve, then dummy data equivalent to the rate is validated as a sampling value. Further, the same determining means is also used in a maximum phase selecting means. This eliminates the variation in eddy current tripping characteristics owing to the variation in current transformers 25a, 25b, 25c, and improves noise characteristics.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit breaker which performs a trip operation of opening a main circuit contact when a fault current is detected.

[0002]

2. Description of the Related Art In a conventional circuit breaker, when a tripping operation for opening a main circuit contact is performed, a load current is detected by a current transformer provided in the main circuit and the output signal thereof is used. ing. That is, the current transformers are respectively arranged in the plurality of AC electric circuits forming the main circuit, and the output terminals of these current transformers are connected to the input terminals of the current detection circuit. This current detection circuit is configured to include a full-wave rectification circuit that full-wave rectifies the current of each phase detected by the current transformer and converts it into an analog voltage, a resistor, and the like, and has a level according to the current value of each phase. Outputs the analog voltage value of each phase. The output terminal of the current detection circuit is connected to an input port of a microcomputer as a control means through an analog-digital (AD) conversion circuit, and the output port of the microcomputer is connected to a thyristor for driving the trip device. It is connected to the gate.

In the circuit breaker configured as described above, the output signal of the current transformer of each phase is sampled at a certain sampling period and AD converted. Then, the microcomputer calculates the effective value for each phase by the microcomputer and selects the maximum phase. After that, if the microcomputer determines that the current is an overcurrent based on the detected value of the maximum phase, a tripping operation signal is output from the output port of the microcomputer and the tripping device is driven through the gate of the thyristor. An opening operation of the main circuit contact, that is, a tripping operation is performed.

[0004]

The circuit breaker having the above-mentioned conventional structure, however, has a problem that it is easily influenced by the secondary output characteristic of the current transformer. That is, the overcurrent characteristic changes due to the variation in the secondary output characteristic of the current transformer, and therefore, even if the same current is applied to the same product, there is a problem that there is a time lag in the tripping operation. In addition, the wrong signal such as noise may cause the microcomputer to judge that the signal is normal, and the trip operation may be performed.

The present invention has been made to solve the above problems, and an object thereof is to eliminate the change in the overcurrent trip characteristic due to the variation in the secondary output characteristic of the current transformer. Another object of the present invention is to provide a circuit breaker capable of eliminating malfunction due to noise or the like.

[0006]

In order to achieve the above object, the present invention provides a current detecting means including a current transformer for detecting load currents flowing in a plurality of alternating current circuits, and a detection output by the current detecting means. Circuit for converting the signal into a signal having a level corresponding to the load current, an A-D conversion circuit for sampling the signal from the burden circuit at a constant cycle, and an arithmetic process based on the sampling value by the A-D conversion circuit. A circuit breaker including a processing unit that outputs a signal for operating the circuit breaker, the model of the current transformer when the processing unit is the signal sampling by the AD converter. And a first judging means for judging the sampling value by judging the ratio to the rated current by comparing with a preset characteristic curve by the rated current. The square calculation means for squaring the sampling value of each phase validated by the first judging means, and the first squaring means for accumulating the calculation result of the sampling value for each phase for each constant period. The addition means, the counting means for counting the number of times of accumulation by the first addition means, and the maximum of the accumulated data for each phase by the first addition means when the counting means reaches the set count value , A division means for dividing the accumulated data selected by the maximum phase selection means by the set count value, and whether the division result of the division means has reached a predetermined operation level. Second determining means for determining whether or not;
Second addition means for accumulating the division result of the division means at constant intervals when the second determination means determines that the division result has reached a predetermined operation level; and the second addition means. Third judging means for judging whether or not the cumulative result of the means exceeds a predetermined value, and output means for outputting a signal for operating the circuit breaker based on the judgment result by the third judging means. It is configured to include (Claim 1).

In this case, the maximum phase selecting means may determine the sampling value compared with the characteristic curve as an appropriate state. (Claim 2) Furthermore, when the difference between the characteristic curve and the sampling value is equal to or greater than the limit value, the first determining means may use the simulated data as the sampling value (Claim 3).

[0008]

According to the means described in claim 1, the A-D conversion circuit samples the signal of the level detected by the current detecting means and corresponding to the load current at a constant cycle, and the arithmetic processing means performs the sampling. The arithmetic processing based on such a sampling value is performed.

[0009] In this case, the arithmetic processing means, at the time of signal sampling by the A / D converter circuit, compares with a preset characteristic curve depending on the model of the current transformer and the rated current to determine the ratio to the rated current. Then, the level of the sampling value is determined, and the simulated data of the level is validated as the sampling value.

By carrying out such arithmetic processing, the adverse effect due to the superimposed noise of the current transformer is eliminated. Further, the arithmetic processing means squares the sampling values of the respective phases validated in this way, and accumulates the squared values of the square values corresponding to the respective phases at constant intervals. When the maximum value is selected from the accumulated data for each phase of the square value when the set count value is reached, the accumulated data thus selected is divided by the set count value,
When this division result reaches a predetermined level, the division result is accumulated at constant intervals, and when this accumulation result exceeds a predetermined value, a signal for operating the circuit breaker is output. The tripping operation is performed. Therefore, the arithmetic processing for the tripping operation can be performed only by the digital voltage signal.

According to the second aspect of the present invention, during the arithmetic processing as described above, the maximum phase selecting means also compares the characteristic curve with the sampling value to make the sampling value accurate. You can

According to the means described in claim 3, when the difference between the comparison value and the actual sampling value is more than the limit during the arithmetic processing, simulated data is added to the sampling value.
The sampling value can be made accurate by using it as the sampling value.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. In FIG. 1, which shows an outline of the entire electrical configuration, power supply side terminals 21a, 21b, 21
c is connected to a three-phase AC power source composed of A, B, and C phases, and these are connected to the main circuit contacts 22a, 22b, and 2, respectively.
2c and main circuit conductors 23a, 23b, 23 that are AC electric circuits
It is connected to the load side terminals 24a, 24b, 24c via c.

The current transformers 25a, 25b and 25c use the main circuit conductors 23a, 23b and 23c of the respective phases A, B and C as primary side conductors, and their secondary outputs are the rectifier circuits 26a and 26a. Full-wave rectification is performed by 26b and 26c. At this time, the negative output terminals of the rectifier circuits 26a, 26b, and 26c are commonly connected to the line 27, and the positive output terminals are connected to the lines 28a, 28b, and 28c, respectively.

The burden circuits 29a, 29b, 29c are for converting the output currents of the rectifier circuits 26a, 26b, 26c into analog voltage signals for each phase, and these are the above-mentioned lines as shown in FIG. Resistors R1, R2, R are respectively provided between 28a, 28b, 28c and a power supply circuit 30 described later.
It is configured by connecting three.

Therefore, the analog voltage signals Va, Vb, Vc corresponding to the voltage drop at the resistors R1, R2, R3 are output to the lines 28a, 28b, 28c, respectively, and the analog voltage signals Va, Vb, The voltage level of Vc depends on the load current values Ia, Ib, and Ic of each phase.
That is, the current transformers 25a to 25c and the rectifier circuit 2 described above.
6a to 26c and the burden circuits 29a to 29c constitute a current detecting means 31 for detecting the load currents of the A, B, and C phases flowing in the main circuit conductors 23a, 23b, and 23c.

The analog voltage signals Va, Vb, Vc for each phase output from the above current detecting means 31 to the lines 28a, 28b, 28c, respectively, are supplied to the diode 32.
The signal is supplied to the line 33 through the diode OR circuit 32 including a, 32b and 32c, and the signal selecting means 3 is provided.
4 are given.

The signal selecting means 34 repeatedly executes a selecting operation of selectively passing the analog voltage signals Va, Vb, Vc in a predetermined order based on an operation command signal from the outside. The specific configuration will be described later. The specific configuration of the differential amplifier circuit 35 for amplifying the output of the signal selection means 34 will also be described later.

The A / D conversion circuit 36 is a differential amplifier circuit 35.
Output (that is, a voltage signal corresponding to the analog voltage signals Va, Vb, and Vc) is digitally converted, and the converted output is a microcomputer 37 which is an arithmetic means.
Given to.

This microcomputer 37 is AD
The control circuit 36 controls the conversion operation of the conversion circuit 36 and also controls the tripping operation of opening the main circuit contacts 22a to 22c based on the load current value indicated by the input digital voltage signal. Port P _O is connected to the gate of thyristor 38. The microphone computer 37 is also configured to control the signal selecting means 34, and an operation command signal S for operating the signal selecting means 34 from its output port P _1.
A, Sb, and Sc are periodically output as described later.

The thyristor 38 has its anode connected to the line 33 via a release type trip device 39, and its cathode connected to the line 27. The trip device 39 is configured to open the main circuit contacts 22a, 22b, 22c via a trip mechanism (not shown) when energized in response to the thyristor 38 being turned on.

The time-limit control circuit 40 is connected between the line 33 and the line 27 via a constant voltage diode 41 having the polarity shown in the figure. The trigger pulse is output after the time limit corresponding to the magnitude of the applied voltage elapses and is given to the gate of the thyristor 38.

The signal selection means 34 and the A / D conversion circuit 3
6 and the microcomputer 37 and other power sources are obtained from the power source circuit 30. FIG. 2 shows a concrete configuration example of the signal selecting means 34 and the differential amplifier circuit 35 together with related circuits, which will be described below. That is, as described above, the burden circuits 29a, 29
The resistors R1, R2, and R3 that form b and 29c are connected between the lines 28a, 28b, and 28c and the power supply circuit 30. The power supply circuit 30 outputs an analog ground voltage to a line 42 connected to the power supply circuit 30. A positive voltage is applied between the line 42 and a line 43 to which the resistors R1, R2, and R3 are commonly connected. It is configured as a dual power supply type that outputs a negative voltage between the line 42 and the line 27 while outputting the same.

In the signal selecting means 34, the input side terminals of the analog switches 44a, 44b and 44c are connected to the lines 28a, 28b, and the lines 28a, 28b, via resistors R4, R5, R6, respectively.
28c, and each output side terminal is commonly connected to the line 45. At this time, the line 45 is connected to the analog ground potential line 42 via the resistor R7, and the noise absorbing capacitor C1 is connected in parallel to the resistor R7.

The analog switches 44a, 44b,
The gate terminal 44c receives the operation command signals Sa, Sb, Sc from the microcomputer 37 at its gate terminal, and becomes conductive in the signal input state. Further, in the signal selecting means 34, the respective anodes of the diodes D1, D2 and D3 for preventing the application of the excessive voltage when the analog switches 44a, 44b and 44c are turned off are connected to the respective input terminals. The cathodes of the diodes D1, D2 and D3 are commonly connected to the line 43.

On the other hand, in the differential amplifier circuit 35, the operational amplifier 46 fed from the lines 43 and 27 has its non-inverting input terminal (+) connected to the line 45, and its inverting input terminal (-) is a resistor. Line 43 via R8
It is connected to the. Further, a parallel circuit of a feedback resistor R9 and a noise absorbing capacitor C2 is connected between the output terminal of the operational amplifier 46 and the inverting input terminal (−). Further, the output terminal of the operational amplifier 46 is connected to the AD conversion circuit 36.
Of the input terminal AD. In this case, when the resistance values of the resistors R4 to R9 are represented by the symbols, the resistance values are R4 = R5 = R6 = R8 = Ra, R7.
= R9 = Rb.

The operation of the above configuration will be described together with the control contents of the microcomputer 37. In the state where the load current flows through the main circuit conductors 23a, 23b, 23c,
Analog voltage signal V on lines 28a, 28b, 28c
Since a, Vb, and Vc are output, the power supply circuit 30 functions and the signal selection means 34, the differential amplifier circuit 35,
Power is supplied to the A-D conversion circuit 36 and the microcomputer 37.

In such a power-on state, the main circuit conductor 2
When a small-scale fault current that does not result in a short-circuit fault flows through 3a, 23b, and 23c, the following action occurs. That is,
From the current detection means 31 to the lines 28a, 28b, 28c, analog voltage signals Va, V having voltage levels corresponding to the load current values Ia, Ib, Ic of the respective phases A, B, C.
b, Vc are output, and these voltage signals V
As is well known, the waveforms of a, Vb, and Vc are absolute value waveforms. Here, the power supply circuit 30 causes the lines 43 and 42 to
When the voltage output between them is Vz, Va, Vb, V
c is represented by the following equation.

Va = R1 · Ia + Vz Vb = R2 · 1b + Vz Vc = R3 · Ic + Vz On the other hand, the microcomputer 37 repeats the operation command signals Sa, Sb, Sc in this order in a predetermined cycle in a time-division manner as described later. It is output and given to the signal selecting means 34. Therefore, during the period when the operation command signal Sa is output, the analog switch 44a becomes conductive, and the analog voltage signal Va output to the line 28a is transmitted to the differential amplifier circuit 35 via the resistor R4, the analog switch 44a, and the line 45.
Is applied to the non-inverting input terminal (+) of the operational amplifier 46 inside.

Further, during each period when the operation command signals Sb and Sc are output, the analog voltage signals Vb and Vc output to the lines 28b and 28c are respectively applied to the resistor R5 in accordance with the conduction of the analog switches 4b and 44c. , Analog switch 44b, line 45 or resistor R6, analog switch 44c, line 45 to the non-inverting input terminal (+) of the operational amplifier 46.

At this time, since the line 45 is connected to the analog ground potential line 42 through the resistor R7, the analog switch 44 is connected as described above.
The analog voltage signals V'a, V'b, V'c given to the non-inverting input terminal (+) of the operational amplifier 46 according to the conduction of a, 44b, 44c are given by the following equations. However, in the following equation, Vo is the potential of the line 42 (analog ground potential).

V′a = (R1 · Ia + Vz−Vo) R7 / (R4 + R7) V′b = (R2 · Ib + Vz−Vo) R7 / (R5 + R7) V′c = (R3 · Ic + Vz−Vo) R7 / (R6 + R7) ) Then, to the inverting input terminal (-) of the operational amplifier 46, a voltage having a value indicated by (Vz-Vo) is applied from the line 43 to the operational amplifier 46 via the resistor R8, and the non-inverting input terminal (+) thereof is supplied. On the other hand, the analog voltage signals V'a and V '
Since either b or V'c is input, the amplified output voltage of the operational amplifier 46 is obtained by the following equation. However, in the following, analog voltage signals V'a, V'b, V '
The amplified output voltage of the operational amplifier 46 in each case where c is input will be represented as Vxa, Vxb, and Vxc, respectively.

Vxa = V′a (R8 + R9) / R8− (Vz−Vo) R9 / R8 Vxb = V′b (R8 + R9) / R8− (Vz−Vo) R9 / R8 Vxc = V′c (R8 + R9) / R8- (Vz-Vo) R9 / R8 Here, because R4 = R5 = R6 = R8 = Ra and R7 = R9 = Rb are set, V'a, V
′ B, V′c and Vxa, Vxb, Vxc are respectively obtained by the following equations.

V′a = (R1 · Ia + Vz−Vo) Rb / (Ra + Rb) V′b = (R2 · Ib + Vz−Vo) Rb / (Ra + Rb) V′c = (R3 · Ic + Vz−Vo) Rb / (Ra + Rb) ) Vxa = V'a (Ra + Rb) / Ra- (Vz-Vo) Rb / Ra = Ia.R1.Rb / Ra Vxb = V'b (Ra + Rb) / Ra- (Vz-Vo) Rb / Ra = Ib. R2.Rb / Ra Vxc = V'c (Ra + Rb) / Ra- (Vz-Vo) Rb / Ra = Ic.R3.Rb / Ra As described above, the microcomputer 37 controls the signal selecting means 34. As a result, the differential amplifier circuit 35
From the output terminal of each of the load current values Ia, I of the phases A, B, C
b, an analog voltage signal Vx having a voltage level proportional to Ic
It is possible to take out a, Vxb, and Vxc periodically. In this case, if the resistors R1, R2, R3 forming the burden circuits 29a, 29b, 29c are set equal, the analog voltage signals Vxa, Vxb, Vxc can be compared with the same reference.

The microcomputer 37 uses the signal selection means 34 based on such operation command signals Sa, Sb, Sc.
Simultaneously with the time-division control of No. 3, the A-D conversion circuit 36 is also time-division controlled. Therefore, the A-D conversion circuit 36
Are analog voltage signals Vxa and Vx obtained as described above.
xb and Vxc are sampled at a constant cycle. That is, the A / D conversion circuit 36 includes the burden circuit 29a,
The analog voltage signals from 29b and 29c are sampled at a constant cycle and converted into a digital voltage signal, and the digital voltage signal (corresponding to the sampling value in the present invention) is input to the microcomputer 37.

At this time, the microcomputer 37 selects the maximum load current among the load currents indicated by the digital voltage signal based on a preset program, calculates the effective value thereof, and indicates the effective value. The determination of the level of each phase load current value is performed, and the contents of these calculations will be described later with reference to FIG.

Further, the microcomputer 37 detects the presence or absence of a fault current based on the level discrimination result, and when it detects that the fault current has flown, it performs a time-delayed operation according to the magnitude of the fault current. After that, a trigger pulse is output from the output port P _O. Then, the thyristor 38 which receives the trigger pulse at its gate is turned on and the tripping device 39 is energized, so that the normal tripping operation of opening the main circuit contacts 22a, 22b, 22c is performed. .

On the other hand, the main circuit conductors 23a, 23
When a large-scale fault current such as a short-circuit current flows in b and 23c, it operates as follows. That is, in this case, since the voltage levels of the analog voltage signals Va, Vb, Vc output from the current detection means 31 to the lines 28a, 28b, 28c suddenly rise, the voltage between the line 33 and the line 27 is also diode-ORed. The voltage rises through 32 and exceeds the Zener voltage of the constant voltage diode 41.

Then, the constant voltage diode 41 breaks down and the time limit control circuit 40 is energized. Therefore, the time limit control circuit 40 outputs a predetermined time limit corresponding to the magnitude of the applied voltage (ie, load current value). A trigger pulse is output after a lapse of time. Therefore, the trigger pulse causes the thyristor 38 to be turned on, and the trip device 39 causes the main circuit contacts 22a, 22b, 22c to be turned on.
The instantaneous tripping operation is performed to open the.

Now, FIG. 3 shows a microcomputer 37.
The operation contents of the above are shown and will be described below together with related operations. In FIG. 3, first, after executing the initialization step a corresponding to the power-on of the microcomputer 37, the variable K is set to the initial value “1” (step b). Then, in step c, the signal selection means 34
In response to the operation command signal Sa, the digital conversion start command is output to the A / D conversion circuit 36. Then, the signal selecting means 34 causes the A-phase analog voltage signal Va.
And the voltage signal Va is converted by the A / D conversion circuit 36 into digital data Ak indicating the A phase digital voltage signal (corresponding to the sampling value in the present invention).
Is converted to.

Next, in step d, the characteristic curve set from the measured digital data Ak converted as described above and the current transformer model and rated current as shown in FIG. All the ratios are compared, and if the ratio is equal to the simulated data with respect to the ratio, the measured digital data Ak is determined to be an appropriate value.

When it is judged "YES" in step d (that is, when the digital data Ak is proper), the process directly proceeds to step f,
In the case of "NO" (when the digital data Ak is improper), in step e, the simulated data A
k ′ is validated as the measured digital data Ak, and then the process proceeds to step f. The steps d and e correspond to the first determining means in the present invention.

In the step f corresponding to the square calculation means, the digital data A validated as described above is used.
A squared operation of k is performed, and the operation result value Ak ² is stored as data Dk. Further, in the next step g (corresponding to the first adding means), the digital data Dk (= Ak ² ) stored as described above is accumulated in the accumulation memory data Ek. After that, the above steps c to g are repeated in a constant cycle until it is determined as “YES” in step s, which will be described later. Therefore, the above-described square calculation and accumulation are performed in a constant cycle. Done.

Thereafter, in step h, the operation command signal Sb is output to the signal selecting means 34, and
A digital conversion start command is output to the A / D conversion circuit 36. Therefore, in this case, the B-phase analog voltage signal Vb passes through the signal selection means 34 and the AD conversion circuit 36.
Is converted into digital data Bk indicating a B-phase digital voltage signal (corresponding to the sampling value in the present invention).

Next, in step i, referring to the measured digital data Bk converted as described above and the characteristic curve set from the model of the current transformer and the rated current as shown in FIG. Are compared, and the measured digital data Bk is determined to be an appropriate value if it is equal to the simulated data with respect to the ratio.

When it is judged "YES" in the above step i (that is, when the digital data Bk is proper), the process directly proceeds to step k,
In the case of "NO" (when the digital data Bk is improper), in step j, the simulated data B
k ′ is validated as the measured digital data Bk, and then the process proceeds to step k. The steps i and j correspond to the first determining means in the present invention.

In the step k corresponding to the square calculation means, the square calculation of the digital data Bk is performed, the calculation result value Bk ² is stored as the data Fk, and the step 1 corresponding to the first addition means is performed. , The data Fk (= Bk ² ) stored as described above
Is added to the accumulation memory data Gk. Also in this case, the above-described square calculation and accumulation are performed at regular intervals.

Subsequently, at step m, the operation command signal Sc is outputted to the signal selecting means 34 and A-
A digital conversion start command is output to the D conversion circuit 36. Therefore, in this case, the C-phase analog voltage signal V
c passes through the signal selecting means 34, and the A-D conversion circuit 36 causes digital data C indicating a digital voltage signal for the C phase.
converted to k.

Next, in step m, the measured digital data Ck converted as described above and the characteristic curve set from the model of the current transformer and the rated current as shown in FIG. The ratio is compared, and if the ratio is equal to the simulated data for the ratio, the measured digital data Ck is determined to be an appropriate value. When it is determined to be “YES” in step m (that is, the digital data C
If k is appropriate), the process directly proceeds to step P. If “NO” (when the digital data Ck is incorrect), in step o,
The simulated data Ck 'is validated as the actually measured digital data Ck, and thereafter, the process proceeds to step p. The steps m and o correspond to the first determining means in the present invention.

In the step p corresponding to the square calculation means, the square calculation of the digital data Ck represented by the digital voltage signal is performed and the calculation result value C is obtained.
k ² is stored as the data Hk, and the data Hk (= Ck ² ) stored as described above is stored in the accumulation memory data I in step q corresponding to the first adding means.
Add to k. Also in this case, the above-described square calculation and accumulation are performed at regular intervals.

After this, in step s, the variable K
Has reached the set count value N, and if "NO", step r (corresponding to counting means) for incrementing the variable K by "1" is executed and then the process returns to step c. In this case, if the cycle of one cycle in steps c to q is t ₀ , “YE
The required time T until it is judged as "S" is T = N · t ₀ , so N in steps g, l, and q is N = T / t _0.
Is represented by

If "YES" is determined in the above step s, that is, steps c to q are executed N times and each phase digital data Dk (= Ak ² ), Fk (= Bk ² ), Hk.
(= Ck ² ) is sampled N times, and when the respective accumulated data Ek, Gk, Ik are obtained, in step t corresponding to the maximum phase selecting means, the accumulated data for each of the above phases is obtained. Select the largest of Ek, Gk, Ik,
This is stored as maximum value data Jk. Next, in step u corresponding to the dividing means, the maximum value data Jk is divided by the set count value N, and the division result Jk / N (= Jk · t0 / T) is stored as the division data Lk.

Thereafter, in step v corresponding to the second judging means, it is judged whether or not the division data Lk has reached the overcurrent operation level. This step v
When "YES" is obtained in step S11, the division data Lk is accumulated in the accumulation memory data Mk in step x corresponding to the second adding means. In step v, "N
When it becomes "O", in step w, the division data Lk is subtracted from the accumulation memory data Mk. Such steps x and w are followed by “YE
It is repeated in a constant cycle until it is judged as "S", and therefore the accumulation or subtraction as described above is performed in a constant cycle.

The above step y corresponding to the third judging means.
Then, it is determined whether or not the cumulative memory data Mk exceeds a predetermined value P. When "YES", step z (corresponding to the output means) for outputting a trigger pulse from the output port P0 is executed. The calculation operation ends. Therefore, at the end of such arithmetic operation, the above-mentioned tripping operation is performed by the trigger pulse. In step y, "N
When it becomes "O", the process returns to the step b, and the following steps are repeated as described above.

Here, generally, the protection characteristic of the circuit breaker is set as shown in FIG. That is, when the load current value exceeds the overcurrent operation level, the long time delay operation, the short time delay operation, and the instantaneous operation are executed according to the magnitude of the load current. In particular, in the long-time operation region corresponding to the overcurrent protection operation performed by the microcomputer 37 of this embodiment, the operation time is inversely proportional to the square of the load current value due to the arithmetic processing as shown in FIG. It is set to the time delay characteristic. That is, in the long-time operation region, operation is performed such that (load current) ² × (operation time) = constant value.

As described above, according to this embodiment, since the overcurrent protection operation having the anti-time limit characteristic is performed by the digital calculation, the troublesomeness required in the conventional configuration in which the analog circuit elements are combined is required. It is possible to reduce the number of required analog circuit elements, and to simplify the circuit configuration and suppress the manufacturing cost.

In particular, in this embodiment, when the A-D conversion circuit 36 samples the voltage signal according to the load current, the digital voltage signal (digital data Ak, Bk, Ck) as the sampling result is converted into The characteristic curve is a theoretical characteristic curve in which the ratio of the current transformers 25a, 25b, 25c to the rated current is compared with a preset characteristic curve, and the ratio to the rated current is determined from the characteristic curve. If it deviates more, the simplification data corresponding to the ratio to the rated current is simply validated as the sampling value, and the maximum phase selection means can also use the same determination means, The following effects can be achieved.

That is, the load current I is the main circuit conductors 23a, 2
3b, 23c, current transformers 25a, 25b, 2
The secondary output "V2" is generated through 5c, and the rectifier circuit 26
a, 26b, 26c, burden circuits 29a, 29b, 29
c, the signal selection means 34, and the A / D conversion circuit 36 to be input to the arithmetic processing means. In this case, the current transformer 25a,
If the secondary output characteristics of 25b and 25c are the theoretical characteristic curve "A" of the characteristic curve shown in FIG. 5, the sampling value is processed as it is. For example, 100A of 15A current transformers 25a, 25b and 26c. In the case where the load current I ₁ flows 200% in the characteristic curve of “E”, the rectifier circuits 26a, 26b, 26c and the burden circuits 29a, 29
The secondary output voltage "V2E" is output from b, 29c, the signal selection means 34, and the AD conversion circuit 36. In this case, this output is the secondary output voltage "V2" in the theoretical characteristic curve "A".
Since it is "A", there is a difference of V2E-V2A, and if this difference exceeds a certain limit, "V2A" is validated as the simulated data for the sampling value. Therefore, the current transformers 25a, 25a
Even if there are variations in the secondary output characteristics of b and 25c, the current transformer 2 is determined because it is judged based on the theoretical characteristic curve "A".
It is possible to eliminate the change in the overcurrent trip characteristic due to the variations in 5a, 25b, and 25c. The same applies when the characteristic curves of the current transformer are "B", "C", and "D".

Even when an erroneous signal due to superimposed noise is detected, as shown in FIG. 6, for example, "F1"
When the sample data of is detected and the sampled value is not on the preset characteristic curve “A”, it is judged from the past data “FA” until the sampling, and the simulated data “FA ′” As a result, by replacing them and moving to the next calculation means, it is possible to obtain a stable tripping operation which is hardly affected by the superposed noise or the like.

In the above embodiment, when the voltage signal corresponding to the load current is sampled, it is compared with a preset characteristic curve and the ratio to the rated current is judged to judge the sampling value. However,
Also in the maximum phase selection means, by adopting the same means as described above, the sampling value can be made more accurate.

Even if the characteristic curves of the current transformers 25a, 25b, 25c are changed due to problems in manufacturing and assembly, similar characteristic curves can be obtained by storing several kinds of expected characteristic curves. It is possible to make a configuration that can be changed by selecting by switching.

Further, the present invention is not limited to the above-mentioned embodiments, and various modifications may be made without departing from the scope of the invention, for example, the signal processing circuit may be realized by a digital circuit formed by combining discrete circuits. Can be carried out.

[0063]

According to the present invention, as is clear from the above description, the sampling value from the A / D conversion circuit is compared with a preset characteristic curve depending on the model of the current transformer and the rated current. However, since the sampling value is determined by determining the ratio to the rated current, the change in the characteristics due to the current transformer and variations due to the tripping operation by the circuit breaker is eliminated. The noise resistance can be improved.

[Brief description of drawings]

FIG. 1 is an overall schematic circuit configuration diagram in an embodiment of the present invention.

FIG. 2 is a circuit configuration diagram showing a part of FIG. 2 in detail.

FIG. 3 is a flowchart showing the control contents of the main part in one embodiment of the present invention.

[Fig. 4] Protection characteristic curve diagram

FIG. 5: Output characteristic curve diagram

FIG. 6 Output characteristic curve diagram

[Explanation of symbols]

In the drawing, 22a, 22b and 22c are main circuit contacts, and 23
a, 23b and 23c are main circuit conductors (AC circuit), 25
a, 25b, 25c are current transformers, 26a, 26b, 26c
Is a rectifier circuit, 29a, 29b and 29c are burden circuits, 30
Is a power supply circuit, 31 is current detection means, 34 is signal selection means, 35 is a differential amplifier circuit, 36 is an AD conversion circuit, 37
Is a microcomputer (arithmetic processing means), 38 is a thyristor, and 39 is a trip device.

Claims (3)

[Claims] 1. A current detecting means including a current transformer for detecting load currents flowing through a plurality of alternating current circuits, and a burden circuit for converting a detection output of the current detecting means into a signal having a level corresponding to the load currents. , An A-D conversion circuit for sampling the signal from the burden circuit at a constant cycle, and an operation for performing a calculation process based on the sampling value by the A-D conversion circuit to output a signal for operating the circuit breaker In the circuit breaker including a processing means, the arithmetic processing means compares a preset characteristic curve depending on a model of the current transformer and a rated current at the time of signal sampling by the AD conversion circuit, and The first to judge the sampling value by judging the ratio to the current
Determining means, and a square calculating means for squaring the sampling values of each phase validated by the first determining means.
First adding means for accumulating the calculation result of the sampling value for each phase by the squaring means for each constant period, counting means for counting the number of times of accumulation by the first adding means, and this counting Maximum phase selecting means for selecting the maximum of the accumulated data for each phase by the first adding means when the means has reached the set count value, and the accumulated data selected by this maximum phase selecting means Is divided by the set count value, a second judgment means for judging whether or not the division result of the division means has reached a predetermined operation level, and the division result by the second judgment means. Second addition means for accumulating the division result of the division means at a constant cycle when it is determined that the predetermined operation level is reached, and whether the accumulation result of the second addition means exceeds a predetermined value Third judgment to judge whether Stage and, circuit breaker characterized in that it is configured to include an output means for outputting a signal for operating the circuit breaker based on the determination result by the third determining means. 2. In the selection of the maximum phase by the maximum phase selection means, the sampling value is compared with a preset characteristic curve depending on the model of the current transformer and the rated current to determine the ratio to the rated current. The circuit breaker according to claim 1, wherein the circuit breaker is configured to be used as a sampling value. 3. The first determining means included in the arithmetic processing means is configured to use the simulated data as the sampling value when the difference between the sampling value and the characteristic curve is equal to or more than the limit value. The circuit breaker according to claim 1 or 2.