JPH08213582A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PURPOSE: To enable the full display of the functions of a buried region formed on a semiconductor substrate, simplify the production process and reduce the man-hours. CONSTITUTION: A transfer channel region 14, a gate insulation film 18 and a transfer electrode 19 are formed on a silicon substrate 11 to fabricate a vertical transfer register 2, then a p-type impurity (B), for example, is implanted by a high energy ion implantation through the electrodes 19 and diffused to form buried well regions 12 which form overflow barriers against signal charges, and n-type impurity diffused regions 13 and p-type hole storage regions 16 are formed with the electrodes 19 used as a mask in a portion to form a photodetecting part 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a buried region formed by diffusing introduced impurities inside a semiconductor substrate and a method of manufacturing the same, and more particularly to a light receiving portion and its peripheral portion in a solid-state image sensor. It is suitable for application to the structure.

[0002]

2. Description of the Related Art Generally, as a case of forming a buried region in a semiconductor substrate, for example, a purpose is to reduce collector resistance in a vertical pnp transistor or a vertical npn transistor, or a signal charge is formed under a light receiving portion in a solid-state image sensor. A potential barrier (overflow barrier) is formed to suppress blooming and smear.

Conventionally, when a buried region is formed in a semiconductor substrate, as shown in FIG.
01, for example, before forming a gate insulating film or an oxide film by the LOCOS method, first, a thin oxide film 102 for ion implantation is formed on the substrate, and then impurities are ion-implanted by, for example, high energy. The substrate 10 is introduced into the substrate 101, and thereafter activated by heat treatment to
An impurity diffusion region (embedded region) 103 due to the introduced impurities is formed in the first region 1.

In the case of forming a solid-state image sensor, for example, as shown in FIG. 8, after the above steps, a necessary CCD, for example, n-type and p-type impurities (phosphorus (P ) And boron (B)) are introduced by, for example, ion implantation, film diffusion, etc., and activated by heat treatment, and the buried region 103 in the silicon substrate 101.
On the surface side of the n-type transfer channel region 104, the p-type channel stopper region 15 and the second p-type well region 10.
6 is formed.

After that, after forming a gate insulating film 107 made of, for example, SiO ₂ on the transfer channel region 104, a transfer electrode 108 made of a polycrystalline silicon layer is formed,
Then, thermal oxidation is performed to form a thin thermal oxide film (SiO ₂ film) 109 on the surface of the transfer electrode 108.

After that, an n-type impurity such as phosphorus (P) is ion-implanted into the surface of the silicon substrate 101 using the transfer electrode 108 as a mask, and further activated, and an n-type impurity diffusion region is formed on the surface of the silicon substrate 101. 110 is formed. At this time, a light receiving portion (photodiode) 111 is formed by a pn junction between the n-type impurity diffusion region 110 and the buried region 103. After the formation of the light receiving portion 111, a p-type impurity such as boron (B) is ion-implanted again using the transfer electrode 108 as a mask, and further activated to p-type positive impurity on the surface of the n-type impurity diffusion region 110. The hole accumulation region 112 is formed.

After that, a PSG film 113 which is an interlayer insulating film is deposited on the entire surface by, eg, CVD method. After that, an Al light-shielding film 114 is formed on the entire surface, and then the Al light-shielding film 1 is formed by RIE (reactive ion etching) in the vertical mode, for example.
14 is patterned to form the light receiving portion opening 114a.

Then, a silicon nitride film 115 for surface protection is formed by CVD, for example, on the entire surface including the Al light-shielding film 114. This silicon nitride film 115 and the PSG of the lower layer
The film 113 constitutes a passivation film on the light receiving portion 111. By going through the above manufacturing process,
A conventional solid-state image sensor will be manufactured. It should be noted that the transfer channel region 104 and the transfer electrode 108 form a vertical transfer register unit VR.
The read gate portion RG is formed by a p-type region existing between the light receiving portion and the light receiving portion.

[0009]

By the way, in the conventional semiconductor device such as a solid-state imaging device having the above-mentioned buried region, when the buried region 103 is formed, as described above, the gate insulating film 107 or the gate insulating film 107 is formed on the substrate 101. Before forming the various wiring patterns 108 and the like, impurities are introduced into the substrate 101 only through the oxide film 102 for ion implantation (see FIG. 7) formed on the substrate 101 in advance, so that the substrate 101 The embedded region 103 is formed therein.

In this case, the formation position of the embedded region 103 is the same depth with respect to the surface direction of the substrate 101,
For example, regarding the solid-state image sensor, the embedded region 1
The overflow barrier formed by 03 is the same regardless of the functions of the functional units (light receiving unit 111, read gate unit RG, vertical transfer register unit VR, etc.) formed on the surface side of the substrate. The depth is not structurally superior.

Taking a solid-state image sensor as an example,
Conventionally, as described above, an impurity for forming a buried region is introduced into the substrate 101 by ion implantation with high energy before forming a functional structure such as the upper transfer electrode 108.

In this case, as shown in FIGS. 9 and 10,
The depth of the overflow barrier OB formed in the buried region 103 is constant within the wafer surface. However, heat is applied to the substrate 101 due to the formation of the transfer electrode 108,
Finally, the heat treatment applied to the substrate 101 takes a long time, and the potential gradient at the apex of the overflow barrier OB and its peripheral portion becomes gentle.

Normally, signal charges are accumulated in the light receiving portion 111 as light enters, but when the signal charges are accumulated at or near the apex of the overflow barrier OB, the potential gradient of the overflow barrier OB is increased. If it is gentle, the effective region of the light receiving unit 111 becomes small, the maximum accumulated charge amount decreases, and the potential barrier flows in the lateral direction (read gate RG side) where the height is lower,
As a result, there arises a problem that the incident light amount-dependent characteristic of the accumulated charge amount is deteriorated.

That is, when the potential gradient of the overflow barrier OB is gentle, the substrate 1 jumps over the overflow barrier OB due to the relationship of thermal kinetic energy.
The electric charges (electrons in this case) having a potential close to the potential (threshold value) that begins to overflow on the 01 side are accumulated in the light receiving portion 111 as they are or flow out in the lateral direction without flowing to the substrate 101 side. Become.

Therefore, in terms of photoelectric conversion characteristics, the knee (kne)
The charge in the non-linear characteristic region of point e) or higher is applied to the substrate 101.
It becomes difficult to overflow to the back side, and the dependency of the accumulated charge amount on the incident light amount with respect to the saturated light amount or more becomes poor, which causes deterioration of sensitivity.

On the other hand, in general, in a semiconductor device having a buried region 103, in order to improve individual characteristics in each functional portion, a potential barrier or a separate barrier is separately formed by selective impurity introduction (ion implantation) or diffusion plural times. The well region is formed.

As described above, in the conventional semiconductor device having the buried region in the semiconductor substrate, the function of the buried region formed in the semiconductor substrate cannot be sufficiently exerted, and in order to improve the function. A separate process is required, which may complicate the manufacturing process and increase the number of steps.

The present invention has been made in view of the above problems, and an object of the present invention is to make the function of an embedded region formed in a semiconductor substrate in each functional portion of a semiconductor element formed on the substrate. It is an object of the present invention to provide a semiconductor device which can be made compatible and can fully exhibit the function of the embedded region.

Another object of the present invention is to reduce the number of times impurities are introduced to improve the device characteristics of a semiconductor element formed on a semiconductor substrate, simplifying the manufacturing process and reducing the number of steps. It is to provide a semiconductor device capable of

Further, according to the present invention, the function of the buried region formed in the semiconductor substrate can be sufficiently exerted,
Moreover, it is an object of the present invention to provide a method for manufacturing a semiconductor device, which can simplify the manufacturing process and reduce the number of steps.

[0021]

A semiconductor device according to the present invention is configured so that a buried region formed in a semiconductor substrate in a plane direction has a change in a depth direction (the invention according to claim 1).

In this case, the embedded region may be configured to have a change in the depth direction corresponding to the device characteristics of the semiconductor element formed on the semiconductor substrate (the invention according to claim 2). .

In addition, a light receiving portion for photoelectrically converting incident light from an object into a signal charge in an amount corresponding to the amount of light in the embedded region during the accumulation period, and a charge for transferring the signal charge to an output side during the charge transfer period. A well region that functions as a potential barrier against the signal charge in a solid-state imaging device having a transfer section and a read gate section that transfers the signal charge accumulated in the light receiving section to the charge transfer section during a read period, and You may comprise so that a depth direction may differ corresponding to each part (invention of Claim 3).

In the semiconductor element, a light receiving portion for photoelectrically converting incident light from a subject into an amount of signal charge corresponding to the amount of light in a storage period, and a charge for transferring the signal charge to an output side in a charge transfer period. A solid-state imaging device having a transfer section and a read gate section that transfers the signal charge accumulated in the light receiving section to the charge transfer section during a read period, and the embedded region functions as a potential barrier against the signal charge. The well region may have a different depth direction corresponding to each portion (claim 4).
Invention described).

Further, the light receiving portion is configured to have at least a pn junction of the buried region forming the well region and a first conductivity type impurity diffusion region formed on the surface side from the buried region, The read gate portion is formed by another impurity diffusion region of the second conductivity type continuously formed on the surface side from the buried region, and the charge transfer portion is continuously formed on the surface from the buried region. It may be configured to have an impurity diffusion region of the first conductivity type formed on the surface side through another impurity diffusion region of the second conductivity type (the invention according to claim 5).

Next, in the method for manufacturing a semiconductor device according to the present invention, after forming a semiconductor element pattern on a semiconductor substrate, impurities are introduced into the semiconductor substrate through the semiconductor element pattern, and the introduced impurities are introduced. A buried region is formed by diffusion of (a).

In this case, the semiconductor element pattern photoelectrically converts the incident light from the subject into a signal charge of an amount corresponding to the amount of light in the accumulation period, and transfers the signal charge to the output side in the charge transfer period. A transfer electrode formed on the charge transfer section in a solid-state imaging device having a charge transfer section for performing a read operation and a read gate section for transferring the signal charge accumulated in the light receiving section to the charge transfer section during a read period. ,
The embedded region may be a well region functioning as a potential barrier for the signal charges (the invention according to claim 7).

[0028]

In the semiconductor device according to the present invention described in claim 1 or claim 2, since the buried region formed in the semiconductor substrate in the plane direction has a change in the depth direction,
It becomes possible to make the embedded region exist at a position corresponding to the characteristics of each functional portion forming the semiconductor element formed on the semiconductor substrate. As a result, the function of the embedded region formed in the semiconductor substrate can be made to correspond to each functional part of the semiconductor element formed on the substrate, and the function of the embedded region can be sufficiently exhibited. It will be possible.

Further, in the semiconductor device according to the present invention as defined in claims 3 to 5, since the semiconductor element formed on the semiconductor substrate is a solid-state image pickup element, the embedded region formed in the semiconductor substrate is The well region functions as a potential barrier against signal charges of the solid-state image sensor, that is, an overflow barrier for regulating / controlling the amount of signal charges accumulated.

In this case, since the depth direction of the well region is different corresponding to each part, the well region has a function corresponding to each characteristic of the light receiving part, the reading gate part and the charge transfer part. Will have.

Specifically, the well region is formed below the light receiving part so as to surround the light receiving part, and the potential barrier of the potential barrier formed in the well region has a steep characteristic. As a result, the amount of signal charges accumulated in the light receiving portion (maximum amount of signal charges accumulated) can be increased, and signal charges exceeding the apex of the potential barrier can be reliably transferred to the substrate due to the thermal kinetic energy of the signal charges. It will be leaked to the side.

Therefore, due to the photoelectric conversion characteristics of the light receiving section, the signal charges in the non-linear characteristic region above the knee point are not accumulated in the light receiving section, and the range of the linear characteristic region can be made large. Therefore, the dependency of the accumulated charge amount on the incident light amount with respect to the saturated light amount or more becomes good, and the sensitivity can be improved.

Next, in the method of manufacturing a semiconductor device according to the present invention of claim 6, first, a semiconductor element pattern is formed on a semiconductor substrate. Then, impurities are introduced into the semiconductor substrate through this semiconductor element pattern. Then, a buried region is formed by diffusion of the introduced impurities.

At this time, buried regions having different depths are formed according to the semiconductor element pattern under each impurity diffusion area (functional portion) forming the semiconductor element formed on the surface of the semiconductor substrate. . That is, since the embedded region has a change in the depth direction, it becomes possible to form the embedded region at a position according to the characteristics of each functional portion forming the semiconductor element.

As a result, the function of the embedded region formed in the semiconductor substrate can be made to correspond to each functional portion of the semiconductor element formed on the substrate, and the function of the embedded region is sufficiently exhibited. It becomes possible. In addition, it is possible to reduce the number of impurity introductions for improving the device characteristics of the semiconductor element formed on the semiconductor substrate,
It is possible to simplify the manufacturing process and reduce the number of steps.

In the method of manufacturing a semiconductor device according to the present invention, the transfer electrode of the solid-state image pickup device is formed on the semiconductor substrate, and then impurities are introduced into the semiconductor substrate through the transfer electrode. Then, a buried region is formed by diffusion of the introduced impurities.

Therefore, when the solid-state image pickup device is formed on the semiconductor substrate, the transfer is performed under the respective function units of the light-receiving unit, the read gate unit, and the charge transfer unit which form the solid-state image pickup device formed on the surface of the semiconductor substrate. Embedded regions having different depths are formed according to the pattern of the electrodes. That is,
The buried region will have a change in the depth direction,
The embedded region is formed at a position according to the characteristics of each functional unit forming the solid-state image sensor.

As a result, the buried region is formed below the light receiving part so as to surround the light receiving part, and the potential barrier of the potential barrier formed in the buried region has a steep characteristic. as a result,
The amount of signal charges accumulated in the light receiving part (maximum amount of signal charges accumulated) can be increased, and signal charges that exceed the apex of the potential barrier due to the thermal kinetic energy of the signal charges reliably flow to the substrate side. Will be done.

Therefore, due to the photoelectric conversion characteristics of the light receiving portion, signal charges in the non-linear characteristic region above the knee point are less likely to be accumulated in the light receiving portion, and the range of the linear characteristic region can be widened. Therefore, the dependency of the accumulated charge amount on the incident light amount with respect to the saturated light amount or more becomes favorable, and the sensitivity can be improved.

Further, as can be seen from the above, it is possible to minimize the introduction of impurities a plurality of times for improving the characteristics of each functional portion, so that the steps for improving the characteristics are significantly reduced. As a result, it is possible to reduce the number of manufacturing steps and the number of steps.

[0041]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device and a method of manufacturing the same according to the present invention will be described below, for example, by frame interline transfer (FIT).
Example applied to a CCD image sensor of the system (hereinafter,
The image sensor according to the embodiment and the manufacturing method thereof will be described.
Will be described with reference to FIGS.

The image sensor according to this embodiment is shown in FIG.
As shown in FIG. 5, a large number of light receiving portions 1 that perform photoelectric conversion into electric charges according to the amount of incident light are arranged in a matrix, and further, among the large number of light receiving portions 1, with respect to the light receiving portions 1 arranged in the column direction. There is no common light receiving portion 1 formed in the image portion 3 and the image portion 3 arranged in the row direction and having a plurality of common vertical transfer registers 2. The image unit 3 has a plurality of vertical transfer registers 2 and a storage unit 5 in which only a large number of vertical transfer registers 4 are continuously formed.

Further, two horizontal transfer registers, which are adjacent to the storage section 5 and are common to a large number of vertical transfer registers 4, are arranged in parallel. Where 2
Of the horizontal transfer registers of the book, the horizontal transfer register located on the storage unit 5 side is the first horizontal transfer register H1,
The other horizontal transfer register is referred to as a second horizontal transfer register H2.

Between the storage unit 5 and the first horizontal transfer register H1, the signal charges transferred to the final stage of the vertical transfer register 4 in the storage unit 5 are transferred to the first horizontal transfer register H1. Two vertical-horizontal transfer registers VH1 and VH2 are formed in common for a plurality of vertical transfer registers 4 and in parallel with each other. These two vertical-horizontal transfer registers VH1 and VH
Vertical-horizontal transfer pulses φVH1 and φVH2 are supplied to H2, respectively, and the signal charges from the vertical transfer register 4 are supplied to the first horizontal transfer register H1 by the supply of these transfer pulses φVH1 and φVH2.
Will be transferred to.

Further, the first and second horizontal transfer registers H
1 and H2, the signal charges transferred to the first horizontal transfer register H1 are selectively supplied to the second horizontal transfer register H2.
The horizontal-horizontal transfer registers HH that are transferred to the side are arranged in the horizontal direction along the horizontal transfer registers H1 and H2. In this horizontal-horizontal transfer register HH,
The horizontal-horizontal transfer pulse φHHG is supplied, and the first transfer pulse φHHG is supplied.
Signal charges in the horizontal transfer register H1 of the second
Will be transferred to the horizontal transfer register H2.

The final stages of the first and second horizontal transfer registers H1 and H2 have first and second stages, respectively.
Output units 6a and 6b are connected. These first and second output units 6a and 6b are connected to each horizontal transfer register H.
1 and H2 for converting the signal charge transferred from the final stage into an electric signal (for example, a voltage signal), for example, a charge-electric signal conversion unit 7 including a floating diffusion or a floating gate, and this charge-
The electric signal from the electric charge-electrical signal conversion unit 7 and the reset gate RG that sweeps out the signal charge after the electric signal conversion is performed in the electric signal conversion unit 7 to the drain region D according to the input of the reset pulse Pr It has an amplifier 8 for amplification. The power supply voltage Vdd is applied to the drain region D.

On the vertical transfer register 2 in the image part 3 and the vertical transfer register 4 in the storage part 5, four vertical transfer electrodes made of, for example, two layers of polycrystalline silicon are formed as insulating films, although not shown. Is formed through. That is, four vertical transfer electrodes are set as one set, and a large number of the sets are sequentially arranged in the vertical direction. The four vertical transfer electrodes φ in the image section 3 are supplied to the four vertical transfer electrodes φ having different phases.
IM1 to φIM4 are supplied respectively, and the storage unit 5
The four vertical transfer electrodes φST1 to φST4 having different phases from each other are supplied to the four vertical transfer electrodes in FIG.

By supplying the vertical transfer pulses φIM1 to φIM4 in the image section 3 and the four vertical transfer pulses φST1 to φST4 in the storage section 5,
The potential distributions under the vertical transfer electrodes in the image part 3 and the storage part 5 are sequentially changed, and as a result,
The signal charges are respectively transferred to the vertical transfer register 2 in the image part 3 and the vertical transfer register 4 in the storage part 5.
Will be transferred in the vertical direction (on the side of the first horizontal register H1).

Particularly, in the image section 3, the light receiving section 1
In the vertical blanking period, the signal charges accumulated in the vertical transfer register 2 are first read into the vertical transfer register 2, and then in the vertical blanking period, the signal charges transferred to the vertical transfer register 2 are quickly stored in the storage unit 5. To the vertical transfer register 4.

The storage section 5 transfers the signal charges transferred to the vertical transfer register 4 in the vertical blanking period to the first horizontal transfer register H1 side by row in the subsequent horizontal blanking period. As a result, the signal charges in the final stage of the vertical transfer register 4 are first transferred to the first horizontal transfer register H1 via the two vertical-horizontal transfer registers VH1 and VH2. The charges are transferred to the second horizontal transfer register H2 via the horizontal-horizontal transfer register HH.

Then, in the next horizontal scanning period, the first
And by applying two-phase horizontal transfer pulses φH1 and φH2 of two different phases to the horizontal transfer electrodes formed of, for example, two layers of polycrystalline silicon formed on the second horizontal transfer registers H1 and H2, signal charges are sequentially applied. Transferred to the corresponding charge-electric signal converter 7 on the side of the output units 6a and 6b,
It is converted into an electric signal in each electric charge-electrical signal converter 7, and is taken out as the image pickup signals S1 and S2 from the corresponding output terminal 9 via the amplifier 8, respectively.

Here, looking at the cross section around the light receiving portion 1 of this image sensor, as shown in FIG. 2, for example, a p-type impurity is introduced into an n-type silicon substrate 11 by introducing a p-type impurity (for example, boron (B)). Embedded well region 12, an n-type impurity diffusion region 13 for forming the light receiving portion 1, and an n-type transfer channel region 1 forming the vertical transfer register 2.
4 and p-type channel stopper regions 15 are formed,
Further, a p-type positive charge storage region 16 is formed on the surface of the n-type impurity diffusion region 13, and the n-type transfer channel region 1 is formed.
The second p-type well regions 17 for the purpose of reducing the smear are formed immediately below the layers 4, respectively. The p-type region 1 between the n-type impurity diffusion region 13 and the transfer channel region 14
Reference numeral 7 constitutes the read gate portion RG.

In this image sensor, as shown in the figure, a p-type buried well region 12 is formed on the surface of an n-type silicon substrate 11, and the buried well region 12 is formed.
By forming the n-type impurity diffusion region 13 forming the light receiving portion 1 at a position shallower than the above, it is configured to have a so-called electronic shutter function.

That is, by setting the substrate potential supplied to the silicon substrate 11 to the high level in synchronization with the shutter pulse, the potential barrier (overflow barrier) in the p-type buried well region 12 is lowered and the light receiving portion 1
The electric charges (electrons in this case) accumulated in the above will be swept away in the vertical direction, that is, toward the silicon substrate 11 side, beyond the overflow barrier. As a result, the period from the final application time of the shutter pulse to the electric charge read time becomes a substantial exposure period, and it is possible to prevent inconveniences such as an afterimage.

Further, in this image sensor, a photodiode is formed by a pn junction between the n-type impurity diffusion region 13 and the p-type buried well region 12, and a pn between the n-type impurity diffusion region 13 and the read gate portion RG. A photodiode having a junction, a photodiode having a pn junction of the n-type impurity diffusion region 13 and the channel stopper region 15, and a photodiode having a pn junction of the n-type impurity diffusion region 13 and the p-type hole accumulation region 16. A light receiving unit 1 (photoelectric conversion unit) is configured, and this light receiving unit 1
Are arranged in a matrix to form an imaging region. In the case of a color image pickup system, the light receiving unit 1
Depending on the color arrangement of the color filters (three primary color filters or complementary color filters) formed corresponding to the above, for example, four pixels adjacent to each other form one pixel.

On the transfer channel region 14, channel stopper region 15 and read gate portion RG, for example, S
Four transfer electrodes composed of the first-layer polycrystalline silicon layer and the second-layer polycrystalline silicon layer are formed through the gate insulating film 18 made of iO ₂ , and these transfer channel regions 1
4, the gate insulating film 18 and the transfer electrode constitute the vertical transfer register 2. Note that, in the cross-sectional view of FIG. 2, only the transfer electrode (to which the vertical transfer pulse φIM1 is applied) 19 made of, for example, the first polycrystalline silicon layer is shown as the transfer electrode.

A silicon oxide film (SiO ₂ film) 20 formed by thermal oxidation is formed on the surface of the transfer electrode 19, a PSG film 21 is formed on the entire surface including the transfer electrode 19, and the PSG film is further formed. 21 on the lower transfer electrode 1
A light-shielding Al film 22 (referred to as an Al light-shielding film) is formed so as to cover 9 and the CV is formed on the entire surface including the Al light-shielding film 22.
The SiN film 23 is formed by the D method.

The Al light-shielding film 22 is selectively etched and removed on the light receiving portion 1, and light is made to enter the light receiving portion 1 through the opening 22a formed by this etching removal. .

In the sectional view of FIG. 2, for simplicity, the flattening film on the Al light-shielding film 22, the color filter, the micro condenser lens, etc. are omitted.

In the image sensor according to this embodiment, the depth direction of the p-type buried well region 12 is different under the light receiving portion 1, under the read gate portion RG and under the vertical transfer register 2. Particularly, below the light receiving portion 1, the buried well region 12 is formed so as to wrap the light receiving portion 1 three-dimensionally.

Now, a method of manufacturing the image sensor according to the above embodiment will be specifically described with reference to the manufacturing process diagrams of FIGS. 3 and 4. The same reference numerals are given to those corresponding to FIG.

First, as shown in FIG. 3A, p-type impurities (for example, boron (B)) are introduced into the n-type silicon substrate 11 through the insulating film 31 for ion implantation by, for example, ion implantation, A p-type well region 32 reaching the surface is formed.

Next, as shown in FIG. 3B, a p-type impurity (for example, boron (B)) is selectively introduced into the p-type well region 32 by, for example, ion implantation to form a p-type well region 32. A high-concentration p-type channel stopper region 15 is formed on the surface, and then p-type impurities are selectively introduced again by ion implantation to form a second p-type well region 17. After that, n-type impurities (such as phosphorus (P) and arsenic (As)) are formed on the surface of the second p-type well region 17.
Is selectively introduced by, for example, ion implantation, and the second p
N-type transfer channel region 14 on the surface of the well region 17
To form.

Next, as shown in FIG. 3C, after removing the ion implantation insulating film 31, a gate insulating film 18 made of, for example, SiO ₂ is formed on the transfer channel region 14, and then this gate insulating film is formed. A transfer electrode 19 made of a polycrystalline silicon layer is formed via 18. Then, thermal oxidation is performed to form a thin thermal oxide film (SiO ₂ film) 2 on the surface of the transfer electrode 19.
Form 0. The gate insulating film 18 may be formed by thermal oxidation of the silicon substrate 11 as described above, or may be formed by deposition by the CVD method.

Next, as shown in FIG. 4A, the transfer electrode 19
Is used as a mask to introduce a p-type impurity (for example, boron (B)) into the silicon substrate 11 at a position deeper than the P-type well region 32 by ion implantation with high energy with an implantation energy of 1 MeV or more. The buried well region 12 is formed.

In this case, since the transfer electrode 19 is present on the transfer channel region 14, the impurities are introduced below the transfer channel region 14 through the transfer electrode 19, and the impurity under the transfer channel region 14 is introduced. The introduction position is shallower than the impurity introduction position below the portion that becomes the light receiving portion 1 due to the thickness of the transfer electrode 19.

Therefore, the buried well region 12 is
The light receiving portion 1, the read gate portion RG, and the transfer channel region 14 are continuously formed below the portion.
Moreover, the depth direction is different under each part.

Further, in the portion which becomes the read gate portion RG and the portion which corresponds to the channel stopper region 15,
Since the transfer electrode 19 is formed at the end, the buried well region 12 is formed in an inclined state when viewed from the side surface (cross section). That is, in the illustrated example, the buried well region 12 is formed such that the portion corresponding to the light receiving portion 1 is deepest and the portion corresponding to the transfer channel region 14 is shallowest, so that the channel stopper region 15 and the read gate portion are formed. The portion corresponding to RG is formed in a shape (inclined state) that allows the buried well regions 12 formed at the shallow position and the deep position to communicate with each other.

Although not shown, when element isolation is performed by selective oxidation or the like, the buried well region 12 is also formed below the field insulating layer related to the element isolation at a position corresponding to the thickness of the insulating layer. Will be formed.

In the ion implantation of the impurities, the gate insulating film 18 formed on the surface of the silicon substrate 11 functions as a buffer layer for absorbing irradiation damage caused by the ion implantation.

Here, the implantation energy in the high energy ion implantation is determined by the visible light long wavelength limit (about 800 nm) when the image sensor according to the present embodiment is an element that receives visible light. For example, in the case of boron (B) having a small mass, it is about 1 MeV (the injection peak is about 1.7 μm from the substrate surface).

In order to obtain a sufficiently long wavelength sensitivity as an image sensor, in the case of boron (B), it is desirable that it is about 3 MeV (the injection peak is about 3.8 μm). In addition, if the element is an infrared ray receiving element, the implantation energy will be high, and if it is an ultraviolet ray or X-ray receiving element, the implantation energy will naturally be low.

Next, as shown in FIG. 4B, the transfer electrode 19
Is used as a mask to selectively introduce an n-type impurity (for example, phosphorus (P) or arsenic (As)) into the surface of the P-type well region 32 by ion implantation so that n-type impurities are introduced into the surface of the P-type well region 32. Form the impurity diffusion region 13. afterwards,
Again using the transfer electrode 19 as a mask, P-type impurities (for example, boron (B)) are selectively introduced by ion implantation, and the p-type hole accumulation region 16 is formed on the surface of the n-type impurity diffusion region 13. To form.

Next, as shown in FIG. 4C, a PSG film 21 which is an interlayer insulating film is deposited on the entire surface to a thickness of about 200 to 400 nm, for example, by the CVD method. After that, A over the entire surface
l After forming the light-shielding film 22, for example, R in the vertical mode
The light-shielding portion opening 22a is formed by patterning the Al light-shielding film 22 by IE (reactive ion etching).

Then, as shown in FIG.
A silicon nitride film 23 for surface protection is formed on the entire surface including 2 by a CVD method with a thickness of about 300 to 500 nm. The silicon nitride film 23 and the lower PSG film 21 form a passivation film on the light receiving portion 1. Since the subsequent steps are the same as the normal CCD process, the description thereof will be omitted.

As described above, in the image sensor according to the above embodiment, the p-type buried well region 12 formed under the light receiving portion 1 is formed on the silicon substrate 11 via the gate insulating film 18. The p-type impurity is introduced into the silicon substrate 11 by high-energy ion implantation through the transfer electrode 19.

The buried well region 12 is used as the light receiving portion 1.
Is a region that functions as a potential barrier against the signal charges accumulated in the above, that is, an overflow barrier for regulating / controlling the accumulation amount of the signal charges.

In this case, since the depth direction of the buried well region 12 is different corresponding to each part, the buried well region 12 includes the light receiving part 1, the read gate part RG and the vertical transfer register 2. It will have the function according to each characteristic.

Specifically, the buried well region 12 is formed below the light receiving portion 1 so as to surround the light receiving portion 1, and as shown in FIGS. The potential well formed is
It becomes deeper than the conventional case (see FIGS. 9 and 10),
The potential gradient of the overflow barrier OB has a steep characteristic.

As a result, the amount of signal charges accumulated in the light receiving portion 1 (maximum amount of signal charges accumulated) can be increased, and the signal charges exceeding the apex of the overflow barrier OB can be obtained due to the thermal kinetic energy of the signal charges. Will surely flow to the substrate 11 side. This is because even if the signal charges are accumulated until the potential well is full, the potential gradient is steep, and thus the signal charges easily overflow and it is difficult to accumulate a certain amount or more of the signal charges. That is, due to the thermal kinetic energy, the ability to accumulate signal charges having a potential close to the value (threshold value) that jumps over the potential barrier and starts to flow to the substrate 11 side is lower than in the conventional case.

Therefore, due to the photoelectric conversion characteristics of the light receiving portion 1, the signal charges in the non-linear characteristic region above the knee point are not accumulated in the light receiving portion 1, and the range of the linear characteristic region can be made large. Since this is possible, the dependency of the accumulated charge amount on the incident light amount with respect to the saturated light amount or more becomes good, and the sensitivity can be improved.

From the above description, when a large amount of light is incident, the phenomenon that the signal charges flow out to the vertical transfer register 2 side beyond the read gate portion RG is suppressed, and blooming (charge overflow) resistance is suppressed. Can be improved and increased.

Further, since the signal charges are not accumulated in the light receiving portion 1 beyond the overflow barrier OB, the signal charge amount transferred by the vertical transfer register 2 is also the maximum accumulated charge amount stored in the light receiving portion 1 in advance. It doesn't have to be so large. Therefore, the transfer channel regions forming the vertical transfer register and the horizontal transfer register can be easily formed, and the amount of charge handled by the register can be small.

Further, since the buried well region 12 having a depth corresponding to the function of each part can be formed by one-time high-energy ion implantation through the transfer electrode 19, ions using a conventional plurality of masks are used. Compared with the case of forming by implantation, it is possible to effectively simplify the manufacturing process and reduce the number of steps.

In the image sensor according to the above-mentioned embodiment, the example applied to the image sensor of the frame / interline transfer (FIT) system is shown, but it is also applied to the image sensor of the interline transfer (IT) system. be able to. In this case, the storage unit 5 shown in FIG. 1 may be omitted. In addition, many light receiving parts 1
Can also be applied to a so-called line sensor in which the read gates are arranged between these light receiving section arrays and the transfer registers formed of CCDs.

In addition to the solid-state imaging device, the same can be applied to a MOS-FET having a buried region in the lower layer, a pnp transistor or an npn transistor having a buried region for the purpose of reducing collector resistance, for example. it can. For example, in the case of a MOS-FET, high-energy ion implantation is performed after formation of a field insulating layer on the substrate by selective oxidation for element isolation, and formation of a gate electrode of, for example, a polycrystalline silicon layer via a gate insulating film. Can be realized by forming an embedded region in the substrate.

[0087]

As described above, according to the semiconductor device of the present invention as defined in claim 1 or claim 2, it is possible to meet the characteristics of each functional portion constituting the semiconductor element formed on the semiconductor substrate. It becomes possible to have an embedded region at the position. As a result, the function of the embedded region formed in the semiconductor substrate can be made to correspond to each functional part of the semiconductor element formed on the substrate, and the function of the embedded region can be sufficiently exhibited. It will be possible.

According to the semiconductor device of the present invention as defined in claims 3 to 5, an embedded region having a function corresponding to each characteristic of the light receiving portion, the read gate portion and the charge transfer portion is formed. It is possible to increase the amount of signal charges accumulated in the light receiving part (maximum amount of signal charges accumulated), and moreover, the incident light amount dependency of the accumulated charge amount with respect to the saturated light amount or more is improved, and the sensitivity is improved. It is possible to improve.

Further, according to the method of manufacturing a semiconductor device of the present invention as defined in claim 6, the buried region has a change in the depth direction, which depends on the characteristics of each functional portion constituting the semiconductor element. It becomes possible to form a buried region at a different position. As a result, the function of the embedded region formed in the semiconductor substrate can be made to correspond to each functional part of the semiconductor element formed on the substrate, and the function of the embedded region can be sufficiently exhibited. It will be possible. In addition, it is possible to reduce the number of impurity introductions for improving the device characteristics of the semiconductor element formed on the semiconductor substrate,
It is possible to simplify the manufacturing process and reduce the number of steps.

Further, according to the method of manufacturing a semiconductor device of the present invention as defined in claim 7, the embedded region has a change in the depth direction, which depends on the characteristics of each functional portion forming the solid-state image pickup device. A buried region will be formed at the open position. As a result, the amount of signal charges accumulated in the light receiving portion (maximum amount of signal charges accumulated) can be increased, and moreover, the dependency of the accumulated charge amount on the incident light amount with respect to the saturated light amount or more is improved, and the sensitivity is improved. Can be achieved. In addition, it is possible to minimize the introduction of impurities multiple times to improve the characteristics of each functional unit, so the steps for improving the characteristics are significantly reduced, and the manufacturing process and man-hours are reduced. Can be realized.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment (hereinafter, referred to as an image sensor according to the embodiment) in which a semiconductor device according to the present invention is applied to a CCD image sensor of a frame interline transfer (FIT) system, for example.

FIG. 2 is a cross-sectional view showing a configuration of a light receiving portion and its peripheral portion of the image sensor according to the present embodiment.

FIG. 3 is a process diagram (1) showing the method for manufacturing the image sensor according to the embodiment.

FIG. 4 is a process diagram (2) showing the method of manufacturing the image sensor according to the embodiment.

FIG. 5 is a characteristic diagram showing a potential distribution on the line AA ′ in FIG.

FIG. 6 is a characteristic diagram showing a potential distribution on the line BB ′ in FIG.

FIG. 7 is a cross-sectional view showing a conventional method of forming a buried region.

FIG. 8 is a cross-sectional view showing a configuration of a light receiving portion and its peripheral portion of an image sensor according to a conventional example.

9 is a characteristic diagram showing a potential distribution on the line AA 'in FIG.

10 is a characteristic diagram showing a potential distribution on the line BB ′ in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Light receiving part 2 Vertical transfer register 11 n-type silicon substrate 12 p-type buried well region 14 n-type transfer channel region 15 p-type channel stopper region 16 p-type hole accumulation region 18 gate insulating film 19 transfer electrode 22 Al light shielding film RG Read gate section

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H04N 1/04 102

Claims (7)

[Claims] 1. A semiconductor device characterized in that a buried region formed in a semiconductor substrate in a plane direction has a change in a depth direction. 2. The semiconductor device according to claim 1, wherein the buried region has a change in a depth direction corresponding to device characteristics of a semiconductor element formed on the semiconductor substrate. 3. The embedded region includes a light receiving portion for photoelectrically converting incident light from a subject into a signal charge of an amount corresponding to the amount of light in the accumulation period, and a charge for transferring the signal charge to an output side during the charge transfer period. A well region that functions as a potential barrier against the signal charge in a solid-state imaging device having a transfer unit and a read gate unit that transfers the signal charge accumulated in the light receiving unit to the charge transfer unit during a read period, 3. The semiconductor device according to claim 1, wherein the depth direction is different for each part. 4. The light receiving portion in which the semiconductor element photoelectrically converts incident light from a subject into a signal charge of an amount corresponding to the amount of light in a storage period, and a charge that transfers the signal charge to an output side in a charge transfer period. A solid-state imaging device having a transfer section and a read gate section for transferring the signal charge accumulated in the light receiving section to the charge transfer section during a read period, wherein the embedded region is a potential barrier against the signal charge. 3. The semiconductor device according to claim 2, wherein the semiconductor device functions as a well region, and the depth direction is different corresponding to each part. 5. The light-receiving portion has at least a pn of the buried region forming the well region and a first-conductivity-type impurity diffusion region formed on the front surface side of the buried region.
The read gate portion is formed of another impurity diffusion region of the second conductivity type continuously formed on the surface side from the embedded region, and the charge transfer portion is formed from the embedded region. A first conductivity type impurity diffusion region formed on the surface side of the second conductivity type impurity diffusion region formed continuously on the surface is formed. Item 3. The semiconductor device according to Item 3 or 4. 6. A semiconductor device pattern is formed on a semiconductor substrate, and then impurities are introduced into the semiconductor substrate through the semiconductor device pattern to form a buried region by diffusion of the introduced impurities. Of manufacturing a semiconductor device. 7. The semiconductor element pattern includes a light receiving portion that photoelectrically converts incident light from a subject into an amount of signal charge corresponding to the amount of light during a storage period, and transfers the signal charge to an output side during a charge transfer period. A transfer electrode formed on the charge transfer unit in a solid-state imaging device having a charge transfer unit and a read gate unit that transfers the signal charge accumulated in the light receiving unit to the charge transfer unit during a read period. 7. The method of manufacturing a semiconductor device according to claim 6, wherein the buried region is a well region functioning as a potential barrier against the signal charges.