JPH08213459A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE: To obtain a semiconductor device and a method for the manufacture thereof wherein defective electrical connection and excessive current density are prevented in through holes. CONSTITUTION: Lower metal wiring 2 formed on a lower insulating film 1 and upper metal wiring 5 formed above the lower metal wiring 2, are electrically connected with each other with part of the side of a metal plug 4 bonded to the upper metal wiring 5. A layer insulating film 3 is formed on the lower insulating film 1 in such a way that the upper metal wiring 5 is buried therein. This prevents the defective electrical connection between the metal plug and lower metal wiring that may occur during the formation of the metal plug. This also suppresses increase in current density in the contact area between the metal plug and upper metal wiring.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a multi-layered metal wiring and a method of manufacturing the same, and more particularly to a poor electrical connection of a metal plug for connecting the wirings and a contact portion between the metal plug and the wiring. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device that suppresses current density in a semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art A method of forming a metal plug in a conventional semiconductor device having multi-layered metal wiring will be described. Figure 2
6 to 30 are sectional views showing steps of forming a metal plug in a conventional semiconductor device. 1 in FIGS. 26 to 30
Is a lower layer insulating film, 2 is a lower layer metal wiring, 3 is an interlayer insulating film, 4
0 is a resist pattern, 41 is a through hole (connection port), 421 is an underlying refractory metal film, 422 is a metal film for embedding, 42 is a metal film for plugs, 4 is a metal plug, 5 is an upper metal wiring, and 52 is a resist. It is a pattern. Also,
29 shows the diameter of the metal plug 4.

First, referring to FIG. 26, after forming lower layer metal wiring 2 on lower layer insulating film 1, interlayer insulating film 3 is formed on the entire surface, and resist pattern 40 is formed on interlayer insulating film 3 by photolithography. Are formed and an etching process is performed to form through holes 41 at desired positions.

Next, referring to FIG. 27, the resist pattern 40 is removed by ashing. After that, an underlaying refractory metal film 421 is formed by a sputtering method, a CVD method, or the like, subsequently, a film is formed on the entire surface by a CVD method, a high-temperature sputtering method, or a sputtering method, and then reflow embedding is performed at a high temperature. The burying metal film 422 is formed by a method or the like. Underlay refractory metal film 42
The plug metal film 42 is composed of the 1 and the embedding metal film 422.

Next, referring to FIG. 28, the metal film 422 for embedding and the underlying refractory metal film 421 are removed from the interlayer insulating film 3 by an etch back process or a CMP method, and the metal inside the through hole 41 is removed. The plug 4 is formed.

Next, referring to FIG. 29, an upper layer metal wiring film is formed on the entire surface, a resist pattern 52 is formed by photolithography, and the upper layer metal wiring film is etched using the resist pattern 52 as a mask. The wiring 5 is formed. As a result, the lower metal wiring 2 and the upper metal wiring 5
Are electrically connected to each other through the through hole 41. Next, referring to FIG. 30, the resist pattern 52 is removed,
The formation of the upper metal wiring 5 is completed.

By the way, in FIG. 26, the surface of the lower metal wiring 2 exposed at the bottom of the through hole 41 is exposed to plasma due to excessive over-etching (excessive etching) during etching of the through hole 41, and carbon is exposed. Many deposits containing (C), fluorine (F) or oxygen (O) atoms are attached. Further, when the resist pattern 40 is removed by ashing, the lower metal wiring 2 is exposed to oxygen plasma, and a metal oxide film is formed on the surface thereof.
If the underlying refractory metal film 421 is formed in this state, the resistance value (through-hole resistance value) of the metal plug may be increased, or, in extreme cases, an electrical open defect may occur. .

Therefore, in the prior art, the underlaying high melting point metal film 4 is used.
Prior to forming No. 21, in order to remove the deposits and the metal oxide film described above, cleaning was performed by a sputter etching method to obtain a low resistance through hole.

[0009]

However, in the above-mentioned steps of forming the multi-layered metal wiring, the problem of electrical connection failure of the metal plug in the through hole is accompanied by the recent reduction of the element pattern size. Has occurred.

First, since the sputter etching process used for cleaning is performed on the entire surface, not only the surface of the lower layer metal wiring 2 exposed at the bottom of the through hole 41 but also the interlayer insulating film 3 are physically etched in the same manner. Figure 31
FIG. 6 is a cross-sectional view showing cleaning by sputter etching. In FIG. 31, 21 is a metal oxide film, 31 is a chamfer,
Other symbols correspond to the symbols in FIG. 26. As shown in FIG. 31, due to the characteristics of the sputter etching method, the etching rate is particularly high at the upper portion of the opening of the through hole 41, and as the etching progresses, the etching rate becomes about 45.
The chamfering 31 is performed. Through hole 41
In the interlayer insulating film 3 above the opening, the oxide film sputter-etched is repeatedly separated from the surface of the interlayer insulating film 3 and then repeatedly collides with and absorbs the side wall of the through hole 41.
It may be adsorbed or deposited on the surface of the lower metal wiring 2 exposed at the bottom of the through hole 41. As the aspect ratio of the through-hole 41 (dimension H in the vertical direction of the through-hole / diameter d of the through-hole) increases with the recent reduction in the element pattern size, the sputter etch rate (through-hole 41) at the bottom of the through-hole 41 increases. 41 Bottom / Interlayer insulating film 3
The upper plane portion) is lowered, and an oxide film is likely to be deposited from the upper portion of the opening of the through hole 41, which makes it difficult to clean the surface of the lower layer metal wiring 2 by sputter etching as in the conventional case. . FIG. 32 is a diagram showing the sputter etch rate at the bottom of the through hole 41 with respect to the aspect ratio. As shown in FIG. 32, since the sputter etching rate decreases as the aspect ratio increases, the surface of the lower layer metal wiring 2 is not sufficiently cleaned even if the sputter etching method used for the cleaning described above is performed, resulting in poor electrical connection. The problem that occurs occurs.

[0011] Next, as shown in FIG. 29, the contact area (S ₀₎ of the metal plug 4 and the upper layer metal wiring 5 embedding the through hole 41, on the surface area of the metal plug 4 ([pi] d ^2/4)
However, as the element pattern size is reduced, the area becomes significantly smaller. As a result, the current density (current value per unit area) at the contact interface between the metal plug 4 and the upper metal wiring 5 increases, the electromigration life deteriorates, and the reliability of the semiconductor device decreases. .

The present invention has been made in order to solve the problems as described above, and there is a poor electrical connection of a metal plug for connecting an upper layer wiring and a lower layer wiring, and a metal plug and an upper layer metal wiring. An object of the present invention is to obtain a highly reliable semiconductor device and a manufacturing method thereof by suppressing the current density in the contact portion.

[0013]

According to a first aspect of the present invention, there is provided a semiconductor device having a multilayer wiring structure, wherein an upper layer metal wiring and a lower layer metal formed in a lower layer of the upper layer metal wiring. Wiring, and a metal plug electrically connecting the upper-layer metal wiring and the lower-layer metal wiring, wherein the metal plug has only a part of a side surface of the metal plug connected to the upper-layer metal wiring. Is characterized by.

The problem solving means according to claim 2 of the present invention is
An interlayer insulating film formed between the upper layer metal wiring and the lower layer metal wiring is further provided, and the upper layer metal wiring is buried in the interlayer insulating film.

In the means for solving the problem according to claim 3 of the present invention, the interlayer insulating film includes a first interlayer insulating film existing above a back surface of the upper metal wiring and a back surface of the upper metal wiring. An underlying second interlayer insulating film is provided, and the first interlayer insulating film and the second interlayer insulating film are made of materials having different etching selection ratios.

The problem solving means according to claim 4 of the present invention is
An interlayer insulating film existing in a lower layer of the upper metal wiring, and a sidewall made of the same material as the metal plug and extending from a side surface of the upper metal wiring to a surface of the interlayer insulating film are further provided.

The problem solving means according to claim 5 of the present invention is
A method of manufacturing a semiconductor device having a multilayer wiring structure, comprising:
After forming the upper layer metal wiring, forming a through hole for electrically connecting the upper layer metal wiring and the lower layer metal wiring, and filling a metal film for a plug to form a metal plug inside the through hole And a step of performing.

The problem solving means according to claim 6 of the present invention is
The method further includes the steps of forming an insulating film on the lower metal wiring, and forming the upper metal wiring so as to be buried in the insulating film.

The problem solving means according to claim 7 of the present invention is
After the step of forming the through hole, a metal film for a plug for forming a metal plug is selectively formed inside the through hole, and a side wall of the upper metal wiring also has a side formed of the metal film for a plug. And a step of selectively forming a wall.

The problem solving means according to claim 8 of the present invention is
A method of manufacturing a semiconductor device having a multilayer wiring structure, comprising:
A step of forming a through hole for electrically connecting the upper layer metal wiring film and the lower layer metal wiring after forming an upper layer metal wiring film for forming the upper layer metal wiring; and a step of forming a metal plug inside the through hole. The method includes a step of filling a metal film for a plug to be formed, and a step of patterning the upper wiring metal film to form the upper metal wiring.

The problem solving means according to claim 9 of the present invention is
The method further comprises the step of selectively forming the plug metal film inside the through hole and selectively forming a sidewall made of the plug metal film also on a sidewall of the upper metal wiring.

According to a tenth aspect of the present invention, there is provided a method for manufacturing a semiconductor device having a multi-layer wiring structure, wherein a through hole is formed for electrically connecting an upper layer metal wiring and a lower layer metal wiring. A step of selectively forming a plug metal film for forming a metal plug inside the through hole, and a wiring forming groove for forming the upper layer metal wiring in the periphery of the plug metal film. And forming a part of the plug metal film, and forming the upper metal wiring connected to the sidewall of the protruding part of the plug metal film.

[0023]

In the semiconductor device according to the first aspect of the present invention, since the side surface of the metal plug is connected to the upper metal wiring, a larger contact area between the side surface of the metal plug and the upper metal wiring can be obtained.

In the semiconductor device according to the second aspect of the present invention, in order to form the metal plug, the through hole is formed in a state where the upper layer metal wiring is buried in the interlayer insulating film. When the insulating material on the surface of the lower layer metal wiring exposed at the bottom of the through hole is removed by etching, since the upper layer metal wiring exists at the upper opening of the through hole, the interlayer insulating film is formed by the above-described etching. It is possible to prevent the insulating material from being deposited on the bottom of the through hole.

In the semiconductor device according to the third aspect of the present invention, since the metal plug is formed in a state of being embedded in the interlayer insulating film, the first interlayer insulating film is etched to form the upper metal wiring. Forming a wiring forming groove, and forming an upper layer metal wiring in the wiring forming groove. Since the first interlayer insulating film and the second interlayer insulating film have different selection ratios when the first interlayer insulating film is etched, the second interlayer insulating film serves as an etching stopper.

In the semiconductor device according to the fourth aspect of the present invention, the side surface of the upper metal wiring is protected by the sidewall.

In the method of manufacturing a semiconductor device according to the fifth aspect of the present invention, the side surface of the metal plug to be formed later is connected to the upper layer metal wiring, and a contact area between the side surface of the larger metal plug and the upper layer metal wiring is obtained. In addition, since the upper-layer metal wiring exists above the through-hole opening by forming the through-hole after forming the upper-layer metal wiring, the insulating material formed by etching the interlayer insulating film as described above. The deposition on the bottom of the through hole is suppressed.

In the method of manufacturing a semiconductor device according to the sixth aspect of the present invention, by forming the upper layer metal wiring buried in the interlayer insulating film, the side surface of the metal plug to be formed later is connected to the upper layer metal wiring, and a larger size is obtained. The contact area between the side surface of the metal plug and the upper-layer metal wiring can be obtained.Also, by forming the through-hole after forming the upper-layer metal wiring, the upper-layer metal wiring exists at the upper part of the through-hole opening. It is possible to prevent the insulating film from being deposited on the bottom of the through hole of the insulating film formed by the etching.

In the method of manufacturing a semiconductor device according to the seventh aspect of the present invention, the side wall is formed to protect the side surface of the upper metal wiring.

In the method of manufacturing a semiconductor device according to the eighth aspect of the present invention, the side surface of the metal plug to be formed later is connected to the upper layer metal wiring, and the side surface of the larger metal plug and the upper layer metal wiring film to become the upper layer metal wiring later. It is possible to obtain a contact area with the upper layer metal wiring, and by forming the through hole after forming the upper layer metal wiring, the upper layer metal wiring exists above the opening of the through hole, so that the interlayer insulating film is etched as described above. It is possible to suppress the deposition of the insulating material thus formed on the bottom of the through hole.

In the method of manufacturing a semiconductor device according to the ninth aspect of the present invention, the side wall is formed to protect the side surface of the upper metal wiring.

In the semiconductor device manufacturing method according to the tenth aspect of the present invention, the side surface of the metal plug to be formed later is connected to the upper layer metal wiring, and a contact area between the side surface of the larger metal plug and the upper layer metal wiring is obtained. You can

[0033]

【Example】

{First Embodiment} A first embodiment of the present invention will be described. FIG. 1 is a sectional view showing a metal plug of a semiconductor device according to a first embodiment of the present invention. Each reference numeral in FIG.
It corresponds to each code in 0, d is the diameter of the metal plug 4,
tM2 is the film thickness of the upper layer metal wiring 5, tILD is the lower layer metal wiring 2
And the film thickness of the interlayer insulating film 3 between the upper metal wiring 5 and the upper metal wiring 5.
The lower metal wiring 2 is formed on the lower insulating film 1, the upper metal wiring 5 is above the lower metal wiring 2, and the metal plug 4 is formed so as to penetrate the interlayer insulating film 3 and the upper metal wiring 5. With the side surface of the plug 4 connected to the upper layer metal wiring 5, the lower layer metal wiring 2 and the upper layer metal wiring 5 are electrically connected to each other until the upper layer metal wiring 5 is buried on the lower layer insulating film 1. The insulating film 3 is formed. The metal plug is composed of an embedding metal film and an underlying refractory metal film formed on the side surface and the back surface of the embedding metal film.

The contact area S between the metal plug 4 and the upper layer metal wiring 5 is πdtM2 depending on the diameter d of the metal plug 4 and the film thickness (tM2) of the upper layer metal wiring 5. It is In the conventional previously described to be the contact area (S ₀₎ is [pi] d ^2/4. Therefore, the contact area ratio (S / S ₀ ) is 4 tM 2 / d. The film thickness tM2 of the upper-layer metal wiring 5 is usually about 0.3 to 2 μm, whereas the diameter d of the metal plug 4 is 1 in the ultra-high integration semiconductor device using the metal plug in the through hole.
Since the contact area ratio (S / S ₀ ) is 1 or more, the contact area of the first embodiment is larger than that of the prior art, and the increase in current density can be suppressed.

Further, in order to form the metal plug 4,
After forming the upper layer metal wiring 5, a through hole for burying the metal plug 4 is formed, and the metal plug 4 is formed in the through hole. Before forming the metal plug 4 in order to suppress the occurrence of electrical failure of the metal plug 4, the surface of the lower layer metal wiring 2 exposed at the bottom of the through hole is cleaned by sputter etching. Since the metal wiring 5 exists, the oxide film is not deposited on the bottom of the through hole as in the conventional case, and the electrical connection failure of the metal plug 4 does not occur.

Next, a manufacturing method for forming the metal plug shown in FIG. 1 will be described. 2 to 7 are sectional views showing the steps of forming the metal plug of the semiconductor device according to the first embodiment of the present invention. 2 to 7 are the same as those in FIG.
6 to 29, which correspond to the reference numerals 40 and 50.
Is a resist pattern, 51 is a wiring forming groove for forming an upper layer metal wiring, and 53 is an upper layer metal wiring film.

First, referring to FIG. 2, after forming lower layer metal wiring 2 on lower layer insulating film 1, interlayer insulating film 3 is formed on the entire surface. The interlayer insulating film 3 is usually formed of an oxide film obtained by oxidizing SiH ₄ or TEOS as a material gas and using O ₂ or O ₃ to oxidize the material gas.

After that, a planarization method in which an oxide film to be formed is used in combination with an organic or inorganic SOG film by a method such as PECVD or atmospheric pressure CVD method, a planarization method by an etch-back method, or a planarization by a CMP method. The surface of the inter-layer insulating film 3 is flattened by applying a method such as a metallization method, and disconnection at the stepped portion of the upper metal wiring and generation of a residue at the time of forming the metal plug are prevented.

The thickness of the interlayer insulating film 3 is set to the lower metal wiring 2
In order to achieve an operating speed (operating performance) of the semiconductor device, which has a withstand voltage sufficient to electrically insulate the upper metal wiring 5 to be formed later, and which suppresses the electrical capacitance between the wirings. Required film thickness (tILD) and upper metal wiring 5
With the film thickness (tM2) of (tILD + tM2).

After the interlayer insulating film 3 is formed as described above and the surface of the interlayer insulating film 3 is flattened, a resist pattern 50 is formed by a photolithography process, and then a wiring having a depth tM2 is formed by an etching process. The trench 51 is formed, and then the resist pattern 50 is removed.

The depth of the wiring forming groove 51 is controlled by the etching amount (etching time). As a means for forming the depth of the upper layer metal wiring 5 with better controllability, FIG.
Although not shown in the figure, an insulating film is formed on the lower metal wiring 2 with a film thickness t.
After forming only the ILD, the wiring forming groove 51 (the depth is t
In some cases, an etching stopper insulating film that functions as an etching stopper for forming M2) is formed, and further an insulating film having a film thickness of tM2 is formed. If the insulating film for the etching stopper is formed, it is possible to control the depth of the wiring forming groove 51 with high accuracy by utilizing the difference in the etching selection ratio (etching rate). The etching stopper insulating film may be a film having an etching selection ratio with the silicon oxide film used as the interlayer insulating film 3, and may be, for example, a silicon nitride film or PPSQ (Poly Ph).
enyl Silses Quioxane) or P
MSQ (Poly Metal Silses Qui)
There is a film formed of an organic material such as oxane).

As another means for forming the depth of the wiring forming groove 51 with better controllability, the structure of the interlayer insulating film 3 is changed from the lower metal wiring 2 to an insulating film having a film thickness tILD (the material is, for example, the material described above). ) And an insulating film having a film thickness tM2 of a material different from the insulating film (for example, the above-mentioned material). With such a configuration of the interlayer insulating film 3, when the interlayer insulating film 3 is etched to form the wiring forming groove 51, the film thickness t is applied from above the lower layer metal wiring 2.
The insulating film up to the ILD itself acts as an etching stopper, and can be formed with better control in forming the wiring forming trench having a depth of tM2.

Next, referring to FIG. 3, an upper metal wiring film 53 is formed on the entire surface. Next, referring to FIG. 4, the upper metal wiring film 53 on the interlayer insulating film 3 is selectively removed by an etch back method, a CMP method, or the like, and the upper metal wiring 5 is formed only inside the wiring forming groove 51. leave. As a result, the upper layer metal wiring 5 buried in the insulating film is formed. The upper metal wiring film 53 is made of Al, Al-Si, Al-Si-Cu,
Aluminum-based alloys such as AlCu, AlSiTi, AlGe, and AlSc, or these aluminum-based alloys and TiN,
Ti, TiN and Ti stack, TiW, W, WSi, Mo
A laminated film with a refractory metal film such as Si or TiON is used. Alternatively, Cu, Ag, Au, W, or a laminated film of these and the above-mentioned refractory metal film may be used. The method for forming these wiring metal films is a method such as a sputtering method, a CVD method, or a method of using these methods together depending on the respective films when forming a laminated film. In order to embed a metal film in the wiring formation groove 51 without generating voids (cavities), it is usually formed by a CVD method, a high temperature sputtering method, a bias sputtering method, a sputtering method, and then kept at a high temperature to keep the metal. A method of embedding by utilizing the reflow of the film is often used.

Next, referring to FIG. 5, a photolithography process is performed to form a resist pattern 40. The upper metal wiring 5 is etched using the resist pattern 40 as a mask, and then the interlayer insulating film 3 is etched. As a result, a through hole 41 that penetrates the upper layer metal wiring 5 and the interlayer insulating film 3 and reaches the lower layer metal wiring 2 is formed. Then, the resist pattern 40 is removed.

Next, referring to FIG. 6, the plug metal film 42.
To form. Next, referring to FIG. 7, the plug metal film 42
Are selectively removed to form the metal plug 4. The metal plug 4 is formed by a method similar to the method of forming the upper layer metal wiring 5 inside the wiring forming groove 51 shown in FIG.
The material of the metal plug 4 (metal film for plug) is the same as the material of the upper metal wiring film 53 described above. The surface of the lower-layer metal wiring 2 exposed at the bottom of the through hole 41 is subjected to plasma during through hole etching, oxygen plasma during resist removal, and an organic solvent used for resist residue removal and cleaning as in the conventional example. The metal oxide film is formed by being exposed to pure water used at that time. The metal oxide film is removed, and sputter cleaning is performed to obtain a good electrical connection.
Since the upper-layer metal wiring 5 is present, there is no deposition (reattachment) of the insulating film on the surface of the lower-layer metal wiring 2 at the bottom of the through hole 41, and the surface of the upper-layer metal wiring 5 is sufficiently cleaned by sputter etching. As a result, the metal plug 4 formed in the through hole 41 electrically connects the lower-layer metal wiring 2 and the upper-layer metal wiring 5 in an excellent electrical connection.

Further, the upper metal wiring 5 and the through hole 4
As described above, the metal plugs 4 in the inner portion 1 contact with each other in a larger area than before, so that even if the diameter d of the through holes 41 is reduced, the increase in current density can be suppressed and the reliability can be improved. .

{Second Embodiment} A second embodiment of the present invention will be described. 8 to 11 are sectional views showing a metal plug of a semiconductor device according to a second embodiment of the present invention. Each reference numeral in FIGS. 8 to 11 corresponds to each reference numeral in FIGS. 2 to 7, 52 is a resist pattern, and 43 is a sidewall.

First, referring to FIG. 8, after forming lower layer metal wiring 2 on lower layer insulating film 1, interlayer insulating film 3 is formed on the entire surface. The film thickness of the interlayer insulating film 3 electrically insulates the lower layer metal wiring 2 and the upper layer metal wiring 5 from each other, has sufficient insulation resistance, and suppresses the electrical capacitance between the wirings, thereby operating the semiconductor device. It has a film thickness tILD necessary to achieve speed (operating performance). The method of forming the interlayer insulating film 3 and the planarization method are the same as those described in the first embodiment. Further, the material gas and the like used in the formation are the same as in the first embodiment.

Subsequently, an upper metal wiring film is formed on the entire surface,
A resist pattern 52 is formed thereon by photolithography. The upper layer metal wiring film is etched using the resist pattern 52 as a mask to form the upper layer metal wiring 5. As the upper metal wiring film, an aluminum alloy as described in the first embodiment or a laminate of an aluminum alloy and a refractory metal film is used. Alternatively, Cu, Ag, Au, W, or a laminated film of these and a refractory metal may be used. A sputtering method or a CVD method is used as a method for forming these metal films for wiring. In the first embodiment, it is necessary to carefully form the metal film so that no void is generated inside the wiring forming groove 51. Therefore, the bias sputtering method or the high temperature sputtering method is used. Alternatively,
Although a CVD method or the like is often used, in this embodiment, it is sufficient to form a metal film on the entire surface of the flat interlayer insulating film 3, and it is easier and cheaper than the first embodiment. A metal film can be formed.

Next, referring to FIG. 9, a resist pattern 5
After removing 2, the resist pattern 40 is formed again by the photolithography process, and the upper metal wiring 5 and the interlayer insulating film 3 are etched by using the resist pattern 40 as a mask. A through hole 41 that penetrates 3 and reaches the lower metal wiring 2 is formed. Then, the resist pattern 40 is removed.

Next, referring to FIG. 10, the plug metal film 4 is formed.
Form 2 The method for forming the plug metal film 42 and its material are the same as those described in the first embodiment. Before forming the plug metal film 42, the through hole 41 is formed.
The surface of the lower layer metal wiring 2 exposed at the bottom is cleaned by sputter etching. However, since the upper layer metal wiring 5 is present at the upper portion of the opening of the through hole 41, it is formed later in the through hole 41 as in the first embodiment. The formed metal plug 4 electrically connects the lower-layer metal wiring 2 and the upper-layer metal wiring 5 in an excellent state.

Next, referring to FIG. 11, the plug metal film 4 is formed.
By etching back 2 through hole 41
A metal plug 4 is formed inside. As for the metal plug 4 and the upper layer metal wiring 5 inside the through hole 41, part of the side surface of the metal plug 4 is connected to the upper layer metal wiring 5 as in the first embodiment. Even when the connection is made in a larger area and the diameter of the through hole 41 is reduced, the increase in current density can be suppressed and the reliability can be improved.

Further, in this embodiment, the metal plug 4 is formed inside the through hole 41, and at the same time, the side wall 43 of the plug metal film 42 is formed on the side wall of the upper layer metal wiring 5. Thereby, the reliability of the upper layer metal wiring 5 is improved. That is, usually, the metal wiring is stressed by the interlayer insulating film and the passivation film, and the wiring pattern (wiring width) is reduced, and the problem of disconnection failure (stress migration) of the metal wiring due to the stress from these films becomes serious. ing. In this embodiment, since the side surface of the upper metal wiring 5 is protected by the sidewall 43 formed of the plug metal film 42, the stress from the interlayer insulating film and the passivation film covering the upper metal wiring 5 formed in the subsequent process is relaxed. It is possible to improve the reliability of metal wiring.

{Third Embodiment} A third embodiment of the present invention will be described. 12 to 15 are sectional views showing steps of forming a through hole of a semiconductor device according to the third embodiment of the present invention. Each reference numeral in FIGS. 12 to 15 corresponds to each reference numeral in FIGS. 2 to 7, and 44 is a resist pattern.

First, referring to FIG. 12, after forming lower layer metal wiring 2 on lower layer insulating film 1, interlayer insulating film 3 is formed on the entire surface. The film thickness of the interlayer insulating film 3 is tILD + tM2 which is the sum of tILD and the film thickness tM2 of the upper metal wiring 5 to be formed later, as in the first embodiment. Next, a resist pattern 44 is formed on the interlayer insulating film 3, and the resist pattern 44 is formed.
Using as a mask, the interlayer insulating film 3 is etched to form the through hole 41 reaching the lower metal wiring 2. Then, the resist pattern 44 is removed.

Next, referring to FIG. 13, the through hole 41
A metal plug 4 is formed inside. The method of forming the metal plug 4, the material and the etch back method are the same as those in the first and second embodiments, but when cleaning the surface of the lower layer metal wiring 2 exposed at the bottom of the through hole 41, the through hole 41 is used. Adhesion of oxide film (SiO) from the opening
It is difficult to prevent the occurrence of deposition. Therefore, it is necessary to take measures such as lowering the pressure during sputter etching and increasing the bias voltage (electric field strength). FIG.
6 shows the sputter etch rate of the aluminum oxide film (metal oxide film 21 shown in FIG. 31) with respect to the bias voltage. FIG.
According to No. 6, by increasing the bias voltage, the sputter etch rate of the aluminum oxide film can be increased.

Next, referring to FIG. 14, a photolithography process and an etching process are performed to form a wiring forming groove 51 around the metal plug 4. As a result, the wiring forming groove 51 is formed.
A part of the side surface of the metal plug 4 is exposed inside.

Next, referring to FIG. 15, after removing the resist pattern 50, an upper layer metal wiring film 53 is selectively formed inside the wiring forming groove 51. Metal film forming method for forming the wiring forming groove 51, metal material, and interlayer insulating film 3
The method of removing the above-mentioned extra metal film is the same as that described in the first embodiment. Thereby, the upper metal wiring 5
Is electrically connected to a part of the side surface of the metal plug 4, and its contact area is πdtM2, which is smaller than that of the conventional structure.
Even when the connection is made in a larger area and the diameter of the through hole 41 is reduced, the increase in current density can be suppressed and the reliability can be improved.

{Fourth Embodiment} A fourth embodiment of the present invention will be described. 17 to 21 are sectional views showing steps of forming a through hole of a semiconductor device according to the fourth embodiment of the present invention. Each reference numeral in FIGS. 17 to 21 corresponds to each reference numeral in FIGS. 8 to 11, and 53 is an upper layer metal wiring film.

First, referring to FIG. 17, lower layer metal wiring 2
Then, the interlayer insulating film 3 is formed on the entire surface in the same manner as described in the second embodiment. At this time, the interlayer insulating film 3 is formed to have a film thickness tILD. The method of forming the interlayer insulating film 3, the planarization method, the material gas, etc. are the same as those described in the first and second embodiments. Subsequently, an upper layer metal wiring film 53 is formed on the entire surface. Upper metal wiring film 53
Are the same as those described in the first and second embodiments. Similar to the second embodiment, also in this embodiment, the upper metal wiring film 53 is formed on the entire surface of the flat interlayer film. Therefore, the upper metal wiring film 53 can be formed more easily and cheaply than in the first embodiment.

Next, referring to FIG. 18, a resist pattern 40 is formed by photolithography, and the upper metal wiring film 53 and the interlayer insulating film 3 are etched by using the resist pattern 40 as a mask, whereby the upper metal wiring film 53 is formed.
A through hole 41 is formed which penetrates the interlayer insulating film 3 and reaches the lower metal wiring 2.

Next, referring to FIG. 19, after removing resist pattern 40, photolithography is performed again to form resist pattern 52 in through hole 41 and upper metal wiring film 53 around the opening of through hole 41. By forming it on the top, using this as a mask, by performing an etching process,
The upper metal wiring 5 is formed.

Next, referring to FIG. 20, after removing resist pattern 52, a metal plug is formed inside through hole 41. Next, with reference to FIG. 21, similarly to the second embodiment, a metal plug is formed inside the through hole 41, and at the same time, a metal film wall is formed on the side wall of the upper layer wiring.

According to this embodiment, as described in the second embodiment, when the surface of the lower layer metal wiring 2 exposed at the bottom of the through hole is cleaned by sputter etching, the upper portion of the through hole opening is Since the upper wiring metal film is present, the insulating film (SiO) is not attached or deposited, and an electrically stable connection state can be obtained.

Further, since the metal plug inside the through hole 41 and the upper layer metal wiring are connected in a larger area than in the conventional structure, the increase in current density is suppressed even when the diameter of the through hole 41 is reduced. It is possible and the reliability is improved.

Further, similarly to the second embodiment, the side wall 43 of the plug metal film 42 is formed on the side wall of the upper metal wiring 5, so that the reliability of the upper metal wiring 5 is improved. .

Further, as the element size is reduced, the size (diameter) of the through hole 41 is also reduced, and resist patterning by photolithography is becoming very difficult. One of the reasons why resist patterning is becoming difficult,
This is a factor of fluctuations in resist film thickness. In the second embodiment, the resist pattern 4 depends on the line width of the lower layer metal wiring 2.
Since the film thickness of 0 varies, the diameter d of the through hole tends to vary in size. Thin upper layer metal wiring 5 (line width is 1
The diameter of the through hole 41 to be formed becomes larger than the desired diameter due to the thin film thickness of the resist pattern 40 above 0 μm), while the thick wiring (the line width is several tens).
(μm or more), the resist pattern 40 becomes thicker and the diameter d of the through hole 41 becomes smaller than the desired diameter. Such a variation in the dimension d of the through hole 41 due to the variation in the film thickness of the resist pattern 40 becomes more serious as the size (diameter d) of the through hole 41 is reduced.
Therefore, when the size (diameter d) of the through-hole 41 is 0.4 to 0.8 μm or less, the advantage of this embodiment becomes great.

Further, since the upper layer metal wiring film 53 exists on the entire surface of the lower layer of the resist pattern 40,
Compared with the embodiment described above, the film thickness of the resist pattern 40 can be further reduced, and there is an advantage that a finer resist pattern 40 can be formed. That is, using the resist pattern 40 as a mask, the upper metal wiring film 53 is formed.
When the interlayer insulating film 3 is etched after etching, the etching process can be performed using the upper metal wiring film 53 as a mask. Therefore, the required thickness of the resist pattern 40 is equal to that of the upper metal wiring film 53. A film thickness that can withstand etching is sufficient. In the first embodiment, when the resist pattern 40 is thinned by the etching process and disappears during the etching of the through hole 41, the interlayer insulating film 3 is etched by the region without the upper metal wiring 5. As a result, the film thickness of the interlayer insulating film 3 which should not be formed is reduced,
Electrical insulation failure will occur. On the other hand, in this embodiment, during the etching process of the interlayer insulating film 3, the upper metal wiring film 53 acts as a protective layer, and the interlayer insulating film 3 is not thinned.

As described above, this embodiment has an advantage that the through hole 41 can be formed more stably.

{Fifth Embodiment} A fifth embodiment of the present invention will be described. 22 and 23 are sectional views showing steps of forming a through hole of a semiconductor device according to the fifth embodiment of the present invention. 22 and FIG. 23 are the same as those in FIG.
20. Corresponding to the respective symbols in FIG.

First, referring to FIG. 22, similarly to the fourth embodiment, after forming lower layer metal wiring 2 on lower layer insulating film 1, interlayer insulating film 3 is formed on the entire surface. Subsequently, an upper layer metal wiring film 53 is formed on the entire surface, and photolithography and etching are performed to form a through hole 41 which penetrates the upper layer metal wiring film 53 and the interlayer insulating film 3 and reaches the lower layer metal wiring 2. The method so far is the same as that of FIGS. 17 and 18 in the fourth embodiment.

Next, the plug metal film 42 is formed on the entire surface. Prior to the formation of the plug metal film 42, the surface of the lower layer metal wiring 2 exposed at the bottom of the through hole 41 is cleaned by sputter etching. However, since the upper layer metal wiring film 53 exists above the opening of the through hole 41. The fact that no electrical connection failure occurs is the same as described in the first to fourth embodiments.

Referring to FIG. 23, a resist pattern 52 is formed by photolithography, the plug metal film 42 is etched using the resist pattern 52 as a mask, and then the upper metal wiring film 53 is etched. The metal plug 4 is formed. As a result, the metal plug 4 embedded in the through hole 41 has a structure extending from the inside of the through hole 41 to the upper surface of the upper metal wiring film 53. That is, the structure is such that the plug metal film 42 is stacked on the upper metal wiring film 53, and both are paired to form the upper metal wiring 5. As a result, any reliability problem caused by an increase in current density at the contact portion between the metal plug 4 inside the through hole 41 and the upper layer metal wiring 5 is eliminated. Further, since the wiring structure in which the plug metal film 42 and the upper metal wiring film 53 are laminated in a pair, the reliability of the upper metal wiring 5 is significantly improved.

{Sixth Embodiment} A sixth embodiment of the present invention will be described. 24 and 25 are sectional views showing steps of forming a through hole of a semiconductor device according to the sixth embodiment of the present invention. 24 and 25 are the same as those in FIG.
23 and correspond to the reference numerals in FIG.

First, referring to FIG. 24, according to the manufacturing method described in the fourth embodiment, lower layer metal wiring 2 is formed on lower layer insulating film 1, and then interlayer insulating film 3 is formed on the entire surface. Next, an upper metal wiring film 53 is formed on the entire surface, and photolithography and etching are performed to form a through hole that penetrates both the upper metal wiring film 53 and the interlayer insulating film 3 and reaches the lower metal wiring 2. To do. The above manufacturing method is the same as that in FIGS. 17 and 18 in the fourth embodiment.

Further, similarly to the case shown in FIG. 22 described in the fifth embodiment, a metal film for a plug is formed on the entire surface.
Prior to the formation of the plug metal film, the surface of the lower metal wiring 2 exposed at the bottom of the through hole 41 is cleaned by sputter etching to remove the oxide on the surface.
As described in the first to fifth embodiments, no electrical connection failure occurs in the through hole 41 because the upper metal wiring film 53 exists in the through hole opening.

Then, the plug metal film on the upper metal wiring film 53 is selectively removed by performing an etching process or a CMP polishing process over the entire surface. As a result, the metal plug 4 is formed inside the through hole 41. The metal plug 4 contacts the upper metal wiring film 53 on its side surface.

Referring to FIG. 25, a photolithography process is performed to form a resist pattern 52, and an etching process is performed using the resist pattern 52 as a mask to form the upper metal wiring 5.

The difference of this embodiment from the fifth embodiment is that after the structure shown in FIG. 22 is formed, the plug metal film is selectively removed to form the metal plug 4 inside the through hole 41 (this embodiment). Example) or the photolithography and etching process is performed to form the upper metal wiring 5 in which the plug metal film 42 and the upper metal wiring film 53 are laminated (fifth embodiment). The fifth embodiment has a drawback that the upper metal wiring 5 has a laminated structure of the plug metal film 42 and the upper metal wiring film 53, and the etching process thereof becomes difficult. In addition, a thick resist pattern 52 is required to etch the stacked thick upper metal wiring film, and the fine resist pattern 5 is required even in the photoengraving process.
Although it is difficult to form the second wiring 2, there is an advantage that the reliability of the upper layer metal wiring 5 is improved. On the other hand, in the present embodiment, in terms of reliability of the upper metal wiring 5,
It is the same as the conventional example, and it is difficult to obtain high reliability of the upper metal wiring 5 as obtained in the fifth embodiment, but in the method of performing the etching process using the resist pattern 52 as a mask, The upper layer metal wiring 5 can be formed by the conventional technique.

{Modification} In the first to sixth embodiments, the case of the two-layer metal wiring structure of the lower layer metal wiring 2 and the upper layer metal wiring 5 has been described. Also in, it is possible to obtain the same structure by the same method and obtain the same effect.

[0081]

According to the first aspect of the present invention, due to the large contact area, even if the diameter of the metal plug is reduced, the increase in the current density of the current flowing through the contact surface can be suppressed, and the reliability is improved. It has the effect of being peeled off.

According to the second aspect of the present invention, since the upper layer metal wiring exists in the upper portion of the through hole opening, the interlayer insulating film is prevented from being etched by the sputter etching to deposit the insulator on the bottom portion of the through hole. Therefore, there is an effect that an electrically good connection state can be obtained between the upper layer metal wiring and the lower layer metal wiring via the metal plug formed later.

According to the third aspect of the present invention, since the second interlayer insulating film functions as an etching stopper, there is an effect that the depth of the wiring forming groove can be formed with good control.

According to the fourth aspect of the present invention, since the side surface of the upper metal wiring is protected, the disconnection failure of the upper metal wiring caused by the stress from the interlayer insulating film or the passivation film covering the upper metal wiring. And the reliability of the upper metal wiring can be improved.

According to the fifth aspect of the present invention, due to the large contact area, even if the diameter of the metal plug is reduced, the increase in the current density of the current flowing through the contact surface can be suppressed, and the reliability can be improved. In addition, the metal plug formed in the through hole is prevented from depositing an insulator in the through hole, and the metal plug formed in the through hole is a semiconductor capable of electrically connecting the upper layer metal wiring and the lower layer metal wiring in an electrically good state. The effect is that a device can be obtained.

According to the sixth aspect of the present invention, due to the large contact area, even if the diameter of the metal plug is reduced, the increase in the current density of the current flowing through the contact surface can be suppressed and the reliability can be improved. Moreover, the deposition of the insulating material in the through hole is prevented, and thus the metal plug formed in the through hole can electrically connect the upper layer metal wiring and the lower layer metal wiring in an electrically good state, Moreover, there is an effect that a semiconductor device in which the upper metal wiring is buried in the interlayer insulating film can be obtained.

According to claim 7 of the present invention, since the side surface of the upper metal wiring is protected, the disconnection failure of the upper metal wiring caused by the stress from the interlayer insulating film or the passivation film covering the upper metal wiring. It is possible to obtain a semiconductor device capable of suppressing the above and improving the reliability of the metal wiring.

According to the eighth aspect of the present invention, due to the large contact area, even if the diameter of the metal plug is reduced, the increase in the current density of the current flowing through the contact surface can be suppressed, and the reliability can be improved. In addition, the metal plug formed in the through hole is prevented from depositing an insulator in the through hole, and the metal plug formed in the through hole is a semiconductor capable of electrically connecting the upper layer metal wiring and the lower layer metal wiring in an electrically good state. The effect is that a device can be obtained.

According to the ninth aspect of the present invention, since the side surface of the upper metal wiring is protected, the disconnection failure of the upper metal wiring caused by the stress from the interlayer insulating film or the passivation film covering the upper metal wiring. It is possible to obtain a semiconductor device capable of suppressing the above and improving the reliability of the metal wiring.

According to the tenth aspect of the present invention, due to the large contact area, even if the diameter of the metal plug is reduced, the increase in the current density of the current flowing through the contact surface can be suppressed, and the reliability can be improved. There is an effect that a semiconductor device can be obtained.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a metal plug of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a process of forming a metal plug of a semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a process of forming a metal plug of the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a step of forming a metal plug of a semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a process of forming a metal plug of the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a process of forming a metal plug of the semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a process of forming a metal plug of the semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a cross-sectional view showing a step of forming a metal plug of a semiconductor device according to a second embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a process of forming a metal plug of a semiconductor device according to a second embodiment of the present invention.

FIG. 10 is a cross-sectional view showing a step of forming a metal plug of a semiconductor device according to a second embodiment of the present invention.

FIG. 11 is a cross-sectional view showing a metal plug of a semiconductor device according to a second embodiment of the present invention.

FIG. 12 is a cross-sectional view showing a process of forming a metal plug of a semiconductor device according to a third embodiment of the present invention.

FIG. 13 is a cross-sectional view showing a process of forming a metal plug of a semiconductor device according to a third embodiment of the present invention.

FIG. 14 is a cross-sectional view showing a step of forming a metal plug of a semiconductor device according to a third embodiment of the present invention.

FIG. 15 is a cross-sectional view showing a metal plug of a semiconductor device according to a third embodiment of the present invention.

FIG. 16 is a diagram showing a sputter etch rate of an aluminum oxide film with respect to a bias voltage.

FIG. 17 is a cross-sectional view showing a step of forming a metal plug of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 18 is a cross-sectional view showing a process of forming a metal plug of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 19 is a cross-sectional view showing a step of forming a metal plug of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 20 is a cross-sectional view showing a step of forming a metal plug of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 21 is a cross-sectional view showing a metal plug of a semiconductor device according to a fourth example of the present invention.

FIG. 22 is a cross-sectional view showing a step of forming a metal plug of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 23 is a cross-sectional view showing a step of forming a metal plug of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 24 is a cross-sectional view showing a step of forming a metal plug of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 25 is a cross-sectional view showing a process of forming a metal plug of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 26 is a cross-sectional view showing a step of forming a metal plug in a conventional semiconductor device.

FIG. 27 is a cross-sectional view showing a step of forming a metal plug in a conventional semiconductor device.

FIG. 28 is a cross-sectional view showing a step of forming a metal plug in a conventional semiconductor device.

FIG. 29 is a cross-sectional view showing a step of forming a metal plug in a conventional semiconductor device.

FIG. 30 is a cross-sectional view showing a metal plug in a conventional semiconductor device.

FIG. 31 is a cross-sectional view showing cleaning by sputter etching.

FIG. 32 is a diagram showing a sputter etch rate at the bottom of a through hole with respect to an aspect ratio.

[Explanation of symbols]

1 lower layer insulating film, 2 lower layer metal wiring, 3 interlayer insulating film,
4 metal plug, 5 upper layer metal wiring, 40 resist pattern, 41 through hole, 42 metal film for plug, 4
3 sidewalls, 44,50 resist pattern,
51 wiring forming groove, 52 resist pattern, 53
Upper metal wiring film.

Claims (10)

[Claims] 1. A semiconductor device having a multilayer wiring structure, wherein an upper metal wiring, a lower metal wiring formed in a lower layer of the upper metal wiring, the upper metal wiring and the lower metal wiring are electrically connected to each other. And a metal plug to be connected, wherein the metal plug has only a part of a side surface of the metal plug connected to the upper layer metal wiring. 2. The interlayer insulating film formed between the upper layer metal wiring and the lower layer metal wiring is further provided, and the upper layer metal wiring is buried in the interlayer insulating film. 1. The semiconductor device according to 1. 3. The interlayer insulating film includes a first interlayer insulating film existing above a back surface of the upper layer metal wiring and a second interlayer insulating film existing below a back surface of the upper layer metal wiring. 3. The semiconductor device according to claim 2, further comprising: the first interlayer insulating film and the second interlayer insulating film made of materials having different etching selection ratios. 4. An interlayer insulating film existing in a lower layer of the upper metal wiring, and a sidewall made of the same material as the metal plug and extending from a side surface of the upper metal wiring to a surface of the interlayer insulating film. The semiconductor device according to claim 1, further comprising: 5. A method of manufacturing a semiconductor device having a multi-layer wiring structure, comprising the steps of forming an upper metal wiring and then forming a through hole for electrically connecting the upper metal wiring and the lower metal wiring. And a step of filling a metal film for a plug to form a metal plug inside the through hole, the method for manufacturing a semiconductor device. 6. The manufacturing of a semiconductor device according to claim 5, further comprising: a step of forming an insulating film on the lower layer metal wiring; and a step of forming the upper layer metal wiring so as to be buried in the insulating film. Method. 7. After the step of forming the through hole, a plug metal film for forming a metal plug is selectively formed inside the through hole, and the plug metal film is formed on the sidewall of the upper layer metal wiring. The method for manufacturing a semiconductor device according to claim 5, further comprising a step of selectively forming a sidewall made of a metal film. 8. A method of manufacturing a semiconductor device having a multilayer wiring structure, wherein an upper metal wiring film for forming an upper metal wiring is formed, and then the upper metal wiring film and the lower metal wiring are electrically connected. To form a through hole, a step of filling the through hole with a plug metal film for forming a metal plug, and a step of patterning the upper wiring metal film to form the upper metal wiring. And a method for manufacturing a semiconductor device comprising: 9. The step of selectively forming the plug metal film inside the through hole, and selectively forming a sidewall made of the plug metal film also on the sidewall of the upper layer metal wiring. The method for manufacturing a semiconductor device according to claim 8, further comprising: 10. A method of manufacturing a semiconductor device having a multilayer wiring structure, comprising: forming a through hole for electrically connecting an upper metal wiring and a lower metal wiring; and forming a metal plug inside the through hole. A step of selectively forming a metal film for a plug to be formed, forming a wiring forming groove for forming the upper metal wiring around the metal film for a plug, and A method of manufacturing a semiconductor device, comprising: a step of projecting a portion; and a step of forming the upper metal wiring connected to a sidewall of a projecting portion of the plug metal film.