JPH08205224A - Intermittent receiving system - Google Patents

Abstract

PURPOSE: To provide an intermittent receiving system with which power consumption is reduced while securing the incoming of a preamble signal. CONSTITUTION: In an incoming call waiting state (step P1), when no call detecting signal is detected and an electric field intensity signal is periodically inputted based on radio waves received in an intermittent receiving state (steps P2 and P5), it is checked whether electric field intensity is changed from the electric field intensity at the time of last detection over a prescribed allowable range or not (step P6) and when it is not changed, the incoming call waiting state is started as is. When the electric field intensity is changed, it is checked whether its value is higher than an electric field intensity value at the time of last detection or not (step P7) and when that value is higher than the last time, a detection bit length for detecting the preamble signal is controlled long (step P8). When that value is lower than the last time, the detection bit length is controlled short (step P9).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a discontinuous reception system,
More specifically, the present invention relates to an intermittent reception method that reduces the power consumption of a receiving device that intermittently receives radio waves.

[0002]

2. Description of the Related Art In a portable radio receiver, such as a pager, a radio wave transmitted from a base station or the like is intermittently received by its receiving circuit (radio circuit section) and a predetermined received signal is received. By detecting the preamble signal from the bit length and synchronizing with the own frame, power consumption is reduced and the signal addressed to itself is received.

Conventionally, in order to detect this preamble signal, 8 bits or 12 bits are used from the received signal.
The presence or absence of preamble detection is determined by extracting a bit string having a fixed length such as bits and determining whether the extracted bit string matches a predetermined bit string of the preamble signal.

That is, the power of the receiving circuit is periodically turned on / off, radio waves are received, a predetermined bit of the received signal is detected, and whether the preamble signal is a preamble signal depends on whether or not it matches the bit string of the preamble signal. Check
If it is not the preamble signal, the power of the receiving circuit is turned off.

When a predetermined bit of the received signal matches the bit string of the preamble signal, it is determined that the preamble signal has been detected, and then the power of the receiving circuit is turned on,
It receives and processes whether or not it is addressed to itself.

[0006]

However, in such a conventional intermittent receiving system, the detection bit length for detecting the preamble signal is fixed,
There is a problem that the preamble cannot be properly detected due to the change of the electric field strength, and the power consumption increases due to a detection error of the preamble signal.

That is, the preamble detection bit length and the incoming call rate have a relationship as shown in FIG. As can be seen from FIG. 12, in the weak electric field, if the preamble detection bit length is short, the number of detection errors is large, but the incoming call rate is high.
It also consumes a lot of power. Further, if the preamble detection bit length is long, power consumption is low, but the preamble signal may not be detected by the set bit length, and the incoming call rate is low. Further, in medium / strong electric fields, although the incoming call rate is high, if the preamble detection bit length is short, the ON time of the receiving unit increases due to a detection error, power consumption is large, and if the preamble detection bit length is long, a detection error occurs. Power consumption is reduced. The electric field strength of the radio wave changes depending on the distance between the receiving device and the transmitting base station and the surrounding environment.

However, in the conventional discontinuous reception system, the preamble detection bit length is constant, so if the preamble detection bit length is set to be short, the incoming call rate is high but many detection errors occur. When the power consumption increases and the preamble detection bit length is set to be long, the power consumption is small, but the preamble signal cannot detect only the set bit length, and there is a problem that the incoming call rate deteriorates when the electric field is weak. there were.

Therefore, according to the present invention, by changing the preamble detection bit length according to the electric field strength of the radio wave, the preamble signal is accurately detected without being influenced by the distance from the transmitting base station or the surrounding environment. It is an object of the present invention to provide an intermittent reception system that can reduce power consumption due to detection error.

[0010]

According to the intermittent receiving method of the present invention, a radio signal is received at a constant cycle, and a specific bit string is detected from digital data demodulated from the received signal to detect only the radio signal of its own frame. In the intermittent reception method for receiving, the electric field strength value of the radio signal is detected by the electric field strength detecting means, the electric field strength value detected by the electric field strength detecting means is compared with a predetermined electric field strength value by the comparing means, The above object is achieved by adjusting the length of the specific bit string detected from the digital data by the detection bit adjusting means based on the comparison result.

In this case, for example, as described in claim 2, the detection bit adjusting means determines the length of the specific bit string to be detected when the detected electric field strength value is larger than the predetermined electric field strength value. The length of the specific bit string to be detected may be shortened by a predetermined bit when the detected electric field strength value is smaller than the predetermined electric field strength value by making the predetermined bit length longer.

According to a third aspect of the present invention, the allowable range of the difference between the detected electric field strength value and the predetermined electric field strength value is stored in the storage means, and the comparison means is stored in the electric field strength detection means. A difference between the detected electric field strength value and the predetermined electric field strength value is calculated to determine whether the difference exceeds the allowable range stored in the storage means,
The detection bit adjusting means may change the length of the specific bit string to be detected only when the comparing means determines that the difference exceeds the allowable range.

Further, as described in claim 4, the comparing means compares the electric field strength value detected this time by the electric field strength detecting means with the electric field strength value detected last time as the predetermined electric field strength value. May be

[0014]

According to the intermittent reception method of the present invention, when a radio signal is received at a constant cycle and a specific bit string is detected from digital data demodulated from the received signal, only the radio signal of its own frame is received. The electric field strength value of the radio signal is detected by the electric field strength detecting means, the detected electric field strength value is compared with a predetermined electric field strength value by the comparing means, and based on the comparison result, the detection bit adjusting means performs digital detection. Adjust the length of the specific bit string detected from the data.

Therefore, the detection bit length for detecting the preamble signal can be changed according to the electric field strength of the radio wave, the preamble can be accurately detected, and the power consumption due to the detection error can be reduced. be able to.

In this case, for example, as described in claim 2, when the detected electric field strength value is larger than the predetermined electric field strength value, the detection bit adjusting means lengthens the length of the specific bit string to be detected by a predetermined bit length. However, when the detected electric field strength value is smaller than the predetermined electric field strength value, the length of the specific bit string to be detected is shortened by a predetermined bit, whereby the preamble can be accurately detected.

Further, for example, as described in claim 3, an allowable range of the difference between the detected electric field strength value and the predetermined electric field strength value is stored in the storage means, and the comparison means stores the detected electric field strength value. The detection bit is calculated only when the difference from the predetermined electric field strength value is calculated, and it is judged whether or not the difference exceeds the allowable range stored in the storage means. When the adjusting means changes the length of the specific bit string to be detected, the detection bit length is appropriately adjusted according to the change of the electric field strength without frequently changing the detection bit length by this allowable range. You can

Further, for example, when the comparing means compares the electric field strength value detected this time by the electric field strength detecting means with the electric field strength value detected last time, the electric field strength value of the electric field strength value The detection bit length can be appropriately adjusted according to changes over time.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the intermittent reception system of the present invention will be described below with reference to the drawings. 1 to 11 are diagrams showing an embodiment of the intermittent reception system of the present invention, and this embodiment is applied to a pager. First, the configuration will be described. FIG. 1 is a circuit block diagram of a pager to which an embodiment of the intermittent reception system of the present invention is applied. In FIG. 1, the pager 1 includes an antenna 2, a wireless circuit unit 3, an A / D conversion unit 4, a decoder unit 5, an ID-ROM 6, a control unit 7, and a ROM.
(Read Only Memory) 8, RAM (Random Access Memo)
ry) 9, an input unit 10, a display unit 11, a notification unit 12, and the like.

The antenna 2 receives a radio wave transmitted from a base station of a pager service company (not shown) and outputs it to the radio circuit section 3. The radio circuit unit 3 is on / off controlled by an intermittent signal input from the decoder unit 5, intermittently receives a radio wave input from the antenna 2, amplifies and demodulates the received signal, and then outputs the signal to the decoder unit 5. At the same time, the RSSi signal (which is a signal indicating a change in electric field strength) generated by the detection circuit is output to the A / D conversion unit 4.

The A / D conversion unit 4 calculates the electric field strength from the RSSi signal input from the radio circuit unit 3, converts the electric field strength into a DC (direct current) voltage, and sends it to the control unit 7 as an electric field strength signal. Output. In the case of the box-sag system, the signal received by the pager 1 has a data structure as shown in FIGS. 2 to 7.

That is, FIG. 2 shows the entire transmission signal format. In the box-sag system, the first preamble signal A successively follows 576-bit “101010”, and a plurality of preamble signals A subsequent thereto. Batch signals (batch data) B, C, ...

The preamble signal A is a signal for causing the pager 1 to recognize that data will be transmitted from now on and for synchronization, and the decoder unit 5 detects the preamble signal A and outputs the batch data B below. , C, ...
・ Recognizes that will be added in sequence. As will be described later, the pager 1 of the present embodiment adjusts the length of the detection bit string (detection bit length) extracted from the received data according to the electric field strength of the radio wave in order to detect the preamble signal A.

FIG. 3 is a diagram showing the format of the batch data B, C, ..., The data comprises a sync code SC and each code consisting of two words following the sync code SC. Each code consists of two words, one word being 32 bits. Furthermore, 1 batch is CD1-
It consists of CD8 block, each code is total,
It consists of 512 (= 32 × 2 × 8) bits.

4 and 5 show the structure of each code of the above two codewords. The address codeword shown in FIG. 4 has a message flag at the beginning, an address code after the message flag, and further, an address code. , Function bits, BCH parity, and even parity are continuous.

FIG. 5 is a message codeword,
The message flag is followed by a message code, BCH parity, and even parity.

The message flag is a flag for recognizing whether the next code is an address code or a message code. When it is "0", it is an address code word, and when it is "1", it is a message. Represents a codeword. The 2nd to 19th bits after the message flag are the address code, which corresponds to the individual calling number.

Further, there are 2 function bits after this address code, and the function bits can be used as bits for indicating a display form and a sound emission form, for example, "00", "01", "1".
It can be set with four kinds of functions by "0" and "11". In the box-sag method, one code, for example,
An error may occur inside the address code, and particularly when the reception state is bad, the demodulation of the FSK signal is not complete and an error occurs.

In order to correct this error, BCH parity is provided in bits 22 to 31 as shown in FIGS. 4 and 5, and correction is performed when an error occurs due to this 10-bit data. There is. Further, after this BCH parity, as shown in FIG. 4 and FIG.
The even parity bit is provided in bit 32. This even parity indicates whether the total number of bits from the beginning to the end represents the number of "1" was an odd number or an even number. For example, when 1 bit "0" and "1" are mistaken, Can determine whether a bit has been dropped or added by this even parity check.

In the case of the message codeword shown in FIG. 5, a message bit is inserted after the message flag. It contains a message from the caller, for example a telephone number, as well as other information. Further, BCH parity data and even parity data are added to the same codeword to form a message codeword. In the box-sag method, the power of the wireless circuit unit 3 is not always turned on, but
Powered on only when needed.

That is, one of the blocks CD1 to CD8 in one batch is assigned to each pager 1, and the power of the radio circuit unit 3 is turned on when the assigned one block is reached. . The signal for detecting the position of the assigned one block is the synchronization codeword, and the pager 1 turns on the power of the wireless circuit unit 3 only for the period of the synchronization codeword and the assigned one block. .

The preamble signal A is a signal for synchronizing the whole, and when the preamble signal A is not synchronized, the power of the radio circuit section 3 is turned on to receive the preamble signal A as well. FIG. 6 is a bit configuration diagram of a synchronous codeword, which is 0111 | 1100 | 1101 |
0010 | 0001 | 0101 | 1101 | 1000
Is the bit configuration.

When the radio circuit section 3 receives a signal of this bit structure, it receives one block from each of the subsequent blocks at the time allocated to each pager 1. The pager 1, for example, turns on the power supply of the wireless circuit unit 3 so as to be in the reception state during the time period of the synchronization code SC, and then turns off the power supply. Then, after detecting the synchronization code SC, the power supply of the wireless circuit unit 3 is turned on again during the code word of the block fitted to the frame, for example, CD2 in FIG. 3, and the address data shown in FIG. It is determined whether (individual call number) is own data (self identification number).

Then, when the received address data is not its own data, that is, when the individual call signal does not match its own identification number, the power supply of the radio circuit section 3 is turned off. When the received address data is its own data, the next message codeword is also received and that data is also fetched. In addition, pager 1
When the power is turned on for the first time, since the whole is not synchronized, the power of the radio circuit unit 3 is periodically turned on to detect the preamble signal A.

These controls are performed by the decoder unit 5. The ON / OFF control of the intermittent signal from the decoder unit 5 turns on / off the radio circuit unit 3 to perform the intermittent receiving operation. For example, when the preamble signal A can be detected and the whole is synchronized, the synchronization code SC and
When the block is assigned to one of the eight blocks CD1 to CD8, the power of the wireless circuit unit 3 is turned on to reduce the power consumption.

In the box-sag system, a word which is an idling codeword is provided in addition to the above codeword, and FIG. 7 shows the bit structure of this idling codeword. The idling codeword is a null code, and when this codeword is received, the pager 1 is in the same state as it receives no data.

For example, when the idling codeword is at the sync codeword position and is received,
If the synchronization is lost and the address codeword or the message codeword exists, it is the same as when nothing is received. The decoder unit 5 is configured as shown in FIG. 8, and includes a bit synchronization circuit 31, a BCH error correction circuit 32, a preamble detection circuit 33, a synchronization code detection circuit 34, a timing control circuit 35, a calling signal detection circuit 36, Data processing circuit 37, address processing circuit 3
8, SC mismatch counter 39 and BS signal decoder 40
And so on.

The decoder section 5 has its bit synchronization circuit 31.
The received signal is input from the radio circuit unit 3 to the bit synchronization circuit 31, and the bit synchronization circuit 31 is a circuit that corrects the disturbance of the signal of "0" and "1" with respect to the demodulation of the FSK signal and is for capturing stable data. .

The signal captured as a stable signal by the bit synchronization circuit 31 is input to the BCH error correction circuit 32, the preamble detection circuit 33 and the synchronization code detection circuit 34, and the preamble detection circuit 33 is designated by the control unit 7. Preamble signal A based on the detected bit length
Is detected and the detection result is output to the timing control circuit 35.

A bit length control signal is input to the preamble detection circuit 33 from the control unit 7, and the preamble detection circuit 33 changes the detection bit length based on the bit length control signal input from the control unit 7. Then, the preamble signal A is detected.

The preamble detection circuit 33 of this embodiment is
Preamble signal A by switching three types of detection bit length
Can be detected, and three types of detection bit lengths are prepared: 6 bits, 8 bits, and 12 bits.

When the preamble detection circuit 33 detects the preamble signal A, the synchronization code detection circuit 34 operates, the synchronization code detection circuit 34 detects whether or not the synchronization code SC is input, and the detection result is the timing control circuit 35. Output to. For example, the synchronization code detection circuit 34
When detecting the synchronization code SC, outputs a detection signal to the timing control circuit 35 and outputs the detected synchronization code SC to the SC mismatch counter 39.

The SC mismatch counter 39 counts the sync code SC input from the sync code detection circuit 34 and outputs it to the BS signal decoder 40. The BS signal decoder 40 receives the sync code SC from the control unit 7 shown in FIG. Control signal and SC
It operates based on the count signal from the mismatch counter 39, outputs an intermittent signal to the wireless circuit unit 3, and
Control, in particular, the on / off operation of the power supply.

The BCH error correction circuit 32 takes in all the data of the block allocated to itself in the batch format, judges whether or not there is a BCH error, and
Further, if there is an error, it corrects the error and outputs the corrected code to the calling signal detection circuit 36.

The calling signal detection circuit 36 is connected to the ID-ROM 6 which stores its own ID number, and the BC
When the corrected code is input from the H error correction circuit 32,
This code (individual call number) is compared with the own ID number (self identification number) stored in the ID-ROM 6, and whether or not it is the call signal of its own is detected depending on whether they match.

That is, when the received code does not match its own ID, the processing is terminated as it is, the codeword is detected again, and if it matches, the control section 7 shown in FIG. 1 is interrupted.

Therefore, the calling signal detection circuit 36 outputs a matching signal to the address processing circuit 38 when the received code matches its own ID, and the address processing circuit 38 receives the matching signal from the calling signal detection circuit 36. Then, the call detection signal is output to the control unit 7 shown in FIG. 1 to interrupt. When the call detection signal is input from the address processing circuit 38, the control unit 7 performs the processing described below.

When the received code matches with its own ID, the ringing signal detection circuit 36 receives the data thereafter, or receives the data currently received and stored in the BCH error correction circuit 22 as serial data. The data is output to the processing circuit 37, and the data processing circuit 37 collects the data serially input from the calling signal detection circuit 36 bit by bit in 8-bit units and outputs the data to the control unit 7 shown in FIG.

Further, the address processing circuit 38 outputs a control signal to the control section 7 when reception of all data is completed. That is, as described above, the received data is output to the control unit 7 in units of 8 bits, and the other 2 function bits included in the received address code are also output to the buffer of the control unit 7. The output of 2 function bits to the buffer of the control unit 7 is controlled by the address processing circuit 38.

The data processing circuit 37 also outputs the message code corrected by the address processing circuit 32 to 8
It is sorted in bit units and output to the control unit 7 as message data. The timing control circuit 35 always has a clock for detecting the timing with respect to the synchronization code SC, and the transmitting base station sequentially transmits the preamble signal A, the batch format, and a plurality of batch data. When the preamble signal A is detected, the power of the radio circuit unit 3 is turned on until the sync code SC is detected, and the power of the radio circuit unit 3 is also turned on by the code word of its own block.

When the power is turned on, the wireless circuit section 3 amplifies and demodulates the wireless signal sent from the antenna 2,
The decoder unit 5 outputs the synchronization code SC to the bit synchronization circuit 31 of the decoder unit 5, and the decoder unit 5 detects the synchronization code SC from the received signal by the bit synchronization circuit 31 and outputs the synchronization code SC to the BCH error correction circuit 32 as described above. The BCH error correction circuit 32 corrects the input data and outputs it to the call signal detection circuit 36, and the call signal detection circuit 36 detects whether or not it is its own call.

In this way, the decoder section 5 is always operating, and the timing control circuit 35 turns on / off the power of the radio circuit section 3 to reduce the power consumption of the pager 1 as a whole.

Again, in FIG. 1, the ID-ROM 6 is
Usually, the own identification number assigned by the pager service company is stored in advance, and as described above,
The decoder unit 5 compares the identification number stored in the ID-ROM 6 with the received individual calling number to determine whether or not it is its own calling.

The control unit 7 includes a CPU (Central Processing).
Unit), timer, various registers, etc., and stores various control programs, system data, etc.
An M8, a RAM 9 for storing received message data, key input data, and the like, an input unit 10, a display unit 11, and a notification unit 12 are connected. The ROM 8 stores various control programs executed by the control unit 7 and various system data, and particularly stores a detection bit length adjustment processing program in the preamble detection in the decoder 5 based on the electric field strength.

The RAM 9 is used as a work memory for the control unit 7, and stores, for example, message data received by the pager 1 and the currently set detection bit length for detecting the preamble signal A.

The control unit 7 uses the RAM 9 as a work memory according to the message data input from the decoder unit 5 and the input instruction signal input from the input unit 10 based on various control programs stored in the ROM 8. hand,
Controls each unit in the pager 1.

The control unit 7 also includes a radio circuit control unit 28, and based on the electric field intensity signal input from the A / D conversion unit 4, the preamble detection circuit 33 of the decoder unit 5 is described.
, A bit length control signal is output via the radio circuit control unit 28 to control switching of the detection bit length of the synchronization signal by the preamble detection circuit 33, and a control signal is output to the BS signal decoder 40. The on / off operation of the wireless circuit unit 3 is controlled.

The input section 10 is provided with various operation keys for controlling the output of the display contents displayed on the display section 11, a power switch, etc., and outputs instructions of each key and switch to the control section 7.

The display unit 11 is an LCD (Liquid Crystal D
isplay) 20 and a display driver 21 having a display buffer
The display driver 21 operates under the control of the control unit 7 and displays various information such as message data input from the control unit 7 and key input data input from the input unit 10.

The notification unit 12 includes the LED 22, the vibrator 23, the speaker 24, and the driver 2 for driving these.
5, 26, 27 and the like are provided, and when a call is made, the user of the pager is notified to that effect. That is, LE
The driver 25 for D22 operates under the control of the control unit 7, and turns on or blinks the LED 22 to notify the user of the pager 1 that there is a call.

The driver 26 for the vibrator 23 operates under the control of the control unit 7 and vibrates the vibrator 23 to give vibration to the user of the pager 1.
The pager 1 user is notified that there is a call.

The driver 27 for the speaker 24 is provided with a voice output circuit, a volume level control circuit, and the like, and operates under the control of the control section 7 to output a ringing sound from the speaker 24 in a loud voice to indicate that there is a call. To inform. Although not shown, the pager 1 is supplied with power from a battery power source to each unit.

Next, the operation of this embodiment will be described. The pager 1 of the present embodiment intermittently supplies / stops (turns on / off) the power supply of the wireless circuit unit 3 and intermittently receives to reduce the power consumption. The reception signal received by the radio circuit section 3 is output to the decoder section 5, and the decoder section 5 checks whether or not the reception is addressed to itself.

At this time, when the decoder unit 5 detects the calling signal in synchronization by detecting the preamble signal A with a predetermined bit length, the decoder unit 5 stores its own identification number stored in the ID-ROM 6 and the received individual signal. By checking whether the calling signals match, it is checked whether the reception is addressed to itself. Then, if the reception is addressed to itself, the power of the wireless circuit unit 3 is continuously turned on and the subsequent data is received.

However, the detection accuracy of the preamble signal A is greatly affected by the electric field strength. That is, FIG.
As shown in 2, when the electric field strength is weak, if the detection bit length is long, the power consumption is small, but the preamble signal may not be detected by the bit length, and if the incoming rate is low and the detection bit length is short, High detection rate and high power consumption, but high call arrival rate.

When the electric field strength is medium or strong, the incoming call rate is high regardless of the detection bit length, but when the detection bit length is short, detection errors increase and power consumption increases.

Therefore, in the pager 1, based on the electric field strength of the radio wave intermittently received by the radio circuit section 3,
By adjusting the detection bit length of the preamble signal A of the decoder 5, power consumption is reduced while maintaining good detection accuracy.

First, the operation of the decoder section 5 will be described with reference to FIGS.
It will be described based on. When the power of the pager 1 is turned on, first, as shown in FIG.
The ON signal is output to, the radio wave is received, the received signal is received by the decoder 5, and as shown in FIG.
A preamble search process is performed (step S1).

This preamble search process is performed in response to a search request from the timing control circuit 35 of the decoder unit 5, and the preamble signal A is 57 as described above.
Although composed of 6 bits, the preamble detection circuit 33 has a predetermined detection bit of the 576 bits (the detection bit length is set by a bit length control signal from the control unit 7 as described later). ), For example, when 8 bits continue as "10101010", it is determined that the preamble signal A is detected, and the timing control circuit 3
The detection signal is output to 5.

In this preamble search process,
During 62.5 msec, the power of the radio circuit unit 3 is turned on, and it is determined whether or not it is the preamble signal A. If it is not the preamble signal A, 106 again.
After 2.5 msec, the power of the radio circuit unit 3 is turned on, and the preamble signal search is performed again.

In the preamble search process, as described above, the power of the radio circuit section 3 is turned on at regular intervals, and it is checked whether or not the preamble signal A is detected. If the preamble signal A is detected, step S2 is executed. Performs synchronous code search processing. That is, when the detection signal indicating that the preamble signal A has been detected (preamble signal detection signal) is input, the timing control circuit 35 causes the synchronization code detection circuit 34 to start a synchronization code detection operation (synchronization code search process) ( Step S2).

The synchronization code SC is shown in FIGS. 2 and 10 (b).
, It appears immediately after the preamble signal A, and when the batch data B, C, ... Are continuous, the batch data B, C ,. It's something to lose.

Since the first preamble signal A is detected after the detection of the preamble signal A, the timing control circuit 35 operates the synchronization code detection circuit 34 immediately after the input of the preamble signal detection signal. , The synchronous code search process is performed.

When the sync code SC is detected in the sync code search process of step S2, the BCH error correction circuit 32 is made to search for and fetch the data of its own block as shown in FIG. 10 (c). Word search processing is performed (step S3). At this time, the wireless circuit unit 3
Power is on.

In this word search process, it is checked whether or not the sync code SC is missing twice (step S4). In general, there is a case where the synchronization code SC is not detected once due to noise or the like. Therefore, if the synchronization loss occurs twice, it is determined that the synchronization is out of synchronization. If the synchronization code SC is lost twice in step S4, the process returns to step S1 to perform the same process from the preamble search process.

That is, in the pager 1, if the preamble signal A is not detected or is erroneously detected when the power is turned on, for example, the detection bit length is 8 bits, and the 8-bit data of "10101010" is actually detected. Even if it is detected, if the detected data is message data or the like, the synchronization cannot be established.
In 4, the synchronization code SC is lost twice.

In step S4, the synchronization code SC is written only once.
When the sync code SC is not lost even once, it is checked whether the received individual calling signal and the own identification number match (step S5).

That is, when the BCH error correction circuit 32 takes in the data of its own block, it corrects the data and outputs it to the calling signal detection circuit 36, and the calling signal detection circuit 36 stores it in the ID-ROM 6 in advance. A process is performed to read out the self-identification number that is stored and detect whether or not the self-identification number and the received individual calling signal match.

If it is determined in step S5 that the received individual calling signal does not match the own identification number, step S5.
Returning to step 3, the same processing as the above is performed from the word search processing, and when the received individual calling signal and the own identification number match in step S5, the message is fetched (step S6).

As described above, in the pager 1, in the preamble search process, as described above, the power of the radio circuit unit 3 is turned on at regular intervals, the preamble signal A is detected, and synchronization is further established. As a result, the power of the wireless circuit unit 3 is turned on only when the block is assigned to itself, and it is checked whether or not the address is the address of itself, thereby reducing the power consumption.

However, as described above, the detection of the preamble signal A is affected by the electric field strength of the received radio wave, and when the electric field strength is weak, the detection accuracy deteriorates, and the preamble signal A is frequently erroneously detected. As a result, the power of the wireless circuit unit 3 is frequently turned on, and power consumption is unnecessarily increased.

Therefore, in the pager 1, the detection bit length of the preamble detection circuit 33 is adjusted according to the electric field strength, the preamble signal A is accurately detected, and the power consumption due to the detection error is reduced. That is, FIG.
As shown in, the control unit 7 adjusts the detection bit length of the preamble detection circuit 33 of the decoder unit 5 based on the electric field strength signal input from the wireless circuit unit 3 via the A / D conversion unit 4. There is.

The detection bit length adjusting process will be described below with reference to the flowchart shown in FIG.
The control unit 7 outputs a control signal to the BS signal decoder 40 of the decoder unit 5 to put the radio circuit unit 3 into the intermittent reception state,
The preamble signal A is detected from the decoder unit 5, and the incoming call waiting state is awaited until a signal indicating that an incoming call is input (step P1).

When the decoder unit 5 detects the preamble signal A and receives the calling signal in the waiting state for the incoming call as described above, the decoder unit 5 sends the calling detection signal to the control unit 7.
Output to. The control unit 7 checks whether this call detection signal is input from the decoder unit 5 (step P2).

When the call detection signal is input, normal incoming call processing is started (step P3), it is checked whether the incoming call processing is completed (step P4), and if message data continues, this message data is Capture (step P3). When the incoming call process is completed in step P4, a signal for turning off the power of the wireless circuit unit 3 is output to the BS signal decoder 40, and the process returns to step P1 to enter the incoming call waiting state.

In this incoming call waiting state, the decoder unit 5
When the preamble detection circuit 33 does not detect the preamble signal A and the call detection signal is not input from the decoder unit 5 in step P2, the radio wave received from the antenna 2 in the intermittent reception state causes the A / D conversion unit 4 to output the radio wave. It is periodically checked whether or not the electric field strength signal has been input (step P5). When the electric field strength signal has not been input, the process returns to step P1 and similarly waits for an incoming call.

In step P5, when the electric field strength signal is input from the wireless circuit section 3 via the A / D conversion section 4, the detection bit length of the preamble detection circuit 33 of the decoder section 5 is based on this electric field strength signal. (Step P6 ~
P9).

That is, it is checked whether or not the electric field strength value indicating the current electric field strength signal has changed from the electric field strength value indicated by the previously input electric field strength signal by exceeding a predetermined allowable range (step P6). If not, the detection bit length is not changed and the process directly returns to step P1 to wait for an incoming call.

At step P6, when the electric field strength value detected this time changes from the electric field strength value detected last time by exceeding a predetermined allowable range, whether the electric field strength value detected this time is larger than the electric field strength value detected last time. Check (step P7). When the current electric field strength value is larger than the previous electric field strength value, a setting change signal for increasing the detection bit length is output to the wireless circuit control unit 28.

That is, as described above, when the electric field strength is strong or medium, the incoming call rate is high regardless of the detection bit length. Therefore, the detection bit length is set to more accurate detection. It is controlled so as to make it longer (step P8). That is, the control unit 7 searches the RAM 9 for the currently set detection bit length and extracts the detection bit length. When the current detection bit length is 6 bits, 8 bits are added to 8 bits.
In the case of a bit, the change control signal for changing the setting detection bit length is output to the wireless circuit control unit 28, while in the case of 12 bits, the change control signal for changing the set detection bit length is output.

In step P7, when the current electric field strength value is smaller than the previous electric field strength value, the control section 7 outputs a setting change signal for shortening the detection bit length to the radio circuit control section 28. .

That is, as described above, when the electric field strength is weak, if the detection bit length is short, detection errors increase and power consumption increases, but the incoming rate is high, and if the detection bit length is long, the preamble is large. The signal cannot be detected by the set bit length, power consumption is low, and the incoming call rate is low, so control is performed to shorten the detected bit length in order to prevent incoming call leakage at the expense of power consumption. (Step P9).

Therefore, the control unit 7 searches the RAM 9 for the currently set detection bit length and takes it out, and if the current detection bit length is 12 bits, it is set to 8 bits and 8 bits.
In the case of bits, the change control signal for changing the setting detection bit length to 6 bits is output to the wireless circuit control unit 28, while in the case of 6 bits, it is left unchanged.

When the change control signal is input from the control unit 7, the radio circuit control unit 28 outputs a bit length control signal to the preamble detection circuit 33 of the decoder unit 5 based on this change control signal, and the preamble detection circuit 33, based on the bit length signal input from the radio circuit control unit 28,
Change / set the detection bit length.

As described above, when the control section 7 outputs the change control signal to the radio circuit control section 28 to change the detection bit length, the control section 7 returns to step P1 and waits for an incoming call.

Therefore, the pager 1 shortens the detection bit length of the preamble signal A when the electric field strength is weak so that an appropriate incoming call can be made, and when the electric field strength is medium or strong, the preamble signal is high. Signal A
While increasing the detection bit length of to maintain proper incoming call,
Power consumption is reduced.

As described above, according to the present embodiment, the pager 1 receives a radio signal at a constant cycle and detects a specific bit string from the digital data demodulated from the received signal, so that only the radio signal of its own frame is received. When receiving the signal, the wireless circuit section 3 and A /
The D conversion unit 4 detects the electric field strength value of the radio signal, compares the detected electric field strength with the electric field strength value detected last time by the control unit 7 which is a comparison means, and based on the comparison result, the detection bit is detected. The length of the detection bit string of the preamble detection circuit 33 is adjusted by the radio circuit control unit 28 that is an adjusting unit.

Therefore, the preamble detection bit length can be changed according to the electric field strength of the radio wave, good reception can be performed, and the power consumption can be reduced.

Further, according to the present embodiment, since the detected bit length is changed by comparing the electric field strength value detected this time with the electric field strength value detected the previous time, the electric field strength value changes with time. The detection bit length can be appropriately adjusted according to the above.

In the above embodiment, the electric field strength is detected by extracting the electric field strength from the radio wave received by the radio circuit unit 3 and performing A / D conversion. The present invention is not limited to this, and any one can be used as long as it can appropriately detect the electric field strength of the received radio wave.

In the above embodiment, the case where the detection bit length of the preamble signal A in the decoder unit 5 is changed in three steps has been described, but the detection bit length is not limited to these. is not.

Further, in the above embodiment, the strength of the electric field strength is determined by comparing the magnitude of the electric field strength value detected this time with the magnitude of the value of the electric field strength detected last time. The determination of the strength is not limited to this. For example, the electric field strength value of a predetermined strength is stored in the RAM or the like, and the electric field strength value of the predetermined strength is compared with the detected electric field strength value. You may do it.

Further, the detection bit length is changed only when the difference between the electric field strength value detected this time and the predetermined electric field strength value, for example, the electric field strength value detected last time, exceeds the predetermined allowable range. May be. In this case, the value of this allowable range is stored in the RAM 9 or the like. By doing so, the detection bit length can be appropriately adjusted according to the change over time of the electric field strength value.

[0104]

According to the notification method of the invention described in claim 1, by receiving a radio signal at a constant cycle and detecting a specific bit string from the digital data demodulated from the received signal, only the radio signal of its own frame is detected. When receiving the signal, the electric field strength detecting means detects the electric field strength value of the wireless signal, the comparing means compares the detected electric field strength value with a predetermined electric field strength value, and based on the comparison result, a detection bit is detected. The adjusting means adjusts the length of the specific bit string detected from the digital data.

Therefore, the detection bit length for detecting the preamble signal can be changed according to the electric field strength of the radio wave, the preamble can be accurately detected, and the power consumption due to the detection error can be reduced. be able to.

In this case, when the detected electric field strength value is larger than the predetermined electric field strength value, the detection bit adjusting means lengthens the length of the specific bit string to be detected by a predetermined bit, When the detected electric field strength value is smaller than the predetermined electric field strength value, the length of the specific bit string to be detected is shortened by a predetermined bit, whereby the preamble can be accurately detected.

Further, as described in claim 3, the allowable range of the difference between the detected electric field strength value and the predetermined electric field strength value is stored in the storage means, and the comparing means stores the detected electric field strength value and the predetermined electric field strength value. The difference from the electric field strength value is calculated, and it is judged whether or not the difference exceeds the allowable range stored in the storage means,
Only when it is determined that this difference exceeds the allowable range, the detection bit adjusting means changes the length of the specific bit string to be detected, without changing the detection bit length frequently by this allowable range, The detection bit length can be appropriately adjusted according to the change in the electric field strength.

Further, as described in claim 4, when the comparing means compares the electric field strength value detected this time by the electric field strength detecting means with the electric field strength value detected last time, the electric field strength value changes with time. The detection bit length can be appropriately adjusted according to such changes.

[Brief description of drawings]

FIG. 1 is a circuit block diagram of a pager to which an embodiment of an intermittent reception system of the present invention is applied.

FIG. 2 is a diagram showing a format of a transmission signal.

FIG. 3 is a diagram showing a format of batch data of the transmission signal of FIG.

FIG. 4 is a diagram showing address codewords of the transmission signal of FIG. 2;

5 is a diagram showing a message codeword of the transmission signal of FIG.

FIG. 6 is a diagram showing a synchronization codeword of the transmission signal of FIG.

7 is a diagram showing an idling codeword of the transmission signal of FIG. 2;

FIG. 8 is a detailed circuit block diagram of a decoder unit in FIG.

9 is a flowchart showing a receiving operation by the decoder unit of FIG.

10 is a diagram showing power-on / off timing (a) in the preamble search process of FIG. 9, sync code search timing (b) in the sync code search process, and word search timing (c) in the word search process. .

11 is a flowchart showing a detection bit length adjustment process by the control unit of FIG.

FIG. 12 is a diagram showing the state of changes in the incoming call rate and current consumption according to the electric field strength and the preamble detection bit length.

[Explanation of symbols]

 1 pager 2 antenna 3 wireless circuit section 4 A / D conversion section 5 decoder section 6 ID-ROM 7 control section 8 ROM 9 RAM 10 input section 11 display section 12 notification section 20 LCD 21 display driver 22 LED 23 vibrator 24 speaker 25, 26, 27 driver 28 wireless control unit 31 bit synchronization circuit 32 BCH error correction circuit 33 preamble detection circuit 34 synchronization code detection circuit 35 timing control circuit 36 call signal detection circuit 37 data processing circuit 38 address processing circuit 39 SC mismatch counter 40 BS signal decoder

Claims (4)

[Claims] 1. In an intermittent reception system for receiving only a radio signal of its own frame by detecting a specific bit string from digital data demodulated from the received signal by receiving a radio signal at a fixed cycle, an electric field strength detecting means is used. The electric field strength value of the radio signal is detected, the electric field strength value detected by the electric field strength detecting means is compared with a predetermined electric field strength value by the comparing means, and based on the comparison result, by the detection bit adjusting means. An intermittent receiving system characterized by adjusting the length of the specific bit string detected from the digital data. 2. The detection bit adjusting means lengthens the length of the specific bit string to be detected by a predetermined bit when the detected electric field strength value is larger than the predetermined electric field strength value, and detects the electric field strength value. 2. The intermittent reception system according to claim 1, wherein the length of the specific bit string to be detected is shortened by a predetermined bit when is smaller than the predetermined electric field strength value. 3. An allowable range of the difference between the detected electric field strength value and the predetermined electric field strength value is stored in a storage means, and the comparing means stores the electric field strength value detected by the electric field strength detecting means and the predetermined value. The difference between the electric field strength value and the electric field strength value is determined to determine whether the difference exceeds the allowable range stored in the storage means, the detection bit adjustment means, the comparison means, the difference is The intermittent reception method according to claim 1 or 2, wherein the length of the specific bit string to be detected is changed only when it is determined that the allowable bit range is exceeded. 4. The comparing means compares the electric field strength value detected this time by the electric field strength detecting means with the electric field strength value detected last time as the predetermined electric field strength value. Item 4. The discontinuous reception method according to any one of items 3.