JPH08204988A - Horizontal output pulse generation circuit - Google Patents

Abstract

PURPOSE: To prevent the breakdown of the horizontal output transistor of a poststage by supplying the output signals of a phase shift circuit and a third frequency division output signal to an OR gate and obtaining horizontal output pulses. CONSTITUTION: This circuit is provided with a horizontal count-down circuit 20 for generating first-third frequency division output signals X, Y and Z provided with a horizontal synchronizing signal cycle in synchronism with horizontal synchronizing signals from an outside and the OR gate 21. Then, when the output signals of the phase shift circuit 6 are not impressed to a horizonal driving circuit 10, the third frequency division output signal Z from the horizontal count-down circuit 20 is supplied to the OR gate 21 and pseudo horizontal output pulses are outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a horizontal output pulse generation circuit of a horizontal deflection circuit used in a TV receiver, a computer display or the like, and more particularly to a horizontal output pulse generation circuit which prevents destruction of horizontal output transistors.

[0002]

2. Description of the Related Art In a horizontal deflection circuit used in a TV receiver, a computer display, etc., a horizontal output pulse is generated in accordance with a horizontal synchronizing signal, and a horizontal deflection coil is driven in accordance with the horizontal output pulse to perform a horizontal deflection operation. Is going. Figure 2
Shows such a horizontal deflection circuit, in which the horizontal synchronizing signal is separated from the video signal applied to the input terminal (1) by the synchronizing separating circuit (2) and applied to the AFC1 circuit (3). The AFC1 circuit (3) consists of a phase comparator and LPF.
It is composed of Horizontal oscillator (4) is 32fH
It oscillates at a frequency of (fH is a horizontal synchronizing signal frequency), and its frequency and phase are controlled by the output signal of the AFC1 circuit (3). Horizontal countdown circuit (5)
Is composed of a plurality of T-type flip-flops connected in cascade and a logic circuit, and divides the clock signal of 32 fH frequency from the horizontal oscillator (4) to obtain various timings and pulses at the horizontal synchronizing signal frequency. Generates a width-divided output signal.

The frequency-divided output A of the horizontal synchronizing signal frequency from the horizontal countdown circuit (5) is applied to the AFC1 circuit (3), and the AFC1 circuit (3), horizontal oscillator (4), and horizontal countdown circuit (5) are used. One AFC loop is constructed. Therefore, the horizontal countdown circuit (5) generates each frequency-divided output signal locked to the horizontal sync signal from the sync separation circuit (2).

The frequency-divided outputs B and C of the horizontal synchronizing signal frequency from the horizontal countdown circuit (5) are supplied to the phase shift circuit (6).
Applied to the first and second phase shift circuits (7) and (8) therein to produce horizontal output pulses. By adjusting the output signal phases of the first and second phase shift circuits (7) and (8), the inversion timing of the flip-flop circuit (9) changes and the phase of the output pulse changes.

The output signal of the phase shift circuit (6) is applied to the horizontal drive circuit (10) as a horizontal output pulse, and the horizontal drive circuit (10) causes a horizontal output transistor (not shown) in the horizontal output circuit (11). ) Is driven and a horizontal deflection current flows through a horizontal deflection coil (not shown) of the cathode ray tube (12). In addition, a part of the output of the horizontal output circuit (11) is applied to the high voltage circuit (13) to supply a high voltage DC voltage to the cathode ray tube (12) and the horizontal FBP.
(Flyback pulse) is generated.

The horizontal FBP is connected to the A terminal via the terminal (14).
It is applied to FC2 (15) and compared in phase with the frequency divided output D of the horizontal synchronizing signal frequency from the horizontal countdown circuit (5). The AFC2 (15) has the same configuration as the AFC1 (3). The output signal of the AFC2 (15) is the first and second phase shift circuits (7) and (8) in the phase shift circuit (6).
And the output signal phases of the first and second phase shift circuits (7) and (8) are adjusted, the inversion timing of the flip-flop circuit (9) changes and the phase of the output pulse changes. .

The AFC2 circuit (15) is a phase shift circuit (6).
The phase of the horizontal output pulse, which is the output signal of, is matched with the phase of the horizontal FBP. Therefore, the horizontal deflection circuit shown in FIG. 2 can generate a horizontal output pulse according to the horizontal synchronizing signal and drive the horizontal deflection coil according to the horizontal output pulse to perform the horizontal deflection operation.

[0008]

By the way, in a horizontal deflection circuit of a television receiver or a computer display using a cathode ray tube, a surge due to discharge in the tube is applied to an IC substrate in the equipment. Even if the surge is applied, the horizontal deflection circuit is applied. The horizontal output pulse within must be generated correctly. However, in the horizontal deflection circuit of FIG. 2, a horizontal output pulse may not be correctly generated due to a surge.

Although the entire horizontal deflection circuit is affected by the surge, the flip-flop circuit (9) that determines the phase of the horizontal output pulse is particularly susceptible. For example, if the pulse width of the horizontal output pulse is short due to the influence of a surge, a high voltage is generated in the horizontal output transistor whose load is the coil, and the horizontal output transistor is destroyed when the next horizontal output pulse is applied. There was a fear that

The situation will be described with reference to FIG. Now, the output signals of the first and second phase shift circuits (7) and (8) are as shown in FIG.
3A and 3B, assuming that the flip-flop circuit (9) performs the falling operation, the Q output of the flip-flop circuit (9) is as shown in FIG. 3C. FIG. 3C shows the case where a normal signal is output as a horizontal output pulse. Here, it is assumed that a surge occurs at the second fall of FIG. 3A, that is, near time t1. Then, the flip-flop circuit (9) may cause an abnormal operation in response to the surge, and the waveforms shown in FIGS. 3D and 3E may be generated. In the case of FIG. 3D, one horizontal output pulse is not generated. In this case, since the frequency of the horizontal output pulse becomes low and the timing of turning on the horizontal output transistor is delayed, the horizontal output transistor may be destroyed when the next horizontal output pulse is applied.

In the case of FIG. 3 (e), the pulse width of the horizontal output pulse becomes narrow. In this case, the horizontal output transistor may be destroyed when the next horizontal output pulse is applied for the above reason.

[0012]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and generates first to third frequency division output signals having a horizontal synchronizing signal period in synchronization with a horizontal synchronizing signal from the outside. A horizontal countdown circuit, a flip-flop circuit that is inverted by the first and second frequency-divided output signals, a phase-shift circuit that shifts the output signal in accordance with a control signal, and the third frequency-divided output signal. An OR gate to which the output signal of the phase shift circuit is applied, and a horizontal output pulse is obtained from the OR gate.

[0013]

According to the present invention, a horizontal countdown circuit for generating a third divided output signal having a horizontal synchronizing signal period in synchronization with a horizontal synchronizing signal from the outside and an OR gate are provided, and the output signal of the phase shift circuit is horizontal. When the voltage is not applied to the drive circuit, the third frequency-divided output signal from the horizontal countdown circuit is output as a pseudo horizontal output pulse, so that the horizontal output transistor in the subsequent stage is not damaged.

[0014]

FIG. 1 shows a horizontal output pulse generation circuit according to the present invention, in which (20) is a first to a third divided output signal (in synchronization with an external horizontal synchronization signal and having a horizontal synchronization signal cycle). Horizontal countdown circuit for generating (X, Y, Z),
(21) is the third frequency division output signal Z and the phase shift circuit (6)
Is an OR gate to which the output signal of and is applied.

In FIG. 1, the same circuit elements as those in FIG. 2 are designated by the same reference numerals and the description thereof will be omitted. The first and second frequency division output signals (X, Y) of FIG. 1 are equal to the frequency division outputs B and C of the horizontal synchronizing signal frequency of FIG.
Now, assuming that both the AFC1 circuit (3) and the AFC2 circuit (15) are operating correctly, the horizontal countdown circuit (20) outputs the first and second frequency division output signals (X, Y).
Occurs. The first and second frequency division output signals (X, Y)
Has the waveforms shown in FIGS. 3 (a) and 3 (b), and the Q output of the flip-flop circuit (9) is as shown in FIG. 3 (c). FIG. 3C shows the case where a normal signal is output as a horizontal output pulse.

Here, it is assumed that a surge occurs at the second fall of FIG. 3A, that is, near time t1. Then
There is a possibility that the flip-flop circuit (9) may cause an abnormal operation in response to the surge to generate the waveforms shown in FIGS. 3 (d) and 3 (e). However, in FIG. 1, the third frequency-divided output signal (Z) is generated from the horizontal countdown circuit (20). The third divided output signal (Z) has a waveform shown in FIG. 3 (f) and is applied to the horizontal drive circuit (10) via the OR gate (21).

Therefore, even if the waveforms shown in FIGS. 3 (d) and 3 (e) occur around time t1 and a sufficient horizontal output pulse cannot be obtained, the pseudo horizontal output pulse shown in FIG. 3 (f) is generated. Can be supplied to the subsequent circuit. Therefore, the pseudo horizontal output pulse of FIG. 3 (f) in which a high voltage is not generated in the horizontal output transistor having the coil as a load is thicker than the pulse width of the regular horizontal output pulse shown in FIG. 3 (c). In this case, since the normal operation is hindered, the pulse width is made narrower than the regular horizontal output pulse shown in FIG. 3C so that the horizontal output transistor is not destroyed.

FIG. 4 shows a method of setting the generation timing of the pseudo horizontal output pulse of FIG. 3 (f).
3A shows the case where the pulse in FIG. 3C is shifted to the maximum on the left side, and FIG. 4B shows the case where the pulse in FIG. 3C is shifted to the maximum to the right side. FIG.
It is a logical product of (a) and FIG. If it exists in this range, the operation of the AFC2 circuit (15) can be continued without adversely affecting the operation.

[0019]

As described above, according to the present invention, a horizontal countdown circuit for generating a third divided output signal having a horizontal synchronizing signal period in synchronization with a horizontal synchronizing signal from the outside and an OR gate are provided, and the horizontal countdown circuit is provided. Since the third frequency-divided output signal from the countdown circuit is output as a pseudo horizontal output pulse, there is no fear that the horizontal output transistor in the subsequent stage will be destroyed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a horizontal output pulse generation circuit of the present invention.

FIG. 2 is a circuit diagram showing a conventional horizontal output pulse generation circuit.

FIG. 3 is a waveform diagram for explaining the operation of FIG.

FIG. 4 is a waveform diagram for explaining the operation of FIG.

[Explanation of symbols]

 (6) Phase shift circuit (20) Horizontal countdown circuit (21) OR gate

Claims (2)

[Claims] 1. A horizontal countdown circuit for generating first to third frequency-divided output signals having a horizontal synchronizing signal period in synchronization with a horizontal synchronizing signal from the outside, and an inversion by the first and second frequency-divided output signals. A phase shift circuit having a flip-flop circuit, the output signal of which shifts the phase in response to a control signal; and an OR gate to which the third frequency division output signal and the output signal of the phase shift circuit are applied, A horizontal output pulse generation circuit, wherein a horizontal output pulse is obtained from the OR gate. 2. A signal having a pulse width obtained by ANDing a maximum variable phase output signal in one direction of the phase shift circuit and a maximum variable phase output signal in the other direction of the phase shift circuit as the third frequency division output signal. 2. The horizontal output pulse generation circuit according to claim 1, wherein the horizontal output pulse generation circuit is generated by a horizontal countdown circuit.