JPH08204681A - Redundant system path monitor - Google Patents

Abstract

PURPOSE: To prevent occurrence of errorneous path alarm at changeover of a clock supply section without extending a scale of a transmitter even when number of contained transmission lines is increased in the redundant system path monitor monitoring a path of a cross connect section of the transmitter having a redundant system. CONSTITUTION: A 1st prescribed pattern and a 2nd prescribed pattern are inserted alternately to a transmission signal by a prescribed timing signal and the result is outputted to a confirmation means 4. The confirmation means 4 confirms the accurate arrival of a transmission signal based on the pattern inserted to the transmission signal to confirm it that occurrence of a path error in the transmission line is not caused. A timing signal generating means 5 is provided with a redundant configuration and when the active means is switched to the standby means, a mask signal generating means 6 generates a mask signal over a prescribed time from the switching point of time and a confirmation inhibit means 7 inhibits a confirmation operation of the confirmation means 4 while the means 7 receives a mask signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a redundant system path monitoring apparatus for monitoring paths in a cross-connect section of a transmission apparatus having a redundant system, and more particularly to a redundant configuration of a cross-connect section for line setting in a synchronous digital transmission apparatus. Further, the present invention relates to a redundant path monitoring device that monitors whether there is an abnormality in each of the working and protection paths of the cross-connect unit.

In recent years, SDH (Synchronous Digital Hierarchy) has been provided which defines an interface for effectively multiplexing various high speed services and existing low speed services. This SDH makes it possible to create a high-speed synchronous network by introducing the concept of pointers.
As a result, it becomes possible to freely access the required time slot in the multiplexed pulse train. The present invention particularly relates to a redundant path monitoring device in such an SDH transmission device.

[0003]

2. Description of the Related Art FIG. 6 shows one configuration example of an SDH transmission system. That is, the switch 1 is installed in the module C101.
02-105 are connected, the exchanges 107-110 are connected to the module C106, and the module C101 is connected.
And the module C106 are connected via the module B112. The module C converts the interface of the existing digital exchange and the interface of the existing digital transmission device into an SDH interface, and multiplex-converts the existing low speed signal into a high speed signal (for example, 52 Mb / s). The module B also cross-connects SDH information signals. That is, it fulfills the functions of focusing, separating, and refilling paths between a plurality of transmission lines. The path here is set between transmission nodes as a logical path for carrying information without depending on a service, and a virtual container corresponds to this in SDH. Module B1
12, module C101 and module C106
Between 0 and 1, transmission lines of 0-system and 1-system having a redundant configuration are respectively provided. The redundant path monitoring device according to the present invention is
Configured in module B112. In place of the module C106 and the exchanges 107 to 110, SD
You may make it connect the module A which performs the long distance optical relay transmission of H information signal.

FIG. 7 shows the internal structure of a conventional module B112. That is, the input-side 0-system interface unit 113 including # 1 to #N and the input-side 1-system interface unit 116 including # 1 to #N are connected to the module C101 of FIG. The output-side 0-system interface section 115 and the output-side 1-system interface section 118 including # 1 to #N are connected to the module C106 in FIG. 0-line setting section 114 and 1
The system line setting unit 117 includes the 0 system interface unit 11
The 3rd and 1st system interface section 116, the 0th system interface section 115, and the 1st system interface section 118 are connected. Also, the clock supply unit has a redundant configuration,
The 0-system clock supply unit 119 and the 1-system clock supply unit 120, which are in an asynchronous relationship with each other, are
21 is connected. The reference pulse generator 121 includes a selector 121a and a frame pulse generator 121b,
The selector 121a selects the clock signal from the 0-system clock supply unit 119 or the clock signal from the 1-system clock supply unit 120 according to the instruction of the clock system switching unit 122, and sends it to the frame pulse generation unit 121b. The frame pulse generation unit 121b generates a frame pulse (FP) based on the transmitted clock signal, and together with the clock signal, each interface unit 113, 115, 116, 1
18 and the line setting units 114 and 117.

A conventional redundant system path monitoring device provided in the module B112 as described above will be described with reference to FIG. Reference numerals 113a, 115a, 116a, 11 in the figure
Reference numeral 8a denotes a 0-system interface unit 113, a 0-system interface unit 115, a 1-system interface unit 116, and a 1-system interface unit 118, which are # 1 to #N, respectively.
Each one of these. 0 system interface section 113a
Is provided with an FTS insertion unit (FTSINS) 113b, and the FTS insertion unit 113b is provided with a first predetermined pattern (0) in the FTS (vacant) area of a signal transmitted through the 0-system path.
P) and an inverted pattern (* 0P) of this pattern. These patterns are fixed patterns. The insertion procedure will be described with reference to FIG.
13b is 0P, every 1/4 cycle of the frame pulse at the input timing of the frame pulse [FP; FIG. 9 (A)].
0P, * 0P and * 0P are inserted into the FTS area in this order [Fig. 9 (B)]. The FTS area is an unnecessary SOH (Section Over Head) area that becomes unnecessary after the termination of the 0-system interface 113.

Returning to FIG. 8, similarly, the FTS insertion unit (FTSINS) 11 is provided in the 1-system interface unit 116a.
6b is provided, and the FTS insertion unit 116b has a second predetermined pattern (1P) and an inverted pattern (* 1P) of this pattern in the FTS area of the signal transmitted by the 1-system path.
Insert. The second predetermined pattern (1P) is a fixed pattern different from the first predetermined pattern (0P). This insertion procedure is also as shown in FIG. 9C, at every 1/4 cycle of the frame pulse at the input timing of the frame pulse,
1P, 1P, * 1P, * 1P are inserted in the FTS area in this order.

Returning to FIG. 8, the 0-system line setting section 114 is provided with a 0-system first confirming section (FTSCHK1) 114a and a 1-system first confirming section (FTSCHK1) 114b. A 0-system signal is sent from the 0-system interface section 113a to the confirmation section 114a, and the first confirmation section 1
A 14-system signal is sent from the 1-system interface section 116a to 14b. The first confirmation unit 114a detects a pattern included in the FTS area of the 0-system signal based on the frame pulse, and if it is 0P, 0P, * 0P, * 0P, normal transmission is performed. The selector (S
(EL) 114c and the line setting unit 114d send a 0-system signal. Similarly, the first confirmation unit 114b also detects a pattern included in the FTS region of the 1-system signal on the basis of the frame pulse, and if it is 1P, 1P, * 1P, * 1P, it is normal. Selector 1 is determined to be transmitting
The system 1 signal is sent to 14c and the line setting unit 114d.

Selector 114c and line setting unit 114
d alternately selects the patterns included in each FTS area of the transmitted 0-system and 1-system signals and inserts them into the FTS area of the signal of the current system of the 0-system and 1-system. And sends it to the second confirmation unit (FTSCHK2) 114e. This alternate selection and insertion, as shown in FIG. 9D, is 1 / of the frame pulse at the input timing of the frame pulse.
Every 4 cycles, the first pattern 0P in the FTS area of the 0-system signal, the second pattern 1P in the FTS area of the 1-system signal, the third pattern * 0P in the FTS area of the 0-system signal The fourth pattern * 1P of the FTS area of the 1-system signal is selected, and the FTS of the 0-system or 1-system working signal is selected.
Inserted in the area. However, since the line setting unit 114d has a memory, when outputting from the line setting unit 114d,
The inserted pattern is delayed by 1/4 cycle of the frame pulse. In this way, the pattern shown in FIG. 9D is transmitted to the second confirmation unit 114e.

The second confirmation section 114e, at the input timing of the frame pulse, every ¼ cycle of the frame pulse,
* 1P, 0P, 1P, * 0P are spontaneously generated in this order [FIG. 9 (E)], and these are respectively compared with the patterns inserted in the FTS area of the signal sent from the line setting unit 114d. If they match each other, it is determined that normal transmission is performed, and the signal is transmitted to the 0-system interface unit 1
15a and 1-system interface section 118a.

The 1-system line setting section 117 has the same configuration as the 0-system line setting section 114. The 0-system interface unit 115a includes a third confirmation unit (FTSCHK3) 115.
b is provided, and the second confirmation unit 1 of the 0-system line setting unit 114 is provided.
The signal from 14e and the signal from the second confirmation section of the 1-system line setting section 117 are input. Third confirmation unit 115b
Is configured to include two sets of the same configuration as the second confirmation unit 114e, and each can perform the same operation as the second confirmation unit 114e and confirm that normal transmission is performed. There is. Similarly, the 1-system interface unit 118a
Also, the third confirmation unit (FTSCHK3) 118b is provided, and the signal from the second confirmation unit 114e of the 0-system line setting unit 114 and the signal from the second confirmation unit of the 1-system line setting unit 117 are normal. You can confirm that it is being transmitted to.

[0011]

By the way, the 0-system clock supply section 119 and the 1-system clock supply section 120 shown in FIG.
Is not synchronized as described above, the frame pulse generated by the frame pulse generation unit 121b based on the clock signal from the 0-system clock supply unit 119 (see FIG. 10).
(A)] and the frame pulse generated based on the clock signal from the 1-system clock supply unit 120 [FIG.
There is a deviation from the phase of (B)]. Therefore,
For example, when the working 0-system clock supply unit 119 has an abnormality and is switched to the spare 1-system clock supply unit 120 based on the selection (SEL) signal [FIG. 10 (C)], the frame pulse generation unit 121b The frame pulse generated in step (1) is as shown in FIG. That is, initially, FIG.
The same thing as the frame pulse shown in (A) is generated, and thereafter, the free-running frame pulse 123 may be generated before switching to the same frame pulse as shown in FIG. 10 (B). This is the frame pulse generator 121.
Since b is provided with a free-running counter that counts up in a frame cycle to generate a frame pulse, a frame based on the clock signal from the 1-system clock supply unit 120 after the selection (SEL) signal is input. Pulse 12
This is because, if the free-running counter counts up before 4 is generated, the free-running frame pulse 123 is generated.

The FTS inserting section 1 of the 0-system interface section 113a which receives the frame pulse shown in FIG.
As described above, 13b indicates 0P, 0P, every 1/4 cycle of the frame pulse at the input timing of the frame pulse.
Insert * 0P and * 0P in this order in the FTS area [Fig. 1
0 (E); in this figure, the description of “P” is omitted and “* 0” is described as “0 *”]. In particular,
Even when the frame pulse 124 is input immediately after the input of the free-running frame pulse 123, this insertion is performed, so that “·· 0 *, 0, 0,
The insertion form is "0, 0 *, ...".

Similarly, the insertion mode of the FTS insertion section 116b of the 1-system interface section 116a receiving the frame pulse shown in FIG. 10D is also shown in FIG. 10F (the illustration of "P" is omitted in this figure as well). And "* 1" to "1 *"
(Notated)), self-propelled frame pulse 1
When inputting 23, "・ ・ 1 *, 1,1,1,1 *, ・ ・"
It is in the form of insertion.

The second confirmation section (F of the 0-system line setting section 114)
As described above, the TSCHK2) 114e is the first pattern 0 of the FTS area of the 0-system signal at every 1/4 cycle of the frame pulse at the input timing of the frame pulse.
The second pattern 1 in the FTS area of P and 1 system signals
Third pattern * 0 in FTS area of P, 0 system signal
Fourth pattern * 1 in the FTS area of P and 1 system signals
Select P and delay by 1/4 cycle of the frame pulse to 0
It is inserted in the FTS region of the system or system 1 signal. In particular, immediately after the input of the free-running frame pulse 123, the frame pulse 1
Even when 24 is input, since this selection and insertion are performed, "... 0 *, 1 *, 0, 0, 1, 0 *" as shown by broken line arrows in FIGS. , ... "are selected.

On the other hand, in the second confirmation section 114e, as described above, * 1P, 0P, 1P, * 0P are spontaneously generated in this order at every 1/4 cycle of the frame pulse at the frame pulse input timing. I am letting you. In particular, even when the frame pulse 124 is input immediately after the input of the free-running frame pulse 123, this generation is performed.
As shown in (G), "... 0 *, 1 *, 1 *, 0, 1,
0 *, ... ".

Therefore, as a result of the comparison in the second confirmation section 114e, a mismatch of "0" and "1 *" occurs when the frame pulse 124 is input [FIG. 10 (H)]. The second confirmation unit 114e has been described above, but the second confirmation unit (FTSCHK2) of the line 1 line setting unit 117 has been described.
Alternatively, each third confirmation unit (FTSCHK3) of the 0-system interface unit 115a and the 1-system interface unit 118a.
The same thing occurs in 115b and 118b.

The result of this comparison is monitored by a monitoring unit (SV
Section), and is recognized as a 0-system path alarm based on the position where the mismatch occurs [FIG. 10 (I)]. In other words, even if the clock supply unit is simply switched from the working mode to the standby mode and there is no abnormality in the path, a path alarm is generated due to the switching of the clock supply unit, and as a result, the path switching is performed. There was a problem of being broken.

In order to prevent the occurrence of such an erroneous path alarm, as shown in FIG.
(H)] is notified to the monitoring unit via the alarm protection circuit 125 having three stages of rear protection. That is, the comparison result is sent to the D-FFs 125a to 125c connected in series, and the monitoring timing of a half of the frame pulse period is sent as a clock signal to the D-FFs 125a to 125c, so that the D-FFs 125a to 125c receive the monitoring timing. Each output is added to the AND circuit 125d so that when the disagreement continuously occurs three times in the same system, it is determined that the system has an abnormality.

However, such an alarm protection circuit 125
Since each is provided for each path, the number of alarm protection circuits installed increases as the number of accommodated transmission paths increases, which causes a drawback of increasing the cost of the transmission device.

The notification of the comparison result to the monitoring unit is
Normally, it is performed only every polling cycle of several tens of ms, and the frame pulse cycle is 1 ms or less. Therefore, it is impossible for the monitoring unit to mask the above comparison result based on the switching information of the clock supply unit. It was

The present invention has been made in view of such a point, and even if the number of accommodated transmission paths is increased, an erroneous path alarm is generated at the time of switching the clock supply section without expanding the scale of the transmission apparatus. It is an object of the present invention to provide a redundant system path monitoring device that is intended to prevent the occurrence.

[0022]

In order to achieve the above object, the present invention, as shown in FIG. 1, inserts a first predetermined pattern into a signal transmitted through a 0-system path. Means 1 and second predetermined pattern inserting means 2 for inserting the second predetermined pattern into the signal transmitted through the 1-system path
And a signal transmitted by the 0-system path and a signal transmitted by the 1-system path, the first predetermined pattern and the second predetermined pattern respectively inserted in these signals are alternately changed with a predetermined timing signal. The signals transmitted through the 0-system path or 1 are extracted from these alternating patterns.
Alternate pattern insertion output means 3 for inserting and outputting the signal transmitted through the system path, and a signal sent from the alternating pattern insertion output means 3 to take out the pattern inserted in the signal, and alternate each pattern Confirming means 4 for confirming that the incoming call is correct, redundant timing signal generating means 5 for generating at least the above-mentioned predetermined timing signal, and predetermined timing from the switching point of the redundant configuration of the timing signal generating means 5. And masking signal generating means 6 for generating a masking signal for a period of time, and confirmation inhibiting means 7 for inhibiting the confirming operation of the confirming means 4 while receiving the masking signal and receiving the masking signal. A redundant path monitoring device is provided.

[0023]

In the above structure, the first predetermined pattern inserting means 1 inserts the first predetermined pattern into the signal transmitted by the 0-system path, and the second predetermined pattern inserting means 2 The second predetermined pattern is inserted into the signal transmitted through the 1-system path and sent to the alternate pattern insertion output means 3. The alternate pattern insertion / output means 3 alternately takes out the first predetermined pattern and the second predetermined pattern inserted in the respective sent signals at predetermined timing signals, and outputs each of these taken out alternate patterns. It is inserted into the signal transmitted through the system path or the signal transmitted through the system path 1 and output to the confirmation means 4.

Alternate pattern insertion output means 3 and confirmation means 4
Since there is a possibility that a path abnormality will occur in the transmission path between and, the confirmation means 4 receives the signal sent from the alternating pattern insertion output means 3, takes out the pattern inserted in the signal, and alternates each pattern. It confirms that the pattern is received correctly, and confirms that no path abnormality has occurred in the transmission path.

The timing signal generating means 5 has a redundant structure and generates at least the above-mentioned predetermined timing signal. When the timing signal generating means 5 is switched from the working mode to the standby mode, the mask signal generating means 6 generates a mask signal for a predetermined time from the switching time point and sends it to the confirmation prohibiting means 7. The confirmation inhibiting means 7 inhibits the confirming operation of the confirming means 4 while receiving the mask signal.

As a result, the timing signal generating means 5
It is possible to mask an erroneous path alarm generated at the time of switching, and in such a configuration, only one set of the timing signal generating means 5, the mask signal generating means 6, and the confirmation inhibiting means 7 need be provided in the transmission device. Even if the number of accommodated transmission lines increases, the scale of the transmission device is not affected.

[0027]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram of an embodiment of the path monitoring device. The configuration of this embodiment is basically the same as the configurations of the module B and the path monitoring device shown in FIGS. 7 and 8. That is, the 0-system interface units 13a, F in FIG.
TS insertion unit (FTSINS) 13b, 1-system interface unit 16a, FTS insertion unit (FTSINS) 16b, 0
System line setting unit 14, first confirmation unit of 0 system (FTSCHK
1) 14a, 1st system 1st verification section (FTSCHK1) 1
4b, selector (SEL) 14c, line setting unit 14d,
0 system interface section 15a, 1 system interface section 1
8a and 1-system line setting unit 17 include 0-system interface unit 113a and FTS insertion unit (FTSIN) shown in FIG.
S) 113b, 1-system interface section 116a, FTS
Insertion unit (FTSINS) 116b, 0-system line setting unit 11
First confirmation unit (FTSCHK1) 114a of 4, 0 system,
1st system 1st confirmation section (FTSCHK1) 114b, selector (SEL) 114c, line setting section 114d, 0 system interface section 115a, 1 system interface section 118
It has the same configuration and operates in the same manner as the line a and line 1 setting unit 117.

However, the second confirmation section (FT) in FIG.
SCHK2) 32, third confirmation unit (FTSCHK3) 3
3 and the third confirmation unit (FTSCHK3) 34 has the same configuration as the second confirmation unit (FTSCHK2) 1 shown in FIG.
14e, the third confirmation unit (FTSCHK3) 115b, and the third confirmation unit (FTSCHK3) 118b have the same configurations as the respective configurations, and additionally, a mask unit is newly provided. Although not shown in the figure, it goes without saying that the second confirmation section of the 1-system line setting section 17 is the same as the second confirmation section 32 of the 0-system line setting section 14. The mask portion will be described later with reference to FIG.

Further, the 0-system clock supply unit 1 in FIG.
9, 1-system clock supply unit 20, reference pulse generation unit 21,
Selector 21a and frame pulse generator 21b
Has the same configuration and operates as the 0-system clock supply unit 119, the 1-system clock supply unit 120, the reference pulse generation unit 121, the selector 121a, and the frame pulse generation unit 121b shown in FIG. 7, respectively. However, the configuration of the clock system switching unit 31 in FIG. 2 is the same as the configuration of the clock system switching unit 122 shown in FIG. 7, and additionally has a mask signal generating unit. The mask signal generation unit generates a mask signal, and outputs the mask signal to the second confirmation unit 32 of the 0-system line setting unit 14 and the second confirmation unit of the 1-system line setting unit 17.
It is supplied to the third confirmation unit 33 and the third confirmation unit 34. The configuration of the mask signal generator will be described below with reference to FIG.

FIG. 3 is a diagram showing the configuration of the mask signal generation unit included in the clock system switching unit 31. That is, the selection (SEL) signal generated by the clock system switching unit 31 is input to the D terminal of the D-FF 31a, and A
It is input to the ND circuit 31d. The selection signal is inverted by the inverter 31b and then input to the D terminal of the D-FF 31c and the AND circuit 31e.
A clock signal (CLK) is input to each clock (C) terminal of the D-FF 31a and the D-FF 31c.
The outputs from the Q terminals of the D-FF 31a and the D-FF 31c are input to the AND circuit 31d and the AND circuit 31e, respectively. The outputs of the AND circuit 31d and the AND circuit 31e are input to the OR circuit 31f, and the output of the OR circuit 31f is input to the monostable multivibrator 31g.

When the selection signal is switched from the 0-system clock supply unit 19 to the 1-system clock supply unit 20, the selection signal shown in FIG.
As shown in (C), it changes from "0" to "1", and when switching to the opposite, it changes from "1" to "0". When the selection signal changes from "0" to "1" and "1" is maintained as it is, both inputs of the AND circuit 31d become "1", which causes the monostable multivibrator 31g to operate for a predetermined time. A mask signal of "1" is generated over the period. This predetermined time is set to twice the cycle of the frame pulse. On the other hand, if the selection signal changes from "1" to "0" and "0" is maintained as it is,
Both inputs of the AND circuit 31e become "1", whereby the monostable multivibrator 31g generates a mask signal which becomes "1" for a predetermined time [FIG. 5].
(D)].

FIG. 4 shows a second confirming unit 32 of the 0-system line setting unit 14, a second confirming unit of the 1-system line setting unit 17, a third confirming unit 33, and a third confirming unit 34, respectively. It is a figure which shows the structure of the mask part contained. Here, the second confirmation unit 32 will be described as an example.

In the second confirmation section 32, the comparison result shown in FIG.
Input to the ND circuit 36. Then, the mask signal sent from the mask signal generator is ANDed through the inverter 35.
Input to the circuit 36. Then, the output of the AND circuit 36 is sent to the monitoring unit as the path monitoring result.

That is, the comparison result shown in FIG. 5E and the inverted signal of the mask signal shown in FIG. 5D are input to the AND circuit 36, and the AND circuit 36 outputs the mask signal while the mask signal is "1". , The comparison result will not be output.
Therefore, until a predetermined time elapses from the time when the selection signal changes from "1" to "0" or vice versa,
Even if "mismatch" occurs in the comparison result, the information is not sent to the monitoring unit. Therefore, it is possible to prevent the monitoring unit from erroneously recognizing the path alarm when the clock supply unit is switched.

In the above embodiment, the predetermined time, which is the "1" duration of the mask signal generated by the monostable multivibrator 31g, is set to be twice the cycle of the frame pulse. It may be set longer.

[0036]

As described above, according to the present invention, when the timing signal generating means is switched from the working to the spare, the mask signal generating means generates the mask signal for a predetermined time from the switching time, Send to confirmation prohibition means. The confirmation prohibiting means prohibits the confirming operation of the confirming means for confirming that no path abnormality has occurred in the transmission path while receiving the mask signal. This makes it possible to mask an erroneous path alarm generated at the time of switching the timing signal generating means, and in such a configuration, one set of the timing signal generating means, the mask signal generating means, and the confirmation inhibiting means is provided in the transmission device. It suffices to provide it, and even if the number of accommodated transmission lines increases, it does not affect the scale of the transmission device. Therefore, the hardware scale can be reduced and the power consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a configuration diagram of a path monitoring device of the present invention.

FIG. 3 is a configuration diagram of a mask signal generator.

FIG. 4 is a configuration diagram of a mask unit.

FIG. 5 is a timing chart of the device of the present invention.

FIG. 6 is a configuration diagram of a transmission system.

FIG. 7 is an internal configuration diagram of a conventional module B.

FIG. 8 is a configuration diagram of a conventional path monitoring device.

FIG. 9 is a diagram illustrating pattern insertion and pattern detection.

FIG. 10 is a timing chart of a conventional device.

FIG. 11 is a block diagram of an alarm protection circuit.

[Explanation of symbols]

 1 First Predetermined Pattern Inserting Means 2 Second Predetermined Pattern Inserting Means 3 Alternate Pattern Inserting Output Means 4 Confirming Means 5 Timing Signal Generating Means 6 Mask Signal Generating Means 7 Confirmation Prohibiting Means

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazunori Hanae, 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor, Hiroshi Oguri, 1015, Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited ( 72) Inventor Katsuhiko Nakamoto 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited

Claims (2)

[Claims] 1. A redundant path monitoring device for monitoring a path of a cross-connect part of a transmission device having a redundant system, wherein a first predetermined pattern insertion for inserting a first predetermined pattern into a signal transmitted through a 0 system path. Means, second predetermined pattern inserting means for inserting a second predetermined pattern into a signal transmitted through the 1-system path, and a signal transmitted through the 0-system path and a signal transmitted through the 1-system path. Then, the first predetermined pattern and the second predetermined pattern respectively inserted in these signals are alternately taken out at a predetermined timing signal, and these taken out alternating patterns are transmitted through the 0-system path. Alternate pattern insertion output means for inserting and outputting a signal or a signal transmitted through the 1-system path, and a signal received from the alternate pattern insertion output means Confirming means for taking out the inserted pattern and confirming that the alternating patterns are correctly received; timing signal generating means having a redundant configuration for generating at least the predetermined timing signal; and the timing signal generating means. Mask signal generating means for generating a mask signal for a predetermined time from the time of switching the redundant configuration of means, and confirmation for receiving the mask signal and for inhibiting the confirming operation of the confirming means while receiving the mask signal. A redundant path monitoring device comprising: a prohibition unit. 2. The predetermined time for the mask signal generating means to generate the mask signal is at least twice the cycle of the predetermined timing signal generated by the timing signal generating means. Redundant path monitoring device.