JPH08204548A - Digital pll circuit and its digital filter - Google Patents

Abstract

PURPOSE: To generate a stable output clock signal by providing a level conversion processing means between the digital filter and a D/A converter so as to suppress the occurrence of plural phase lock points. CONSTITUTION: A signal level conversion processing means 12 discriminates a signal level obtained by a filtering processing means 11 and when the level is at a maximum, the conversion processing into a minimum value or a median and when the level is at a minimum value, the conversion processing to a maximum value or a median are conducted alternately. Furthermore, in the case of pulse wave whose high level is smaller than the maximum value and whose low level is higher than the minimum value, one of the conversion processing of the high level into a maximum value or of the low level into a minimum value is conducted. Thus, a phase comparison signal OPout is converged into a prescribed value and a trailing timing of a reference clock signal VREF is synchronously with a rising timing of a feedback clock signal VLOOP. Thus, only one phase synchronization point is obtained without the production of plural points and a stable output clock without phase shift, that is, a voltage Vout is generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital PLL used in, for example, a communication device in a circuit for generating an internal clock in synchronization with a reference clock supplied from the outside.
The present invention relates to a circuit and a digital filter used in this digital PLL circuit.

[0002]

2. Description of the Related Art Conventionally, a digital PLL circuit of this type is constructed, for example, as follows. FIG. 20 is a circuit block diagram showing the configuration. That is, this digital PLL circuit has a voltage controlled crystal oscillator (VCXO) 7, and the oscillation clock signal Vout of this VCXO 7 is frequency-divided by a frequency divider 8 composed of a counter to obtain a feedback clock signal VLO.
After becoming OP, it is input to the phase comparator 1 together with the reference clock signal VREF supplied from the outside. The phase comparator 1 compares the phase of the feedback clock signal VLOOP with the reference clock signal VREF, and outputs a pulse signal in which the phase difference is represented by duty. This pulse signal is integrated by the analog filter 2, and this integrated output signal passes through the operational amplifier (OPAMP) 3 and the phase comparison signal OPou.
After reaching t, the analog / digital converter (A / D)
4 and is converted into a digital signal by the A / D 4 and then input to the digital filter 5.

The digital filter 5 is composed of, for example, a microcomputer, and executes a filtering calculation process for determining the loop band of the digital PLL circuit by the program process of this microcomputer. The signal output from the digital filter 4 is converted into an analog signal by a digital / analog converter (D / A) 6 and then supplied to the VCXO 7 as a control signal voltage Vcont.

With such a configuration, it is possible to generate the in-device clock Vout which is always synchronized with the reference clock signal VREF supplied from the carrier side. However, the following problems have been pointed out in such a conventional digital PLL circuit. That is, the digital PL
As described above, the L circuit uses the digital filter 5 as a loop filter, and the digital filter 5 performs the filtering calculation processing by the program processing. Therefore, for example, the reference clock signal VRE
If the phase difference between the feedback clock signal VLOOP and the reference clock signal VREF changes significantly, as in the case where F is switched from the working mode to the backup mode, the filtering calculation process of the digital filter 5 cannot follow this phase change, and In some cases, phase lock pull-in cannot be performed in the PLL loop.

In order to confirm this phenomenon, for example, the frequency of the reference clock signal VREF is changed from 2.48110 MHz to 2.048070 MHz, 2.048050 MHz and 2.047920 MHz, and the control signal voltage Vcont and the phase comparison signal OPout at that time are changed. Was investigated. The results are shown in FIGS. 21, 22 and 23, respectively. This is a measurement of the waveforms of the control signal voltage Vcont and the phase comparison signal OPout at the point where the frequency of the reference clock signal VREF has changed, using an oscilloscope having a pre-trigger function.

First, as shown in FIG. 21, the frequency of the reference clock signal VREF is changed from 2.48110 MHz to 2.048.
When the frequency is changed to 070 MHz, since the frequency change is relatively small, the control signal voltage Vcont is changed after this frequency change.
And the phase comparison signal OPout quickly converges to a constant value, and the PLL loop is synchronized. At this time, the phase comparison signal OPout converges to 0V which is the minimum value. on the other hand,
As shown in FIG. 22, when the frequency of the reference clock signal VREF is changed relatively greatly from 2.48110 MHz to 2.048050 MHz, the control signal voltage Vco
The nt and the phase comparison signal OPout are pulsed and do not converge to a constant value, so that synchronization is not drawn.

Further, as shown in FIG. 23, the frequency of the reference clock signal VREF is changed from 2.48110 MHz to 2.0.
When the frequency is further changed to 47920 MHz, synchronization pull-in is performed in the PLL loop, but the phase synchronization point is different from that in the case of FIG. That is, the frequency of the reference clock signal VREF is set to 2.48110.
When changing from 2.0 MHz to 2.048070 MHz, for example, as shown in FIG.
Of the reference clock signal VREF is 2.48110.
When the frequency is changed from 2.0 MHz to 2.047920 MHz, for example, as shown in FIG.
Are synchronized with the rising timing of the feedback clock signal VLOOP.

That is, in the case of FIG. 25, the digital PLL circuit has a plurality of phase synchronization points. It is presumed that the reason is that the digital PLL circuit has two filters, the analog filter 2 and the digital filter 5, as a loop filter. When there are a plurality of phase synchronization points as described above, the output clock signal Vou
Since the phase of t is shifted on the way, there is a possibility that a malfunction occurs in the gate array in the communication device which operates by receiving this output clock signal Vout, which is extremely undesirable.

[0009]

As described above, in the conventional digital PLL circuit, the reference clock signal VREF is used.
When the frequency greatly changes as in the case where the current is switched from the active to the standby, the control signal voltage Vcont changes abruptly, and the change cannot be followed by the filtering calculation process of the digital filter 5, resulting in phase synchronization. There was a problem that it could not be removed. Also, the reference clock signal V
Depending on the amount of change in the frequency of REF, multiple synchronization points are generated even if phase synchronization is achieved, and as a result, the output clock signal Vout
There is a risk that the phase becomes unstable and a malfunction occurs in the circuit that operates by receiving this output clock signal.

The present invention has been made in view of the above circumstances, and an object of the present invention is to ensure that the phase synchronization pull-in is always performed even when the frequency of the reference clock signal largely changes, and more It is an object of the present invention to provide a digital PLL circuit and its digital filter capable of generating a stable output clock signal without generating a phase synchronization point.

[0011]

In order to achieve the above object, the digital PLL circuit of the present invention is provided with a level conversion processing means at the subsequent stage of the digital filter. Then, in this level conversion processing means, when the level of the control signal generated by the digital filter reaches a predetermined maximum value, processing for converting the level of the control signal to a predetermined minimum value and conversion to a median value And a process for selectively converting the level of the control signal generated by the digital filter to the predetermined maximum value and the median value when the level of the control signal generated by the digital filter reaches the predetermined minimum value. When the level of the control signal generated by the digital filter has a pulse waveform smaller than the predetermined maximum value and larger than the predetermined minimum value, A process of converting the level of the control signal into at least one of the predetermined maximum value and the minimum value is performed, and the signal after this arithmetic processing is performed. It is obtained so as to output to the digital-to-analog converting circuit as a control signal.

The digital filter of the present invention further comprises a second arithmetic processing means in addition to the first arithmetic processing means for performing filtering arithmetic processing for setting the loop band for the output signal of the analog-digital converter. I have it. Then, in the second arithmetic processing means, when the level of the signal obtained by the first arithmetic processing means reaches a predetermined maximum value, processing for converting the level of the signal into a predetermined minimum value and a median value And selectively converting the signal level obtained by the first processing means into the predetermined maximum value and the median value. Further, when the level of the signal obtained by the first processing means has a pulse waveform smaller than the predetermined maximum value and larger than the predetermined minimum value, the level of the signal is changed to the predetermined maximum value. And at least one of the minimum value is performed, and the signal after this arithmetic processing is output as a control signal.

[0013]

As a result, according to the digital PLL circuit and the digital filter of the present invention, the filtering operation processing of the digital filter cannot follow the frequency change of the reference clock signal, and the signal level after the filtering operation processing reaches the maximum value. When it reaches or becomes the minimum value, the signal level after the filtering operation processing is converted to the minimum value or the median value or the maximum value or the median value by the level conversion processing means or the second operation processing means. Even if the signal level after filtering does not reach the maximum or minimum value, if the signal waveform is a repeating pulse waveform, the signal level after filtering is changed to the maximum or minimum value. It That is, the signal level that has not fully increased to the maximum value or the signal level that has not fully decreased to the minimum value due to the delay in the arithmetic processing of the digital filter is forcibly pulled in by the level conversion processing means or the second arithmetic processing means. It will be set to a possible level.

For this reason, even if the signal after digital filtering cannot follow the frequency change of the reference clock signal due to the delay in the arithmetic processing of the digital filter, the control signal voltage similar to the case where it follows as a result is generated. Can be supplied to the VCXO. Therefore, as a result, a sufficiently large capture range can be obtained, which makes it possible to provide a digital PLL circuit that can reliably follow a large frequency change.

Further, by performing the level conversion processing as described above, the phase comparison signal has a constant value (for example, 0).
V) will converge. Therefore, the falling edge of the reference clock signal and the rising edge of the feedback clock signal are synchronized with each other at the same timing, and as a result, the number of phase synchronization points is not plural but only one. Therefore, it is possible to generate a stable output clock signal with no phase shift and the like, thereby preventing malfunction in a circuit such as a gate array which operates by receiving this output clock signal.

[0016]

First, the principle of the present invention will be described. The waveform of the control signal voltage Vcont when the synchronous pull-in described in FIG. 22 is not performed is examined in detail. As a result, it was found that there are four types of waveforms of the control signal voltage Vcont depending on the value of the frequency change of the reference clock signal VREF. These waveforms are shown in FIGS. 5, 7, 9 and 11.

First, in FIG. 5, the low level has a minimum value of 0V.
7 shows a waveform of the control signal voltage Vcont that is (GND) and has a maximum high level of 5V.
In this state, for example, assume that the power of the digital PLL circuit is once turned off and then turned on again. Then, the control signal voltage V
The waveform of cont converges to a constant voltage as shown in FIG. 6, and the digital PLL circuit is in a synchronized state.

Next, FIG. 7 shows that the low level is 0, which is the minimum value.
7 shows a waveform of the control signal voltage Vcont which is higher than V and has a maximum high level of 5V. Also in this case, the digital PLL is used as in the case of FIG.
When the power of the circuit is once turned off and then turned on again, the waveform of the control signal voltage Vcont converges to a constant voltage as shown in FIG. 8 as in the case of FIG. 6, and the digital PLL circuit is brought into a synchronized state.

Further, FIG. 9 shows a waveform of the control signal voltage Vcont in which the low level is 0V which is the minimum value, and the high level is smaller than 5V which is the maximum value. Also in this case, as in the case of FIG. 5, when the power of the digital PLL circuit is once turned off and then turned on again, the waveform of the control signal voltage Vcont converges to a constant voltage as shown in FIG.
The L circuit is in a synchronized state.

Further, in FIG. 11, the low level is higher than the minimum value of 0 V and the high level is the maximum value of 5 V.
3 shows a waveform of the control signal voltage Vcont smaller than the above. In this case, even if the power of the digital PLL circuit is once turned off and then turned on again, the control signal voltage Vcont does not converge as shown in FIG. In other words, it can be seen that power-on reset is not effective. Next, the reference clock signal VRE
I tried changing the frequency of F within a certain range. The waveform at this time is shown in FIG. As is clear from the figure, the control signal voltage Vcont converges to a constant value and the digital PLL circuit is synchronized. That is, the waveform of the control signal voltage Vcont is shown in FIG.
In such a case, the level of the control signal voltage Vcont should be changed. Specifically, the signal level after the filtering calculation processing in the digital filter may be converted into the maximum value or the minimum value.

From the above, the reference clock signal VREF
As a solution to the case where the frequency is greatly changed and the synchronization pull-in is not performed, the following processing may be added to the signal after the filtering calculation processing.

(1) When the signal level after the filtering calculation process reaches the maximum value, the process of converting the level of the signal to the minimum value and the process of converting it to the central value are selectively performed.

(2) When the signal level after the filtering calculation process reaches the minimum value, the process of converting the level of the signal to the maximum value and the process of converting it to the central value are selectively performed.

(3) When the high level of the signal after the filtering calculation process is smaller than the maximum value and the low level becomes a pulse wave larger than the minimum value, the level of the signal is changed to the maximum value and the minimum value. Convert to at least one.

Next, an embodiment of the present invention constructed based on the above principle will be described. FIG. 1 is a circuit block diagram showing the configuration of the digital PLL circuit according to the embodiment. In the figure, the same parts as those in FIG. 20 are designated by the same reference numerals and detailed description thereof will be omitted.

The digital filter 10 is composed of, for example, a microcomputer, and its functions are a filtering processing means 11 and a signal level conversion processing means 12.
It has and. The filtering processing means 11 is A /
The filtering operation processing for setting the loop band of the digital PLL circuit is performed on the signal supplied from D4.

The signal level conversion processing means 12 judges the level of the signal obtained by the filtering processing means 11, and if the signal level is the maximum value, the processing for converting the level of the signal to the minimum value and the central value. Alternately with the process of converting to. On the other hand, the filtering processing means 1
If the level of the signal obtained in 1 is the minimum value, the process of converting the level of the signal to the maximum value and the process of converting it to the central value are alternately performed. Further, it is determined whether or not the signal obtained by the filtering processing means 11 is a pulse wave whose high level is smaller than the maximum value and whose low level is larger than the minimum value. Then, in the case of such a pulse wave, at least one of the process of converting the high level of the signal to the maximum value and the process of converting the low level of the signal to the minimum value is performed.

Next, the operation of the digital PLL circuit configured as described above will be described according to the processing procedure of the digital filter 10. 2 and 3 are flowcharts showing the processing procedure of the digital filter 10.

The digital filter 10 first performs filtering calculation processing on the signal supplied from the A / D 4 at each sampling timing by the main program of the filtering processing means 11.

Next, the digital filter 10 executes the processing described in (1) and (2) above according to the flowchart shown in FIG. 2 at each sampling timing of the signal after the above filtering processing. For example,
First, in step 2a, it is determined whether or not the level (main program output value) A of the signal after the filtering process is 5V which is the maximum value. As a result of this judgment, A
= The maximum value, it is determined in step 2b whether or not the value of A has been converted to the minimum value at the previous sampling timing, and if not, step 2d
Then, the value of A is converted into the minimum value, and the process returns to the main program. On the other hand, if the value of A is converted to the minimum value at the previous sampling timing, the process proceeds to step 2c, where the value (maximum value) of A is the central value. Convert to 5V,
Return to main program.

When it is determined in step 2a that the value of A is not the maximum value, the digital filter 1
If 0, the process proceeds to step 2e, and it is determined whether the value of A is 0V which is the minimum value. If the result of this determination is that A = minimum value, then the procedure moves to step 2f, where it is determined whether or not the value of A has been converted to the maximum value at the previous sampling timing, and if it has not been converted. In step 2h, the value of A is converted into the maximum value, and the process returns to the main program. On the other hand, at the previous sampling timing, the above A
If the value of is converted to the maximum value, the process proceeds to step 2g, where the value of A (minimum value) is converted to the central value of 2.5 V, and the process returns to the main program.

Thus, the level conversion process corresponding to the power-on reset is performed when the high level of the signal level A after the filtering process is the maximum value and when the low level is the minimum value. And
This level-converted signal is used as a control signal by the D / A 6
Converted into an analog control voltage VC by the VCXO
7 is supplied. Therefore, finally the phase comparison signal OP
out and the control signal voltage Vcont converge to a constant value, which causes the digital PLL circuit to have a reference clock signal VREF.
It will be in a synchronized state with.

On the other hand, step 2a and step 2 described above.
It is assumed that it is determined in e that A is neither the maximum value nor the minimum value. Then, the digital filter 10
Shifts to the flowchart shown in FIG. Then, the processing described in (3) above is executed according to this flowchart.

For example, first in step 3a, as shown in FIG.
As shown in, the signal level A (t-1) after filtering processing obtained at the previous sampling timing
Then, it is determined whether or not the difference between the filtered signal level A (t) obtained at the current sampling timing is larger than a predetermined value X. As a result of this judgment, A (t-1)
If −A (t) ≧ X, the process proceeds to step 3b, where the discrimination constant N is incremented, and then step 3
In c, it is determined whether N is larger than the predetermined value Y. If the result of this determination is N ≧ Y, it is determined that the pulse wave in which the high level of the control signal voltage Vcont is smaller than the maximum value and the low level thereof is larger than the minimum value is continuous, and in step 3d. After converting the signal level after the above filtering process to 5 V which is the maximum value, the process returns to the main program. On the other hand, if N <Y is determined in step 3c, the process directly returns to the main program.

On the other hand, in step 3a, A (t-1)
If −A (t) <X, then the digital filter 10
Shifts to step 3e to increment the discrimination constant M here, and then shifts to step 3f to determine whether M is larger than a predetermined value Z or not. If the result of this determination is M ≧ Z, it is determined that the control signal voltage Vcont has converged to a constant voltage and the digital PLL circuit is in synchronization, and the above-mentioned determination constant N is cleared in step 3g, and then the main Return to the program. If it is determined in step 3f that M <Z, it cannot be determined that the digital PLL circuit is synchronized, and the process directly returns to the main program.

Thus, when the high level and the low level of the signal after the filtering process are the pulse waves which are not the maximum value and the minimum value respectively, the signal level after the filtering process is converted to the maximum value. The level-converted signal is converted into an analog control signal voltage Vcont by the D / A 6 and supplied to the VCXO 7. Therefore, the phase comparison signal OPout and the control signal voltage Vcont finally converge to a constant value, whereby the digital PLL circuit is brought into a state of being synchronized with the reference clock signal VREF.

In the digital PLL circuit that has undergone the signal level conversion processing as described above, the reference clock signal V
The circuit operation when the REF frequency was changed was examined by measurement. The results are shown in FIGS. 14, 15 and 16. These results are shown in FIG. 21, FIG. 22 and FIG.
As in the case of, the frequency of the reference clock signal VREF is changed from 2.48110 MHz to 2.048070 MHz,
2.048050MHz and 2.047920MHz
, And the waveforms of the control signal voltage Vcont and the phase comparison signal OPout at that time are measured. As shown in FIGS. 14, 15 and 16, the control signal voltage Vcont converges to a constant voltage with respect to all the frequency changes of the reference clock signal VREF, and the digital PL
It can be seen that the L circuit is synchronous.

The reference clock signal VREF when the operation shown in FIGS. 14, 15 and 16 is performed.
And the waveform of the feedback clock signal VLOOP are shown in FIG. 1 respectively.
7, FIG. 18 and FIG. As is clear from these figures, not only when the frequency change of the reference clock signal VREF is relatively small (FIG. 17) or when the frequency change is relatively large (FIG. 18), the frequency change of the reference clock signal VREF is further large. In the case (FIG. 19), the reference clock signal VREF and the feedback clock signal VLOOP rise in timing and are synchronized with each other. That is, a plurality of phase synchronization points do not occur for any frequency change, and the phase synchronization is always established at one phase synchronization point.

As described above, in the digital PLL circuit of this embodiment, the digital filter 10 is provided with the signal level conversion processing means 12, and the signal level conversion processing means 12 causes the signal level obtained by the filtering processing means 11 to be the maximum value. In that case, the process of converting the level of the signal to the minimum value and the process of converting it to the central value are alternately performed.
On the other hand, if the level of the signal obtained by the filtering processing means 11 is the minimum value, the process of converting the level of the signal to the maximum value and the process of converting it to the central value are alternately performed. Further, it is determined whether or not the signal obtained by the filtering processing means 11 is a pulse wave whose high level is smaller than the maximum value and whose low level is larger than the minimum value. In the case of such a pulse wave, at least one of the process of converting the high level of the signal to the maximum value and the process of converting the low level of the signal to the minimum value is performed.

Therefore, in the present embodiment, the filtering operation processing of the digital filter 10 cannot follow the frequency change of the reference clock signal VREF, and the signal level after the filtering operation processing becomes the maximum value or the minimum value. Then, the signal level after the filtering calculation process is converted to the minimum value or the center value or to the maximum value or the center value, respectively. When the signal level after the filtering process becomes a pulse wave that does not reach the maximum value or the minimum value, the signal level after the filtering process is changed to the maximum value or the minimum value.

That is, the signal level that has not fully increased to the maximum value or the signal level that has not fully decreased to the minimum value due to the delay in the arithmetic processing of the digital filter 10 is forcibly set to a level at which synchronous pull-in is possible. become. For this reason, even if the control signal after the filtering process cannot follow the frequency change of the reference clock signal VREF due to the delay of the arithmetic processing of the digital filter 10, the control signal voltage Vcont similar to the case where it follows as a result is generated. Can be supplied to the VCXO7. Therefore, as a result, a sufficiently large capture range can be obtained, which makes it possible to provide a digital PLL circuit that can reliably follow a large frequency change.

Further, by performing the signal level conversion processing as described above, the phase comparison signal OPout converges at a constant value (for example, 0V). Therefore, the digital PLL circuit is synchronized with the falling timing of the reference clock signal VREF and the rising timing of the feedback clock signal VLOOP being in agreement with each other.
As a result, the number of phase synchronization points is not one but only one.
Therefore, it is possible to generate a stable output clock signal Vout with no phase shift and the like, thereby preventing malfunction in a circuit such as a gate array which operates by receiving this output clock signal Vout.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the case where the microcomputer of the digital filter 10 performs the signal level conversion processing has been described as an example, but a circuit having a signal level conversion function is provided between the digital filter 5 and the D / A 6, and The circuit may be configured to perform signal level conversion processing.

In addition, processing contents and processing procedure of signal level conversion processing, configuration of signal level conversion means, digital PL
The configuration of the L circuit and the like can be modified in various ways without departing from the scope of the present invention.

[0045]

As described in detail above, in the digital PLL circuit of the present invention, level conversion processing means is provided in the subsequent stage of the digital filter, and in this level conversion processing means,
When the level of the control signal generated by the digital filter reaches a predetermined maximum value, the process of converting the level of the control signal to a predetermined minimum value and the process of converting it to a median value are selectively performed, and When the level of the control signal generated by the digital filter reaches the predetermined minimum value, the process of converting the level of the control signal to the predetermined maximum value and the process of converting it to the median value are selectively performed. Further, when the level of the control signal generated by the digital filter has a pulse waveform smaller than the predetermined maximum value and larger than the predetermined minimum value, the level of the control signal is changed to the predetermined maximum value. Value and minimum value are converted, and the signal after this calculation is used as a control signal for digital / analog conversion. It is to be output to the circuit.

Further, in the digital filter of the present invention, the first filtering processing for setting the loop band is performed on the output signal of the analog-digital converter.
In addition to the above arithmetic processing means, a second arithmetic processing means is provided,
In the second arithmetic processing means, when the level of the signal obtained by the first arithmetic processing means reaches a predetermined maximum value, processing for converting the level of the signal to a predetermined minimum value and conversion to a median value And the process of selectively converting the level of the signal obtained by the first processing means into the predetermined maximum value and the median value. When the level of the signal obtained by the first processing means has a pulse waveform smaller than the predetermined maximum value and larger than the predetermined minimum value, the level of the signal is changed to the predetermined maximum value and the minimum value. Convert to at least one of the values,
The signal after this arithmetic processing is output as a control signal.

Therefore, according to the present invention, even if the frequency of the reference clock signal greatly changes, it is possible to ensure that the phase synchronization pull-in is always performed, and furthermore, it is possible to prevent a plurality of phase synchronization points from occurring. Digital PL capable of generating stable output clock signal
An L circuit and its digital filter can be provided.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a configuration of a digital PLL circuit according to an embodiment of the present invention.

FIG. 2 is a flowchart showing a part of signal level conversion processing in a digital filter of the digital PLL circuit shown in FIG.

3 is a flowchart showing another part of the signal level conversion processing in the digital filter of the digital PLL circuit shown in FIG.

FIG. 4 is a diagram showing an example of a signal waveform after filtering processing obtained in the digital filter of the digital PLL circuit shown in FIG.

FIG. 5 is a diagram showing an example of waveforms of a control signal voltage Vcont and a phase comparison signal OPout when synchronous pull-in cannot be performed.

6 is a diagram showing a control signal voltage Vcont and a phase comparison signal O after power-on reset for the waveforms shown in FIG.
The figure which showed the waveform of Pout.

FIG. 7 is a diagram showing another example of the waveforms of the control signal voltage Vcont and the phase comparison signal OPout when the synchronous pull-in cannot be performed.

8 is a control signal voltage Vcont and a phase comparison signal O after a power-on reset is performed on the waveform shown in FIG.
The figure which showed the waveform of Pout.

FIG. 9 is a diagram showing another example of the waveforms of the control signal voltage Vcont and the phase comparison signal OPout when the synchronous pull-in cannot be performed.

10 is a diagram showing waveforms of a control signal voltage Vcont and a phase comparison signal OPout after power-on reset is performed on the waveforms shown in FIG.

FIG. 11 is a diagram showing another example of the waveforms of the control signal voltage Vcont and the phase comparison signal OPout when the synchronization pull-in cannot be performed.

12 is a diagram showing waveforms of a control signal voltage Vcont and a phase comparison signal OPout after power-on reset is performed on the waveforms shown in FIG.

13 is a diagram showing the waveforms of the control signal voltage Vcont and the phase comparison signal OPout after the frequency of the reference clock signal VREF is changed with respect to the waveform shown in FIG.

14 is a control signal voltage Vcont and a phase comparison signal OPout representing the effect of the digital PLL circuit shown in FIG.
The figure which shows an example of the waveform of.

15 is a control signal voltage Vcont and a phase comparison signal OPout representing the effect of the digital PLL circuit shown in FIG.
The figure which shows the other example of the waveform of.

16 is a control signal voltage Vcont and a phase comparison signal OPout representing the effect of the digital PLL circuit shown in FIG.
The figure which shows the other example of the waveform of FIG.

17 is a diagram showing an example of waveforms of a reference clock signal VREF and a feedback clock signal VLOOP showing effects of the digital PLL circuit shown in FIG.

FIG. 18 is a diagram showing another example of the waveforms of the reference clock signal VREF and the feedback clock signal VLOOP showing the effect of the digital PLL circuit shown in FIG. 1.

19 is a diagram showing another example of the waveforms of the reference clock signal VREF and the feedback clock signal VLOOP showing the effect of the digital PLL circuit shown in FIG.

FIG. 20 is a circuit block diagram showing an example of the configuration of a conventional digital PLL circuit.

21 is a diagram showing an example of the waveforms of the control signal voltage Vcont and the phase comparison signal OPout for explaining the problems of the conventional digital PLL circuit shown in FIG.

22 is a diagram showing another example of the waveforms of the control signal voltage Vcont and the phase comparison signal OPout for explaining the problems of the conventional digital PLL circuit shown in FIG.

23 is a diagram showing another example of the waveforms of the control signal voltage Vcont and the phase comparison signal OPout for explaining the problem of the conventional digital PLL circuit shown in FIG.

24 is a diagram showing an example of waveforms of a reference clock signal VREF and a feedback clock signal VLOOP for explaining the problems of the conventional digital PLL circuit shown in FIG.

FIG. 25 is a diagram showing another example of the waveforms of the reference clock signal VREF and the feedback clock signal VLOOP for explaining the problem of the conventional digital PLL circuit shown in FIG. 20.

[Explanation of symbols]

 1 ... Phase comparator 2 ... Analog filter 3 ... Operational amplifier (OPAMP) 4 ... Analog-digital converter (A / D) 5, 10 ... Digital filter 6 ... Digital-analog converter (D / A) 7 ... Voltage control Crystal oscillator (VCXO) 8 ... Counter 11 ... Filtering processing means 12 ... Signal level conversion processing means VREF ... Reference clock signal VLOOP ... Feedback clock signal OPout ... Phase comparison signal Vcont ... Control signal voltage Vout ... Output clock signal

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H03L 7/10 H03L 7/10 D

Claims (2)

[Claims] 1. A voltage-controlled oscillator, a phase comparator for phase-comparing a first clock signal obtained by dividing the oscillation output of the voltage-controlled oscillator with a second clock signal serving as a reference, and a phase comparator for the phase comparator. An analog filter that integrates the output signal, an analog-digital converter that converts the output signal of this analog filter into a digital signal, and a filtering calculation process to set the loop band for the output signal of this analog-digital converter. A digital PLL circuit comprising: a digital filter for generating a control signal, and a digital-analog converter for converting a control signal output from the digital filter into an analog voltage and supplying the analog voltage to the voltage controlled oscillator. The level of the control signal generated by the filter reaches the specified maximum value. In this case, the process of converting the level of the control signal to a predetermined minimum value and the process of converting it to a median value are selectively performed, and the level of the control signal generated by the digital filter becomes the predetermined minimum value. If the level of the control signal is changed to the predetermined maximum value and the median value, the level of the control signal generated by the digital filter is changed to the predetermined value. A level for performing a process of converting the level of the control signal into at least one of the predetermined maximum value and the minimum value when the pulse waveform is smaller than the maximum value and larger than the predetermined minimum value. A digital PLL circuit comprising conversion processing means between the digital filter and the digital-analog converter. 2. A voltage-controlled oscillator, a phase comparator for phase-comparing a first clock signal obtained by dividing the oscillation output of the voltage-controlled oscillator with a second clock signal serving as a reference, and a phase comparator for the phase comparator. An analog filter that integrates the output signal, an analog-digital converter that converts the output signal of this analog filter into a digital signal, a digital filter that generates a control signal based on the output signal of this analog-digital converter, and this The digital filter used in a digital PLL circuit including a digital-analog converter that converts a control signal output from a digital filter into an analog voltage and supplies the analog voltage to the voltage-controlled oscillator, wherein: Performs filtering calculation processing to set the loop band for the output signal A first arithmetic processing means, processing for converting the level of the signal obtained by the first arithmetic processing means to a predetermined minimum value when the level of the signal reaches a predetermined maximum value, and a median value. And the process of converting the level of the signal obtained by the first processing means to the predetermined maximum value and the process of converting it to the median value. Further, when the level of the signal obtained by the first processing means has a pulse waveform smaller than the predetermined maximum value and larger than the predetermined minimum value, the level of the signal is changed to the predetermined maximum value. And a second arithmetic processing means for performing a process of converting into at least one of the minimum value and outputting the signal obtained by these processes as the control signal. Rufiruta.