JPH08204510A - Frequency control method and device for controlling frequency - Google Patents

Frequency control method and device for controlling frequency

Info

Publication number
JPH08204510A
JPH08204510A JP787395A JP787395A JPH08204510A JP H08204510 A JPH08204510 A JP H08204510A JP 787395 A JP787395 A JP 787395A JP 787395 A JP787395 A JP 787395A JP H08204510 A JPH08204510 A JP H08204510A
Authority
JP
Japan
Prior art keywords
frequency
reference frequency
data
circuit
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP787395A
Other languages
Japanese (ja)
Inventor
Kunihiko Sakaihara
井 原 邦 彦 酒
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP787395A priority Critical patent/JPH08204510A/en
Publication of JPH08204510A publication Critical patent/JPH08204510A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To provide a reference frequency with higher precision with a simple and inexpensive device configuration. CONSTITUTION: A reception circuit 11 receives an input signal received from a base station or a relay station and a CPU 13 analyzes part of a signal resulting from the received signal demodulated by a demodulation circuit 12 to calculate a frequency deviation. The frequency deviation is corrected to update reference frequency data stored in a memory 14 and the updated reference frequency data are D/A-converted by a D/A converter 15. A variable reference frequency oscillating circuit 16 generates a reference frequency based on the data and a PLL synthesizer loop 17 generates a local signal and it is mixed with a reception frequency at the reception circuit 11 and the mixed signal is demodulated by a demodulation circuit 12.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、基地局、中継局等を利
用する無線システム全般の移動端末の周波数制御方法お
よびその装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency control method and apparatus for a mobile terminal in a general wireless system using a base station, a relay station and the like.

【0002】[0002]

【従来の技術】図2は従来の移動端末におけるデジタル
制御方式による周波数制御装置の構成を示すものであ
る。図2において、21は受信回路、22は復調回路、
23はCPU、24は読み出し専用のメモリ(RO
M)、25はD/Aコンバータ、26は可変型基準周波
数発振回路、27はPLLシンセサイザループである。
CPU23は、メモリ24から基準周波数データ読み込
んで制御データをD/Aコンバータ25に渡す。D/A
コンバータ25は、渡された制御データを基に基準周波
数データをアナログ信号に変換して可変型基準周波数発
振回路26に渡す。可変型基準周波数発振回路26は、
基準周波数を発振してPLLシンセサイザループ27に
渡す。PLLシンセサイザループ27は、この基準周波
数を基に局部周波数を発振して受信回路21にローカル
信号を渡す。受信回路21では、このローカル信号の局
部周波数と基地局または中継局からの受信入力信号の周
波数とを合成して中間周波数を発生させ、復調回路22
で受信入力信号を復調し、その一部をCPU23に渡
す。
2. Description of the Related Art FIG. 2 shows the configuration of a conventional frequency control device using a digital control method in a mobile terminal. In FIG. 2, 21 is a receiving circuit, 22 is a demodulation circuit,
23 is a CPU, 24 is a read-only memory (RO
M), 25 is a D / A converter, 26 is a variable reference frequency oscillation circuit, and 27 is a PLL synthesizer loop.
The CPU 23 reads the reference frequency data from the memory 24 and passes the control data to the D / A converter 25. D / A
The converter 25 converts the reference frequency data into an analog signal based on the passed control data and passes it to the variable reference frequency oscillation circuit 26. The variable reference frequency oscillation circuit 26 is
The reference frequency is oscillated and passed to the PLL synthesizer loop 27. The PLL synthesizer loop 27 oscillates a local frequency based on this reference frequency and passes a local signal to the receiving circuit 21. In the receiving circuit 21, the local frequency of this local signal and the frequency of the input signal received from the base station or relay station are combined to generate an intermediate frequency, and the demodulation circuit 22
The received input signal is demodulated by and a part of it is delivered to the CPU 23.

【0003】図3は従来の移動端末におけるアナログ制
御方式による周波数制御装置の構成を示すものである。
この例では、可変型基準周波数発振回路34が基準周波
数を発振し、PLLシンセサイザループ35がこの基準
周波数を基に局部周波数を発振して受信回路31にロー
カル信号を渡し、受信回路31ではこのローカル信号の
局部周波数と受信入力信号の周波数とを合成して中間周
波数を発生させ、復調回路32で受信入力信号を復調
し、その一部をCPU33に渡す。
FIG. 3 shows the configuration of a conventional frequency control device using an analog control method in a mobile terminal.
In this example, the variable reference frequency oscillating circuit 34 oscillates a reference frequency, and the PLL synthesizer loop 35 oscillates a local frequency based on this reference frequency to pass a local signal to the receiving circuit 31. The local frequency of the signal and the frequency of the received input signal are combined to generate an intermediate frequency, the demodulation circuit 32 demodulates the received input signal, and a part thereof is passed to the CPU 33.

【0004】このように、上記従来の移動端末における
周波数制御装置では、基準周波数の精度が自己の内部回
路のみで決まっていた。
As described above, in the conventional frequency control device for the mobile terminal, the accuracy of the reference frequency is determined only by its own internal circuit.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、上記従
来の周波数制御装置では、基準周波数の精度を自己の内
部回路のみに頼るので、何等かの要因により基準周波数
がずれてしまった場合、運用中の修正が難しく、また経
時変化や電源電圧の変動による基準周波数のずれに対し
て補正をかけることも困難であるという問題があった。
However, in the above-mentioned conventional frequency control device, since the accuracy of the reference frequency depends only on its own internal circuit, if the reference frequency is deviated due to some reason, it is still in operation. There is a problem in that it is difficult to correct, and it is also difficult to correct the deviation of the reference frequency due to changes over time or fluctuations in the power supply voltage.

【0006】本発明は、このような従来の問題を解決す
るものであり、より高精度の基準周波数を簡易かつ低価
格の装置構成で得ることのできる周波数制御方法および
その装置を提供することを目的とする。
The present invention solves such a conventional problem, and provides a frequency control method and a device therefor capable of obtaining a highly accurate reference frequency with a simple and low-priced device configuration. To aim.

【0007】[0007]

【課題を解決するための手段】本発明は、上記目的を達
成するために、より高精度の基準周波数発振回路を有す
る基地局または中継局からの受信周波数により常時自己
の基準周波数の補正を行ない、その補正値を新規の基準
値データとして更新し続けるようにしたものである。
In order to achieve the above object, the present invention constantly corrects its own reference frequency by the reception frequency from a base station or a relay station having a more accurate reference frequency oscillation circuit. The correction value is continuously updated as new reference value data.

【0008】[0008]

【作用】したがって、本発明によれば、受信周波数に対
し自己補正をかけたデータにより常時基準周波数の基本
データを更新することにより、基準周波数発振回路の特
性上温度補償のみを高精度にするだけで、経時変化や電
源電圧の変動に伴う周波数のずれは、かなり広範囲にわ
たって許容することができ、回路構成の簡略化や構成部
品の低価格化が可能になる等の効果を有する。
Therefore, according to the present invention, the basic data of the reference frequency is constantly updated with the data obtained by self-correcting the reception frequency, so that only the temperature compensation is highly accurate due to the characteristics of the reference frequency oscillation circuit. Therefore, the frequency shift due to the change over time or the fluctuation of the power supply voltage can be allowed in a considerably wide range, and the circuit configuration can be simplified and the cost of the component parts can be reduced.

【0009】[0009]

【実施例】図1は本発明の一実施例の構成を示すもので
ある。図1において、11は受信回路、12は復調回
路、13はCPU、14は随時書き込み読み出し可能な
メモリ(RAM)、15はD/Aコンバータ、16は可
変型基準周波数発振回路、17はPLLシンセサイザル
ープである。CPU13は、メモリ14から基準周波数
データ読み込んで制御データをD/Aコンバータ15に
渡す。D/Aコンバータ15は、渡された制御データを
基に基準周波数データをアナログ信号に変換して可変型
基準周波数発振回路16に渡す。可変型基準周波数発振
回路16は、基準周波数を発振してPLLシンセサイザ
ループ17に渡す。PLLシンセサイザループ17は、
この基準周波数を基に局部周波数を発振して受信回路1
1にローカル信号を渡す。受信回路11では、このロー
カル信号の局部周波数と基地局または中継局からの受信
入力信号の周波数とを合成して中間周波数を発生させ、
復調回路12で受信入力信号を復調し、その一部をCP
U13に渡す。CPU13は、入力された信号を解析し
て周波数ずれを算出し、その周波数差を修正してメモリ
14内の基準周波数データを更新し、更新された基準周
波数データを基にD/Aコンバータ15に制御データを
送り、上記の動作を繰り返す。
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the configuration of an embodiment of the present invention. In FIG. 1, 11 is a receiving circuit, 12 is a demodulation circuit, 13 is a CPU, 14 is a memory (RAM) that can be written and read at any time, 15 is a D / A converter, 16 is a variable reference frequency oscillation circuit, and 17 is a PLL synthesizer. It is a loop. The CPU 13 reads the reference frequency data from the memory 14 and passes the control data to the D / A converter 15. The D / A converter 15 converts the reference frequency data into an analog signal based on the passed control data, and passes the analog signal to the variable reference frequency oscillation circuit 16. The variable reference frequency oscillation circuit 16 oscillates the reference frequency and passes it to the PLL synthesizer loop 17. The PLL synthesizer loop 17 is
The receiver circuit 1 oscillates a local frequency based on this reference frequency.
Pass the local signal to 1. In the receiving circuit 11, the local frequency of this local signal and the frequency of the input signal received from the base station or relay station are combined to generate an intermediate frequency,
The demodulation circuit 12 demodulates the received input signal, part of which is CP
Hand it over to U13. The CPU 13 analyzes the input signal, calculates the frequency shift, corrects the frequency difference, updates the reference frequency data in the memory 14, and outputs to the D / A converter 15 based on the updated reference frequency data. Send control data and repeat the above operation.

【0010】このように、上記実施例によれば、より高
精度の基準周波数発振回路を有する基地局または中継局
からの受信周波数により常時自己の基準周波数の補正を
行ない、その補正値を新規の基準値データとして更新し
続けるようにしたので、可変型基準周波数発振回路の単
体仕様においては、温度特性のみを高精度に抑え込め
ば、その他の周波数安定性は、機器が運用されている限
り常時基地局または中継局と同等にすることができる。
As described above, according to the above embodiment, the self reference frequency is constantly corrected by the reception frequency from the base station or the relay station having the higher precision reference frequency oscillation circuit, and the correction value is newly set. Since it is kept updated as reference value data, in the stand-alone specification of the variable reference frequency oscillator circuit, if only the temperature characteristics are suppressed with high accuracy, other frequency stability will always be maintained as long as the equipment is in operation. It can be equivalent to a station or relay station.

【0011】[0011]

【発明の効果】本発明は、上記実施例から明らかなよう
に、受信周波数により常時自己の基準周波数の補正を行
ない、その補正値を新規の基準値データとして更新し続
けるようにしたので、無線システムにおける移動端末の
周波数精度を基地局または中継局なみにすることがで
き、基準周波数発振器の構成を簡略化および低価格化す
ることができる。
As is apparent from the above embodiment, the present invention constantly corrects its own reference frequency according to the received frequency and continuously updates the correction value as new reference value data. The frequency accuracy of the mobile terminal in the system can be made similar to that of the base station or the relay station, and the configuration of the reference frequency oscillator can be simplified and the cost can be reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例における周波数制御装置の構
成を示すブロック図
FIG. 1 is a block diagram showing a configuration of a frequency control device according to an embodiment of the present invention.

【図2】従来のデジタル制御方式の周波数制御装置の構
成を示すブロック図
FIG. 2 is a block diagram showing a configuration of a conventional digital control type frequency control device.

【図3】従来のアナログ制御方式の周波数制御装置の構
成を示すブロック図
FIG. 3 is a block diagram showing the configuration of a conventional analog control type frequency control device.

【符号の説明】[Explanation of symbols]

11 受信回路 12 復調回路 13 CPU 14 メモリ(RAM) 15 D/Aコンバータ 16 可変型基準周波数発振回路 17 PLLシンセサイザループ 11 receiver circuit 12 demodulator circuit 13 CPU 14 memory (RAM) 15 D / A converter 16 variable reference frequency oscillator circuit 17 PLL synthesizer loop

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 受信周波数により常時自己の基準周波数
の補正を行ない、その補正値を新規の基準値データとし
て更新し続ける周波数制御方法。
1. A frequency control method in which a self reference frequency is constantly corrected by a reception frequency and the correction value is continuously updated as new reference value data.
【請求項2】 基地局または中継局からの受信入力信号
を復調した信号を解析して周波数ずれを算出し、その周
波数差を修正してメモリ内に保持された基準周波数デー
タを更新する制御手段と、更新された基準周波数データ
をD/A変換する手段と、D/A変換されたデータを基
に基準周波数を発生する手段とを備えた周波数制御装
置。
2. Control means for analyzing a signal obtained by demodulating a received input signal from a base station or a relay station to calculate a frequency shift, correcting the frequency difference, and updating the reference frequency data held in the memory. And a means for D / A converting the updated reference frequency data, and a means for generating a reference frequency based on the D / A converted data.
JP787395A 1995-01-23 1995-01-23 Frequency control method and device for controlling frequency Pending JPH08204510A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP787395A JPH08204510A (en) 1995-01-23 1995-01-23 Frequency control method and device for controlling frequency

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP787395A JPH08204510A (en) 1995-01-23 1995-01-23 Frequency control method and device for controlling frequency

Publications (1)

Publication Number Publication Date
JPH08204510A true JPH08204510A (en) 1996-08-09

Family

ID=11677751

Family Applications (1)

Application Number Title Priority Date Filing Date
JP787395A Pending JPH08204510A (en) 1995-01-23 1995-01-23 Frequency control method and device for controlling frequency

Country Status (1)

Country Link
JP (1) JPH08204510A (en)

Similar Documents

Publication Publication Date Title
JP3187341B2 (en) Method and apparatus for temperature compensation of a reference oscillator in a communication device
JP5096416B2 (en) Apparatus and method for calibrating local oscillator frequency in wireless communication
JP4267828B2 (en) Frequency generation method and system for wireless devices
KR20000068186A (en) Digital Communication Device
JPH08204510A (en) Frequency control method and device for controlling frequency
JP2009194778A (en) Frequency correcting method and apparatus
JP2001077670A (en) Frequency-correcting circuit and traveling object communications equipment
JP3056197B1 (en) Radio selective call receiver and local frequency generation method
JP2674534B2 (en) Oscillator
US20050184810A1 (en) PLL circuit
JP2639326B2 (en) Quaternary FSK receiver
JP3698543B2 (en) Wireless receiver, wireless transceiver, and circuit for wireless receiver
JPH0637825A (en) Fsk receiver
JPH09326752A (en) Mobile communication terminal equipment
JP3744770B2 (en) Mobile phone
KR100274164B1 (en) Tuner of digital satellite broadcasting reception
JP4618554B2 (en) FSK modulation apparatus and wireless communication apparatus including the same
KR100703448B1 (en) Method for synchronizing with base station in portable radio telephone using wide code division multiple access
JP2024028022A (en) Radio station and frequency error compensation method
JPH06216957A (en) Orthogonal demodulation frequency automatic adjusting circuit
JP2002305442A (en) Method for system for follow up of frequency
JPH10282273A (en) Reference frequency generation device
JP2002314380A (en) System and method for automatically controlling frequency
JP2002353831A (en) Afc system
JPH05206736A (en) Fm demodulation circuit