JPH08204311A - Manufacture of printed wiring board - Google Patents

Manufacture of printed wiring board

Info

Publication number
JPH08204311A
JPH08204311A JP7013589A JP1358995A JPH08204311A JP H08204311 A JPH08204311 A JP H08204311A JP 7013589 A JP7013589 A JP 7013589A JP 1358995 A JP1358995 A JP 1358995A JP H08204311 A JPH08204311 A JP H08204311A
Authority
JP
Japan
Prior art keywords
exposure
resist
printed wiring
light
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7013589A
Other languages
Japanese (ja)
Other versions
JP3538937B2 (en
Inventor
Toshiyuki Suzuki
俊之 鈴木
Jun Matsuyama
純 松山
Kunji Nakajima
勲二 中嶋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP01358995A priority Critical patent/JP3538937B2/en
Publication of JPH08204311A publication Critical patent/JPH08204311A/en
Application granted granted Critical
Publication of JP3538937B2 publication Critical patent/JP3538937B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PURPOSE: To provide a printed wiring board manufacturing method by which selected ones of a plurality of wall surfaces nearly perpendicular to a planar exposure mask positioned against an insulating substrate composed of a three- dimensional molded body exist on the three-dimensional surface of the insulating substrate. CONSTITUTION: In a printed wiring board manufacturing method, a printed wiring board having through holes 7 for forming a printed wiring circuit 2p and a plurality of wall surfaces nearly perpendicular to a plane mask for exposure by forming a resist 3a by irradiating an electrodeposited resist 3 with light through the mask 4 after successively forming a conductive layer 2 and the resist 3 on the surface of a three-dimensional molded body 1 having an insulating property. The method includes a parallel light ray irradiating process in which a prescribed part of the resist 3 is irradiated with parallel light rays 5h and scattered light irradiating process in which the resist 3 formed on prescribed wall surfaces nearly perpendicular to the mask 4 with scatter light 5s through the mask 4.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、立体的なプリント配線
板の製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a three-dimensional printed wiring board.

【0002】[0002]

【従来の技術】従来、立体成形品を絶縁基板とするプリ
ント配線板の製造方法における回路形成は、例えば、特
開平4ー76985号公報に開示されている。すなわ
ち、図4(a)乃至図4(c)に示すように、立体成形
品10の表面を適度な表面粗さに粗化した後、無電解メ
ッキ及び電解メッキ等により、全面に回路導体用の銅等
の導電層20を形成する。次に、その導電層20の表面
に感光性を有する電着レジスト30等の膜を形成し、平
行光50により露光用平面マスク40を介して露光し、
現像してエッチングレジスト等のレジスト30aを形成
した後、露出した導電層20をエッチングすることによ
り、図3(a)に示すように、立体的な絶縁基板の三次
元の表面にプリント配線回路20pを形成するという方
法が用いられてきた。ここで、電着レジスト30は、光
が当たると硬化または溶解する感光性を有し、現像工程
で不要の電着レジスト30を除去して、不要の導電層2
0を露出させると、不要の導電層20は、エッチング液
で溶解され、回路パターンに必要な導電層20は、エッ
チングレジスト等のレジスト30aで覆われて保護され
るためエッチング液で溶解されずに残る。したがって、
エッチングが完了した後は、使用したエッチングレジス
ト等のレジスト30aを剥離液で剥離を行うことにより
上記の導電層20からプリント配線回路20pが立体成
形品10の三次元の表面に形成される。ポジ型(光溶解
型)の電着レジスト30を使用した場合には、露光され
た部分のみ電着レジスト30が分解され下地の導電層2
0が露出される。すなわち、未露光部の電着レジスト3
0はそのまま残り、エッチングレジスト等のレジスト3
0aとなり、回路パターンになる。逆にネガ型(光硬化
型)の電着レジストを使用した場合には、露光された部
分のみレジストが硬化し、未露光部のレジストが現像で
溶解する。すなわち、露光部の電着レジスト30はその
まま残り、回路パターンになる。
2. Description of the Related Art Conventionally, circuit formation in a method of manufacturing a printed wiring board using a three-dimensional molded product as an insulating substrate is disclosed in, for example, Japanese Patent Laid-Open No. 4-76985. That is, as shown in FIGS. 4 (a) to 4 (c), after roughening the surface of the three-dimensional molded article 10 to an appropriate surface roughness, the entire surface for circuit conductors is subjected to electroless plating or electrolytic plating. A conductive layer 20 of copper or the like is formed. Next, a film such as an electrodeposition resist 30 having photosensitivity is formed on the surface of the conductive layer 20, and exposed by parallel light 50 through the exposure flat mask 40,
After developing to form a resist 30a such as an etching resist, the exposed conductive layer 20 is etched to form a printed wiring circuit 20p on the three-dimensional surface of a three-dimensional insulating substrate as shown in FIG. 3A. Has been used. Here, the electrodeposition resist 30 has a photosensitivity that cures or dissolves when exposed to light, and the unnecessary electrodeposition resist 30 is removed in the developing process to remove the unnecessary conductive layer 2.
When 0 is exposed, the unnecessary conductive layer 20 is dissolved by the etching solution, and the conductive layer 20 necessary for the circuit pattern is covered with and protected by the resist 30a such as an etching resist and therefore is not dissolved by the etching solution. Remain. Therefore,
After the etching is completed, the printed wiring circuit 20p is formed on the three-dimensional surface of the three-dimensional molded product 10 from the conductive layer 20 by peeling the resist 30a such as the used etching resist with a peeling liquid. When the positive type (photo-dissolving type) electrodeposition resist 30 is used, the electrodeposition resist 30 is decomposed only in the exposed portion and the underlying conductive layer 2 is used.
0 is exposed. That is, the electrodeposition resist 3 in the unexposed area
0 remains as it is and resist 3 such as etching resist
It becomes 0a and becomes a circuit pattern. On the contrary, when a negative type (photo-curing type) electrodeposition resist is used, the resist is hardened only in the exposed part, and the resist in the unexposed part is dissolved by the development. That is, the electrodeposition resist 30 in the exposed portion remains as it is and becomes a circuit pattern.

【0003】しかし、前記のような方法では、図3
(b)、図3(e)及び図3(f)等に示すようなプリ
ント配線板を得ることができなかった。すなわち、立体
成形品10の略垂直な壁面10sが複数ある場合、これ
らの略垂直な壁面10sの中で所定の略垂直な壁面10
sを選択的に露光することができず、略垂直な壁面10
sの全てに導電層20が形成されてしまうか、あるい
は、略垂直な壁面10sのいずれにも導電層20が形成
されないかのいずれかであった。特開平4ー76985
号公報に開示されている実施例では、ポジ型の電着レジ
スト30を使用している。すなわち、図4(a)及び図
4(b)に示すように、ポジ型の電着レジスト30を使
用した場合には、露光用平面マスク40の透明部分であ
る露光部40aを光が透過しても、露光用平面マスク4
0に対する仮想垂直線40sと平行に平行光50を照射
するために、略垂直の壁面10sに形成されたポジ型の
電着レジスト30は露光されないので、図4(c)に示
すように、略垂直の壁面10sの略全面にエッチングレ
ジスト等のレジスト30aが残りパターンニングできな
い。したがって、図3(c)に示すように、略垂直な壁
面10s全てに導電層20が形成されてしまう。立体成
形品10の略垂直な壁面10sに不要な導電層20が形
成されると、例えば、後工程の実装封止で、封止樹脂と
回路金属の密着が悪いので、この封止樹脂と回路金属と
の界面から水分が侵入し、信頼性が悪くなってしまうと
いう問題があった。
However, in the method as described above, FIG.
It was not possible to obtain a printed wiring board as shown in (b), FIG. 3 (e) and FIG. 3 (f). That is, when there are a plurality of substantially vertical wall surfaces 10s of the three-dimensional molded product 10, a predetermined substantially vertical wall surface 10 among these substantially vertical wall surfaces 10s.
s cannot be selectively exposed, and the wall surface 10 is substantially vertical.
Either the conductive layer 20 is formed on all s, or the conductive layer 20 is not formed on any of the substantially vertical wall surfaces 10s. Japanese Unexamined Patent Publication No. 4-76985
In the embodiment disclosed in the publication, a positive type electrodeposition resist 30 is used. That is, as shown in FIGS. 4A and 4B, when the positive electrodeposition resist 30 is used, light is transmitted through the exposed portion 40a which is a transparent portion of the exposure flat mask 40. However, the exposure plane mask 4
In order to irradiate the parallel light 50 parallel to the virtual vertical line 40s for 0, the positive electrodeposition resist 30 formed on the substantially vertical wall surface 10s is not exposed. Therefore, as shown in FIG. The resist 30a such as an etching resist remains on the substantially entire surface of the vertical wall surface 10s, and patterning cannot be performed. Therefore, as shown in FIG. 3C, the conductive layer 20 is formed on all substantially vertical wall surfaces 10s. When the unnecessary conductive layer 20 is formed on the substantially vertical wall surface 10s of the three-dimensional molded product 10, for example, the sealing resin and the circuit metal are poorly adhered to each other in the mounting and sealing in the subsequent step, so that the sealing resin and the circuit are not formed. There is a problem that moisture enters from the interface with the metal and the reliability deteriorates.

【0004】そのために、従来は図3(a)に示すよう
に、例えば、導電層20を形成が不要な立体成形品10
の壁面を垂直にせず、角度をつけて傾斜面10kとする
ことにより、この傾斜面10kには導電層20を形成せ
ず、貫通孔70の略垂直な壁面10sには導電層20を
形成するというようにしていたために、基板が大きくな
ってしまうという問題があった。また、小型化するため
には、図3(f)に示すように、略垂直な壁面10sで
回路を絶縁する。ところが、略垂直な壁面10sで回路
を絶縁したくても、導電層20を形成しなければならな
いスルーホール等の貫通孔70の略垂直な壁面10sが
ある場合には、前記と同様、複数の略垂直な壁面10s
から、選択的に所定の略垂直な壁面10sを露光するこ
とができなかった。
Therefore, conventionally, as shown in FIG. 3A, for example, a three-dimensional molded product 10 which does not require formation of the conductive layer 20 is used.
By forming the inclined surface 10k at a certain angle without making the wall surface vertical, the conductive layer 20 is not formed on the inclined surface 10k, and the conductive layer 20 is formed on the substantially vertical wall surface 10s of the through hole 70. Therefore, there is a problem that the substrate becomes large. Further, in order to reduce the size, as shown in FIG. 3 (f), the circuit is insulated by the substantially vertical wall surface 10s. However, even if it is desired to insulate the circuit with the substantially vertical wall surface 10s, if there is the substantially vertical wall surface 10s of the through hole 70 such as the through hole in which the conductive layer 20 has to be formed, a plurality of wall surfaces 10s are formed as described above. Almost vertical wall surface 10s
Therefore, it was not possible to selectively expose the predetermined substantially vertical wall surface 10s.

【0005】逆にネガ型の電着レジスト30を使用した
場合でも、露光された部分のみ電着レジスト30が硬化
し、未露光部の電着レジスト30が現像で溶解する。す
なわち、図5(a)及び図5(b)に示すように、露光
用平面マスク40に対する仮想垂直線40sと平行に平
行光50を照射するために、貫通孔70の略垂直な壁面
10sに形成されたネガ型の電着レジスト30は露光さ
れないので、図5(c)に示すように、貫通孔70等の
略垂直な壁面10sにエッチングレジスト等のレジスト
30aが形成されない。したがって、図3(d)に示す
ように、略垂直な壁面10sのいずれにも導電層20が
形成されず、所定の面にプリント配線回路形成(パター
ニング)ができないという問題があった。以上の説明
は、図3(b)、図3(e)及び図3(f)等に示すよ
うなプリント配線板、すなわち、立体成形品10の略垂
直な壁面10sが複数ある場合、これらの略垂直な壁面
10sの中で所定の略垂直な壁面10sを選択的に露光
することができず、略垂直な壁面10sの全てに導電層
20が形成されてしまうか、あるいは、略垂直な壁面1
0sのいずれにも導電層20が形成されないかのいずれ
かであるという点で共通の問題であるが、特に、図3
(b)に示すようなプリント配線板、すなわち、貫通孔
70が段部を有し、1つの貫通孔70が複数の略垂直な
壁面10sを有する場合には、これらの略垂直な壁面1
0sの中で所定の略垂直な壁面10sを選択的に露光す
ることが、さらに困難であった。
On the contrary, even when the negative electrodeposition resist 30 is used, the electrodeposition resist 30 is cured only in the exposed portion, and the unexposed portion of the electrodeposition resist 30 is dissolved by the development. That is, as shown in FIGS. 5A and 5B, in order to irradiate the parallel light 50 in parallel with the virtual vertical line 40 s with respect to the exposure plane mask 40, the substantially vertical wall surface 10 s of the through hole 70 is irradiated. Since the formed negative electrodeposition resist 30 is not exposed, the resist 30a such as an etching resist is not formed on the substantially vertical wall surface 10s such as the through hole 70 as shown in FIG. 5C. Therefore, as shown in FIG. 3D, there is a problem that the conductive layer 20 is not formed on any of the substantially vertical wall surfaces 10s, and the printed wiring circuit cannot be formed (patterned) on a predetermined surface. In the above description, when there are a plurality of substantially vertical wall surfaces 10s of the printed wiring board, that is, the three-dimensional molded product 10 as shown in FIGS. A predetermined substantially vertical wall surface 10s cannot be selectively exposed out of the substantially vertical wall surface 10s, and the conductive layer 20 is formed on all of the substantially vertical wall surface 10s, or the substantially vertical wall surface 10s. 1
This is a common problem in that the conductive layer 20 is not formed on any of the 0s.
In the case of a printed wiring board as shown in (b), that is, when the through hole 70 has a step portion and one through hole 70 has a plurality of substantially vertical wall surfaces 10s, these substantially vertical wall surfaces 1
It was more difficult to selectively expose a predetermined substantially vertical wall surface 10s within 0 s.

【0006】[0006]

【発明が解決しようとする課題】本発明は前記の事実に
鑑みてなされたもので、その目的とするところは、立体
成形品からなる絶縁基板の三次元の表面で、立体成形品
に配設された露光用平面マスクに対して略垂直な壁面が
複数ある場合に、これらの略垂直な壁面の中から選択的
に、所定の略垂直な壁面に確実に露光ができるプリント
配線板の製造方法を提供することにある。
SUMMARY OF THE INVENTION The present invention has been made in view of the above facts, and an object of the present invention is to provide a three-dimensional surface of an insulating substrate composed of a three-dimensional molded product, which is disposed on the three-dimensional molded product. When there are a plurality of substantially vertical wall surfaces with respect to the exposed exposure plane mask, a method of manufacturing a printed wiring board capable of reliably performing exposure on a predetermined substantially vertical wall surface from these substantially vertical wall surfaces To provide.

【0007】[0007]

【課題を解決するための手段】本発明の請求項1に係る
プリント配線板の製造方法は、絶縁性を有する立体成形
品1の表面に、導電層2を形成し、この導電層2に感光
性を有する電着レジスト3を形成するとともに、露光用
平面マスク4を介して光を照射し、電着レジスト3を露
光、現像してレジスト3aを形成することによりプリン
ト配線回路2pを形成する貫通孔7を備え、露光用平面
マスク4に対して複数の略垂直な壁面1sを有するプリ
ント配線板の製造方法において、立体成形品1に配設さ
れた露光部4aと未露光部4bとを備えた露光用平面マ
スク4を介して、平行光5hを照射して所定の電着レジ
スト3を露光する平行光露光工程と、露光用平面マスク
4を介して、散乱光5sを照射して露光用平面マスク4
に対して所定の略垂直な壁面1sに形成された電着レジ
スト3を露光する散乱光露光工程とを有することを特徴
とする。
A method for manufacturing a printed wiring board according to claim 1 of the present invention comprises forming a conductive layer 2 on the surface of a three-dimensional molded article 1 having an insulating property and exposing the conductive layer 2 to light. Which forms the printed wiring circuit 2p by forming the electro-deposition resist 3 having the property and exposing the electro-deposition resist 3 by exposing it to light through the exposure flat mask 4 to form the resist 3a. A method for manufacturing a printed wiring board having holes 7 and having a plurality of substantially perpendicular wall surfaces 1s with respect to the exposure plane mask 4, comprising an exposed portion 4a and an unexposed portion 4b arranged in the three-dimensional molded article 1. The parallel light exposure step of irradiating the predetermined electrodeposition resist 3 by irradiating the parallel light 5h through the exposure plane mask 4 and the exposure by irradiating the scattered light 5s through the exposure plane mask 4 Plane mask 4
And a scattered light exposure step of exposing the electrodeposition resist 3 formed on a predetermined substantially vertical wall surface 1s.

【0008】本発明の請求項2に係るプリント配線板の
製造方法は、前記貫通孔7が段部を有し、貫通孔7の小
さい開口部7k側の立体成形品1の表面に光乱反射板8
hを配設して小さい開口部7kを覆い、貫通孔7の大き
い開口部7t側の立体成形品1の表面に露光用平面マス
ク4を配設し、この露光用平面マスク4を介して平行光
5hを照射して所定の電着レジスト3を露光する平行光
露光工程と、前記大きい開口部7t側の立体成形品1の
表面に光吸収板8kを配設して大きい開口部7tを覆
い、前記小さい開口部7k側の立体成形品1の表面に露
光用平面マスク4を配設し、この露光用平面マスク4を
介して散乱光5sを照射して所定の電着レジスト3を露
光する散乱光露光工程とを有することを特徴とする。
In the method for manufacturing a printed wiring board according to claim 2 of the present invention, the through hole 7 has a step portion, and the diffused reflection plate is provided on the surface of the three-dimensional molded article 1 on the side of the small opening portion 7k of the through hole 7. 8
An exposure plane mask 4 is provided on the surface of the three-dimensional molded article 1 on the side of the large opening 7t of the through hole 7 to cover the small opening 7k. A parallel light exposure step of irradiating a predetermined electrodeposition resist 3 by irradiating light 5h, and a light absorbing plate 8k are provided on the surface of the three-dimensional molded article 1 on the side of the large opening 7t to cover the large opening 7t. An exposure plane mask 4 is provided on the surface of the three-dimensional molded article 1 on the side of the small opening 7k, and a predetermined electrodeposition resist 3 is exposed by irradiating scattered light 5s through the exposure plane mask 4. And a scattered light exposure step.

【0009】[0009]

【作用】本発明の請求項1に係るプリント配線板の製造
方法では、立体成形品1に配設された露光部4aと未露
光部4bとを備えた露光用平面マスク4を介して、平行
光5hを照射して電着レジスト3を露光する平行光露光
工程で、露光用平面マスク4に対して略垂直な壁面1s
に形成された電着レジスト3以外の所定の電着レジスト
3を精度良く露光し、平行光露光工程で露光することが
できない露光用平面マスク4に対して略垂直な壁面1s
が複数ある場合に、これらの略垂直な壁面1sの中から
選択的に、所定の略垂直な壁面1sに形成された電着レ
ジスト3を、露光用平面マスク4を介して散乱光5sを
照射して露光する散乱光露光工程で露光するので、所定
の垂直な壁面1sに形成された電着レジスト3を確実に
露光できる。
In the method for manufacturing a printed wiring board according to the first aspect of the present invention, the three-dimensional molded article 1 is parallelized through the exposure flat mask 4 having the exposed portion 4a and the unexposed portion 4b. In the parallel light exposure step of irradiating the electrodeposition resist 3 by irradiating the light 5h, the wall surface 1s substantially perpendicular to the exposure plane mask 4 is exposed.
The predetermined electrodeposition resist 3 other than the electrodeposition resist 3 formed on the surface is accurately exposed, and a wall surface 1s substantially perpendicular to the exposure plane mask 4 that cannot be exposed in the parallel light exposure process.
In the case where there are a plurality of these, the electrodeposition resist 3 formed on the predetermined substantially vertical wall surface 1s is selectively irradiated from the substantially vertical wall surface 1s with the scattered light 5s through the exposure plane mask 4. Since the exposure is performed in the scattered light exposure step of exposing the electrodeposited resist film 3 to the predetermined vertical wall surface 1s, the electrodeposition resist 3 can be reliably exposed.

【0010】本発明の請求項2に係るプリント配線板の
製造方法では、前記貫通孔7が段部を有し、貫通孔7の
小さい開口部7k側の立体成形品1の表面に光乱反射板
8hを配設して小さい開口部7kを覆い、貫通孔7の大
きい開口部7t側の立体成形品1の表面に露光用平面マ
スク4を配設し、この露光用平面マスク4を介して平行
光5hを照射して所定の電着レジスト3を露光する平行
光露光工程を有するので、この平行光5hが光乱反射板
8hに当たって乱反射することによって散乱光5sとな
るため、この乱反射した散乱光5sによって、露光用平
面マスク4に対して垂直な壁面1sに形成された所定の
電着レジスト3が露光される。しかも、前記大きい開口
部7t側の立体成形品1の表面に光吸収板8kを配設し
て大きい開口部7tを覆い、前記小さい開口部7k側の
立体成形品1の表面に露光用平面マスク4を配設し、こ
の露光用平面マスク4を介して散乱光5sを照射して所
定の電着レジスト3を露光する散乱光露光工程を有する
ので、照射された散乱光5sが光吸収板8kで吸収さ
れ、空間7aを形成する露光不要の垂直な壁面1s等の
面に、散乱光5sが照射されるのを防止するため、露光
不要の垂直な壁面1s等の面に形成された電着レジスト
3が露光され難い。すなわち、貫通孔7が段部を有し、
1つの貫通孔7が複数の略垂直な壁面1sを有する場合
であっても、これらの略垂直な壁面1sの中で所定の略
垂直な壁面1sを選択的に露光することができる。
In the method for manufacturing a printed wiring board according to the second aspect of the present invention, the through hole 7 has a step portion, and the diffused reflection plate is provided on the surface of the three-dimensional molded article 1 on the side of the small opening portion 7k of the through hole 7. 8h is provided to cover the small opening 7k, the exposure plane mask 4 is provided on the surface of the three-dimensional molded article 1 on the side of the large opening 7t of the through hole 7, and the exposure plane mask 4 is used for parallelization. Since there is a parallel light exposure step of irradiating the predetermined electrodeposition resist 3 by irradiating the light 5h, the parallel light 5h hits the diffused light reflection plate 8h and is diffused to become the scattered light 5s. Thus, the predetermined electrodeposition resist 3 formed on the wall surface 1s perpendicular to the exposure plane mask 4 is exposed. Moreover, a light absorbing plate 8k is provided on the surface of the three-dimensional molded article 1 on the side of the large opening 7t to cover the large opening 7t, and a flat mask for exposure is formed on the surface of the three-dimensional molded article 1 on the side of the small opening 7k. 4 is provided, and since there is a scattered light exposure step of exposing the predetermined electrodeposition resist 3 by irradiating the scattered light 5s through the exposure plane mask 4, the irradiated scattered light 5s emits the scattered light 5s. In order to prevent the scattered light 5s from being radiated to the surface of the vertical wall surface 1s or the like which is absorbed by the above and does not need to be exposed, the electrodeposition formed on the surface of the vertical wall surface 1s or the like which is not exposed. The resist 3 is hard to be exposed. That is, the through hole 7 has a step,
Even when one through hole 7 has a plurality of substantially vertical wall surfaces 1s, a predetermined substantially vertical wall surface 1s can be selectively exposed among these substantially vertical wall surfaces 1s.

【0011】[0011]

【実施例】以下、本発明を実施例によって、具体的に説
明する。
EXAMPLES The present invention will be specifically described below with reference to examples.

【0012】図1に第1実施例を示す。図1(a)に示
すように、プリント配線板の立体的な絶縁基板となるス
ルーホール等の貫通孔7を備えた凹凸のある形状からな
る立体成形品1は、例えば、熱硬化性樹脂又は熱可塑性
樹脂等を使用して射出成形等により成形して得られたも
のである。例えば、液晶ポリマー(ポリプラスチックス
社製:商品名ベクトラ)等のスーパーエンプラを使用し
て射出成形で成形する。もちろん射出成形のみに限定さ
れるものではなく、切削加工により貫通孔7を備えた凹
凸のある立体成形品1に仕上げてもよい。この立体成形
品1の三次元の表面を強アルカリ溶液で適度な表面粗さ
に粗面化処理した後パラジウムの核付け処理をして導電
層2を密着し易くした後、例えば、無電解銅めっき、ス
パッタリング又は蒸着等を立体成形品1の表面全面に施
し、その上に電気銅めっきで所要の厚みをつけて、全面
に回路導体用の導電層2を形成する。次に、その導電層
2の表面に感光性を有する電着レジスト3、例えば光硬
化型(ネガ型)又は光溶解型(ポジ型)の電着レジスト
3を形成する。
FIG. 1 shows a first embodiment. As shown in FIG. 1A, a three-dimensional molded article 1 having a concavo-convex shape provided with through-holes 7 such as through-holes serving as a three-dimensional insulating substrate of a printed wiring board is formed of, for example, thermosetting resin or It is obtained by molding by injection molding or the like using a thermoplastic resin or the like. For example, injection molding is performed using a super engineering plastic such as liquid crystal polymer (manufactured by Polyplastics Co .: trade name Vectra). Of course, the present invention is not limited to injection molding, and the three-dimensional molded article 1 having the through holes 7 may be finished by cutting. After roughening the three-dimensional surface of the three-dimensional molded article 1 with a strong alkaline solution to a suitable surface roughness and then nucleating palladium to facilitate adhesion of the conductive layer 2, for example, electroless copper Plating, sputtering, vapor deposition, or the like is performed on the entire surface of the three-dimensional molded article 1, and a required thickness is formed on the surface by electrolytic copper plating to form a conductive layer 2 for a circuit conductor on the entire surface. Next, an electro-deposition resist 3 having photosensitivity, for example, a photo-curing (negative) or photo-dissolution (positive) electro-deposition resist 3 is formed on the surface of the conductive layer 2.

【0013】感光性を有するレジストとして、電着レジ
スト3が好ましい理由は、一般の液状レジストでは、立
体成形品1の凹凸のある三次元の表面に形成した場合に
凹凸への追従性は、10μm程度までであり、回路形成
の精度が悪いのに対し、電着レジスト3では、立体成形
品1の凹凸のある三次元の表面に完全に追従して密着で
き、回路形成の精度が良くなるためである。ここで、光
硬化型の電着レジスト3は、光が当たる(露光する)と
硬化し、光溶解型の電着レジスト3は、光が当たると溶
解する。したがって、例えば、光硬化型(ネガ型)の電
着レジスト(シプレイ社製:商品名イーグル)を電気泳
動で導電層2の表面に形成し、次いで、例えば、図1
(b)に示すように、立体成形品1に配設された露光部
4aと未露光部4bとを備えた露光用平面マスク4に対
する仮想垂直線4sと平行に、平行露光機6h等の露光
装置を用いて、紫外線等の平行光5hで露光用平面マス
ク4を介して露光を行う。図1(b)では、平行露光機
6hを、光源6kとレンズ6rとによって、模式的に示
した。平行光5hは、例えば、レンズ6r等の焦点に光
源6kを置き、レンズ6rを通過させることにより得る
ことができる。すなわち、平行光5hとは、例えば、あ
る位置で遮蔽板を用いて遮った場合の遮蔽板の露光面積
と、位置を変えて遮蔽板を用いて遮った場合の遮蔽板の
露光面積とが略同じであるような光である。したがっ
て、平行光5hを用いると露光精度がよい。
The reason why the electrodeposition resist 3 is preferable as the resist having photosensitivity is that, when a general liquid resist is formed on the uneven three-dimensional surface of the three-dimensional molded article 1, the followability to the unevenness is 10 μm. Although the accuracy of circuit formation is poor, the electrodeposition resist 3 can perfectly follow and adhere to the uneven three-dimensional surface of the three-dimensional molded product 1, and the accuracy of circuit formation is improved. Is. Here, the photocurable electrodeposition resist 3 is cured when exposed to light (exposed), and the photodissolving electrodeposition resist 3 is dissolved when exposed to light. Therefore, for example, a photo-curable (negative) electrodeposition resist (manufactured by Shipley Co., Ltd .: trade name Eagle) is formed on the surface of the conductive layer 2 by electrophoresis, and then, for example, as shown in FIG.
As shown in (b), exposure of a parallel exposure machine 6h or the like is performed in parallel with the virtual vertical line 4s for the exposure plane mask 4 provided with the exposed portion 4a and the unexposed portion 4b arranged in the three-dimensional molded article 1. The apparatus is used to perform exposure with parallel light 5h such as ultraviolet rays through the exposure plane mask 4. In FIG. 1B, the parallel exposure device 6h is schematically shown by the light source 6k and the lens 6r. The parallel light 5h can be obtained, for example, by placing the light source 6k at the focal point of the lens 6r or the like and passing it through the lens 6r. That is, the collimated light 5h is, for example, the exposure area of the shield plate when the shield plate is used to shield the light at a certain position and the exposure area of the shield plate when the shield plate is shielded at a different position. The light is the same. Therefore, the exposure accuracy is good when the parallel light 5h is used.

【0014】ところが、平行光5hの照射方向に対し
て、垂直な壁面1sは、平行光5hを用いると殆ど露光
されない。すなわち、平行光5hのみでは、垂直な壁面
1sに形成された所定の電着レジスト3を露光できな
い。したがって、平行光5hを用いて露光した後、ある
いは露光する前に、図1(c)に示すように、例えば、
前記露光用平面マスク4を、貫通孔7に露光部4aを当
接するようにした所定の露光用平面マスク4を用いて、
この露光用平面マスク4を介して散乱露光機6s等の露
光装置を使用して、紫外線等の散乱光5sの光で露光を
行う。平行光5hでは貫通孔7等の垂直な壁面1sに形
成された電着レジスト3を露光することが困難である
が、散乱光5sを用いることにより、垂直な壁面1sに
形成された電着レジスト3を容易に露光することができ
る。すなわち、散乱光5sとは、例えば、ある位置で遮
蔽板を用いて遮った場合の遮蔽板の露光面積と、位置を
変えて遮蔽板を用いて遮った場合の遮蔽板の露光面積と
が異なる。すなわち、散乱光5sとは、散乱光5sの光
源と遮蔽板との距離が離れるにしたがい、露光面積が大
きくなるような光である。したがって、散乱光5sを用
いると、散乱光5sの照射方向に対して、垂直な壁面1
sでも露光することができる。ところが、散乱光5sを
用いると露光精度が低くなる。すなわち、散乱光5sの
みでは、電着レジスト3を精度良く露光することができ
ない。したがって、平行光5hを照射して所定の電着レ
ジスト3を露光する平行光露光工程と、散乱光5sを照
射して、露光用平面マスク4に対して略垂直な壁面1s
に形成された電着レジスト3を露光する散乱光露光工程
とを有するので、露光用平面マスク4に対して略垂直な
壁面1sが複数ある場合に、これらの略垂直な壁面1s
の中から選択的に、所定の略垂直な壁面1sに形成され
た電着レジスト3をを確実に露光できる。
However, the wall surface 1s perpendicular to the irradiation direction of the parallel light 5h is hardly exposed when the parallel light 5h is used. That is, the predetermined electrodeposition resist 3 formed on the vertical wall surface 1s cannot be exposed only by the parallel light 5h. Therefore, as shown in FIG. 1 (c), after the exposure using the parallel light 5h or before the exposure, for example,
The exposure plane mask 4 is formed by using a predetermined exposure plane mask 4 in which the exposure portion 4a is brought into contact with the through hole 7.
Through the exposure flat mask 4, an exposure device such as a scattering exposure device 6s is used to perform exposure with light of scattered light 5s such as ultraviolet light. It is difficult to expose the electrodeposition resist 3 formed on the vertical wall surface 1s such as the through hole 7 with the parallel light 5h, but by using the scattered light 5s, the electrodeposition resist 3 formed on the vertical wall surface 1s is exposed. 3 can be easily exposed. That is, for example, the scattered light 5s is different in the exposure area of the shielding plate when the shielding plate is used to block the light at a certain position and the exposure area of the shielding plate when the shielding plate is used to change the position. . That is, the scattered light 5s is such light that the exposure area increases as the distance between the light source of the scattered light 5s and the shield plate increases. Therefore, when the scattered light 5s is used, the wall surface 1 perpendicular to the irradiation direction of the scattered light 5s
can also be exposed. However, when the scattered light 5s is used, the exposure accuracy becomes low. That is, the electrodeposited resist 3 cannot be accurately exposed with only the scattered light 5s. Therefore, the parallel light exposure step of irradiating the predetermined electrodeposition resist 3 by irradiating the parallel light 5h and the wall surface 1s substantially perpendicular to the exposure plane mask 4 by irradiating the scattered light 5s.
Since there is a scattered light exposure step of exposing the electrodeposition resist 3 formed on the substrate 1, if there are a plurality of wall surfaces 1s substantially perpendicular to the exposure plane mask 4, these wall surfaces 1s substantially perpendicular to each other.
It is possible to reliably expose the electrodeposition resist 3 formed on the predetermined substantially vertical wall surface 1s selectively from the above.

【0015】そのため、図1(d)に示すように、未露
光部の電着レジスト3がアルカリ水溶液等の現像液で溶
解除去され、未露光部に導電層2が露出し、露光部の電
着レジスト3がレジスト3aとして導電層2を覆った状
態になる。すなわち、立体成形品1からなる絶縁基板の
三次元の表面で、垂直な壁面1sであって、レジスト不
要面にはレジスト3aを形成せず、かつ、例えば、貫通
孔7等のレジスト必要面にレジスト3aを形成すること
ができる。もちろん、露光の順序を入れ換えて、図1
(c)に示すように、露光用平面マスク4を介して散乱
光5sで露光を行った後に、図1(b)に示すように、
平行光5hで露光を行ってもよい。一方、光溶解型(ポ
ジ型)の電着レジスト3を用いた場合には、逆に露光部
の電着レジスト3が現像液で溶解除去され、露光部に導
電層2が露出し、未露光部の電着レジスト3がレジスト
3aとして導電層2を覆った状態になる。この露出した
導電層2を現像により、例えば、塩化第二銅溶液等のエ
ッチング液で化学的に溶解する。エッチングが完了した
後は、使用したレジスト3aを塩化メチレン等の剥離液
で剥離を行うと、図1(e)に示すように、導電層2に
プリント配線回路2pが形成される。すなわち、光硬化
型の電着レジスト3を用いた場合には、露光部にプリン
ト配線回路2pが形成され、光溶解型の電着レジスト3
を用いた場合には、逆に未露光部にプリント配線回路2
pが形成されることになる。
Therefore, as shown in FIG. 1D, the electrodeposition resist 3 in the unexposed portion is dissolved and removed by a developing solution such as an alkaline aqueous solution, and the conductive layer 2 is exposed in the unexposed portion, so that the exposed portion is not exposed. The deposition resist 3 serves as a resist 3a and covers the conductive layer 2. That is, on the three-dimensional surface of the insulating substrate composed of the three-dimensional molded product 1, which is the vertical wall surface 1s, the resist 3a is not formed on the resist unnecessary surface, and the resist required surface such as the through hole 7 is formed. The resist 3a can be formed. Of course, by changing the order of exposure,
As shown in FIG. 1C, after the exposure with the scattered light 5s through the exposure flat mask 4, as shown in FIG.
The parallel light 5h may be used for the exposure. On the other hand, when the photo-dissolving (positive type) electrodeposition resist 3 is used, conversely, the electrodeposition resist 3 in the exposed area is dissolved and removed by the developing solution, and the conductive layer 2 is exposed in the exposed area and unexposed. The part of the electrodeposition resist 3 serves as a resist 3a and covers the conductive layer 2. The exposed conductive layer 2 is chemically dissolved by an etching solution such as a cupric chloride solution by development. After the etching is completed, the used resist 3a is stripped with a stripping solution such as methylene chloride to form a printed wiring circuit 2p on the conductive layer 2 as shown in FIG. 1 (e). That is, when the photo-curable electrodeposition resist 3 is used, the printed wiring circuit 2p is formed in the exposed portion, and the photo-melting electrodeposition resist 3 is formed.
On the contrary, when the printed wiring circuit 2 is used in the unexposed portion,
p will be formed.

【0016】以上のようにして、立体成形品1からなる
絶縁基板の三次元の表面で、立体成形品1に配設された
露光用平面マスク4に対して略垂直な壁面1sが複数あ
る場合に、これらの略垂直な壁面1sの中から選択的
に、所定の略垂直な壁面1sに形成された電着レジスト
3を、露光用平面マスク4を介して散乱光5sを照射し
て露光する散乱光露光工程で露光するので、所定の垂直
な壁面1sに形成された電着レジスト3を確実に露光で
きる。
As described above, when the three-dimensional surface of the insulating substrate made of the three-dimensional molded product 1 has a plurality of wall surfaces 1s substantially perpendicular to the exposure flat mask 4 arranged on the three-dimensional molded product 1. Then, the electrodeposition resist 3 formed on the predetermined substantially vertical wall surface 1s is selectively exposed from the substantially vertical wall surface 1s by irradiating scattered light 5s through the exposure plane mask 4. Since the exposure is performed in the scattered light exposure step, the electrodeposition resist 3 formed on the predetermined vertical wall surface 1s can be reliably exposed.

【0017】図2に第2実施例を示す。図2(a)に示
すように、プリント配線板の立体的な絶縁基板となるス
ルホール等の貫通孔7を備えた凹凸のある形状からなる
立体成形品1の全面に、第1実施例と同様にして、回路
導体用の導電層2を形成し、次に、この導電層2の表面
に感光性を有する電着レジスト3、例えば光硬化型(ネ
ガ型)の電着レジスト3を形成する。前記貫通孔7は、
例えば、垂直な壁面1sにより形成された、断面積の大
きい空間7aと断面積の小さい空間7sとが連通したよ
うな段部を有するものであってもよい。図2(b)に示
すように、貫通孔7の断面積の小さい空間7sの小さい
開口部7k側の立体成形品1の表面に光乱反射板8hを
配設する。この光乱反射板8hとしては、例えば、表面
に微細な凹凸を有する金属板を使用し、光が当たると散
乱光5sを乱反射する。貫通孔7の断面積の大きい空間
7aの大きい開口部7t側の立体成形品1の表面には、
露光用平面マスク4を配設する。この露光用平面マスク
4を介して平行光5hを照射する。この平行光5hが光
乱反射板8hに当たって散乱光5sを乱反射する。この
乱反射した散乱光5sが断面積の小さい空間7sの垂直
な壁面1sに形成された所定の電着レジスト3を露光す
る。
FIG. 2 shows a second embodiment. As shown in FIG. 2A, the same as in the first embodiment, on the entire surface of the three-dimensional molded product 1 having a concave and convex shape provided with through holes 7 such as through holes which serve as a three-dimensional insulating substrate of the printed wiring board. Then, the conductive layer 2 for the circuit conductor is formed, and then the electrodeposition resist 3 having photosensitivity, for example, the photocurable (negative) electrodeposition resist 3 is formed on the surface of the conductive layer 2. The through hole 7 is
For example, it may have a stepped portion formed by the vertical wall surface 1s such that the space 7a having a large cross-sectional area and the space 7s having a small cross-sectional area communicate with each other. As shown in FIG. 2B, a diffused reflection plate 8h is provided on the surface of the three-dimensional molded product 1 on the side of the opening 7k having a small space 7s having a small cross-sectional area of the through hole 7. As the diffused reflection plate 8h, for example, a metal plate having fine irregularities on the surface is used, and diffuses the scattered light 5s when the light hits. On the surface of the three-dimensional molded product 1 on the side of the large opening 7t of the space 7a having a large cross-sectional area of the through hole 7,
An exposure plane mask 4 is provided. Parallel light 5h is emitted through the exposure plane mask 4. The parallel light 5h strikes the diffused reflector 8h and diffusely reflects the scattered light 5s. The diffused scattered light 5s exposes a predetermined electrodeposition resist 3 formed on the vertical wall surface 1s of the space 7s having a small cross-sectional area.

【0018】次いで、前記大きい開口部7t側の立体成
形品1の表面に、露光用平面マスク4に代えて、例え
ば、黒のゴム板等の光吸収板8kを配設し、前記小さい
開口部7k側の立体成形品1の表面に、光乱反射板8h
に代えて、露光用平面マスク4を配設し、この露光用平
面マスク4を介して、散乱露光機6s等の露光装置を用
いて、紫外線等の散乱光5sを照射して断面積の小さい
空間7sの垂直な壁面1sに形成された所定の電着レジ
スト3と前記小さい開口部7k側の立体成形品1の表面
の所定の電着レジスト3とを露光する。この場合、露光
用平面マスク4は基板と密着させておき、平面の露光の
切れ性を良くする。平行光5hでは略垂直な壁面1sの
所定の電着レジスト3を露光することは困難であるが、
散乱光5sを用いることにより、容易に露光することが
できる。さらに、散乱露光機6s等の露光装置を用い
て、紫外線等の散乱光5sを照射する場合に、前記大き
い開口部7t側の立体成形品1の表面に光吸収板8kを
配設し、前記小さい開口部7k側の立体成形品1の表面
に露光用平面マスク4を配設しているので、照射された
散乱光5sが光吸収板8kで吸収され、断面積の大きい
空間7aを形成する垂直な壁面1sに散乱光5sが照射
されるのを防止する。すなわち、断面積の小さい空間7
sから入り込んだ散乱光5sが吸収され、断面積の大き
い空間7aを形成する垂直な壁面1sの露光不要の電着
レジスト3が露光され難くなるので、所望の露光ができ
る。すなわち、垂直な壁面1sに形成された所定の電着
レジスト3を確実的に露光できるため、図2(d)に示
すように、未露光部の電着レジスト3がアルカリ水溶液
等の現像液で溶解除去され、未露光部に導電層2が露出
し、露光部の電着レジスト3がレジスト3aとして導電
層2を覆った状態になる。すなわち、立体成形品1から
なる絶縁基板の三次元の表面で、垂直な壁面1sでレジ
スト不要部にはレジスト3aを形成せず、かつ、レジス
ト必要部にはレジスト3aを形成することができる。
Next, on the surface of the three-dimensional molded article 1 on the side of the large opening 7t, a light absorbing plate 8k such as a black rubber plate is provided in place of the exposure flat mask 4, and the small opening is provided. On the surface of the three-dimensional molded article 1 on the 7k side, a light diffuse reflection plate 8h
Instead, an exposure plane mask 4 is provided, and an exposure apparatus such as a scattering exposure machine 6s is used to irradiate scattered light 5s such as ultraviolet rays through the exposure plane mask 4 to reduce the cross-sectional area. The predetermined electrodeposition resist 3 formed on the vertical wall surface 1s of the space 7s and the predetermined electrodeposition resist 3 on the surface of the three-dimensional molded article 1 on the side of the small opening 7k are exposed. In this case, the exposure plane mask 4 is brought into close contact with the substrate to improve the cutability of the exposure on the plane. Although it is difficult to expose the predetermined electrodeposition resist 3 on the substantially vertical wall surface 1s with the parallel light 5h,
By using the scattered light 5s, exposure can be easily performed. Furthermore, when irradiating scattered light 5s such as ultraviolet rays using an exposure device such as a scattering exposure device 6s, a light absorbing plate 8k is provided on the surface of the three-dimensional molded article 1 on the side of the large opening 7t, Since the exposure flat mask 4 is arranged on the surface of the three-dimensional molded article 1 on the side of the small opening 7k, the scattered light 5s irradiated is absorbed by the light absorbing plate 8k to form a space 7a having a large cross-sectional area. The vertical wall surface 1s is prevented from being irradiated with the scattered light 5s. That is, the space 7 having a small cross-sectional area
The scattered light 5s that has entered from s is absorbed, and it becomes difficult to expose the electrodeposition resist 3 that does not need to be exposed on the vertical wall surface 1s that forms the space 7a having a large cross-sectional area, so that the desired exposure can be performed. That is, since the predetermined electrodeposition resist 3 formed on the vertical wall surface 1s can be reliably exposed, as shown in FIG. 2D, the unexposed portion of the electrodeposition resist 3 is exposed to a developing solution such as an alkaline aqueous solution. It is dissolved and removed, and the conductive layer 2 is exposed in the unexposed portion, and the electrodeposited resist 3 in the exposed portion covers the conductive layer 2 as the resist 3a. That is, on the three-dimensional surface of the insulating substrate made of the three-dimensional molded product 1, the resist 3a can be formed in the resist-needed portion without forming the resist 3a in the resist-unnecessary portion with the vertical wall surface 1s.

【0019】もちろん、露光の順序を入れ換えて、図2
(c)に示すように、露光用平面マスク4を介して散乱
光5sで露光を行った後に、図2(b)に示すように、
平行光5hで露光を行ってもよい。この露出した導電層
2を現像により、例えば、塩化第二銅溶液等のエッチン
グ液で化学的に溶解する。エッチングが完了した後は、
使用したレジスト3aを塩化メチレン等の剥離液で剥離
を行うと、図2(e)に示すように、導電層2にプリン
ト配線回路2pが形成される。すなわち、光硬化型の電
着レジスト3を用いた場合には、露光部にプリント配線
回路2pが形成され、光溶解型の電着レジスト3を用い
た場合には、逆に未露光部にプリント配線回路2pが形
成されることになる。以上のようにして、貫通孔7が段
部を有し、1つの貫通孔7が複数の略垂直な壁面1sを
有する場合であっても、これらの略垂直な壁面1sの中
で所定の略垂直な壁面1sを選択的に露光することがで
きる。
Of course, by changing the order of exposure, as shown in FIG.
As shown in FIG. 2C, after the exposure with the scattered light 5 s through the exposure plane mask 4, as shown in FIG.
The parallel light 5h may be used for the exposure. The exposed conductive layer 2 is chemically dissolved by an etching solution such as a cupric chloride solution by development. After etching is complete,
When the used resist 3a is stripped with a stripping solution such as methylene chloride, a printed wiring circuit 2p is formed on the conductive layer 2 as shown in FIG. 2 (e). That is, when the photo-curing type electrodeposition resist 3 is used, the printed wiring circuit 2p is formed in the exposed portion, and when the photo-melting type electrodeposition resist 3 is used, the unexposed portion is printed. The wiring circuit 2p is formed. As described above, even when the through-hole 7 has a step and one through-hole 7 has a plurality of substantially vertical wall surfaces 1s, a predetermined approximate wall surface of the substantially vertical wall surfaces 1s is used. The vertical wall surface 1s can be selectively exposed.

【0020】以上により、本発明の請求項1及び請求項
2に係るプリント配線板の製造方法によると、垂直な壁
面1sに代えて斜面にする必要がなく、小型化及び高機
能化したプリント配線板が得られる。さらに、立体成形
品1に配設された露光部4aと未露光部4bとを備えた
露光用平面マスク4を介して、平行光5hを照射して電
着レジスト3を露光する平行光露光工程と、露光用平面
マスク4を介して、散乱光5sを照射して露光用平面マ
スク4に対して略垂直な壁面1sに形成された電着レジ
スト3を露光する散乱光露光工程とを有するので、複雑
な形状の立体マスクが不要である。かつ露光用平面マス
クの変更だけで容易に回路パターンを変更することがで
き、より複雑な基板にも露光の組み合わせ条件によって
柔軟に対応できるので、回路設計の自由度が増す。
As described above, according to the method for manufacturing a printed wiring board according to the first and second aspects of the present invention, it is not necessary to form the inclined surface in place of the vertical wall surface 1s, and the downsized and highly functional printed wiring board is provided. A board is obtained. Further, a parallel light exposure step of irradiating the electrodeposition resist 3 by irradiating the parallel light 5h through the exposure flat mask 4 having the exposed portion 4a and the unexposed portion 4b arranged in the three-dimensional molded article 1. And a scattered light exposure step of irradiating scattered light 5s through the exposure flat mask 4 to expose the electrodeposition resist 3 formed on the wall surface 1s substantially perpendicular to the exposure flat mask 4. No need for a complicated three-dimensional mask. Moreover, the circuit pattern can be easily changed only by changing the plane mask for exposure, and more complicated substrates can be flexibly dealt with according to the combination conditions of exposure, so that the degree of freedom in circuit design is increased.

【0021】[0021]

【発明の効果】本発明の請求項1に係るプリント配線板
の製造方法によると、立体成形品に配設された露光用平
面マスクに対して略垂直な壁面が複数ある場合に、これ
らの略垂直な壁面の中から選択的に、所定の略垂直な壁
面に形成された電着レジスト3を、露光用平面マスクを
介して散乱光を照射して露光する散乱光露光工程で露光
するので、所定の垂直な壁面1sに形成された電着レジ
スト3を確実に露光できるため、垂直な壁面に代えて斜
面にする必要がなく、小型化及び高機能化したプリント
配線板が得られる。さらに、複雑な形状の立体マスクが
不要であり、露光用平面マスクの変更だけで容易に回路
パターンを変更することができ、より複雑な基板にも露
光の組み合わせ条件によって柔軟に対応できるので、回
路設計の自由度が増す。
According to the method of manufacturing a printed wiring board according to the first aspect of the present invention, when there are a plurality of wall surfaces that are substantially perpendicular to the exposure flat mask provided on the three-dimensional molded product, these Since the electrodeposition resist 3 formed on the predetermined substantially vertical wall surface is selectively exposed from the vertical wall surface in the scattered light exposure step of irradiating and exposing the scattered light through the exposure plane mask, Since the electrodeposition resist 3 formed on the predetermined vertical wall surface 1s can be surely exposed, it is not necessary to use an inclined surface in place of the vertical wall surface, and a downsized and highly functional printed wiring board can be obtained. In addition, a 3D mask with a complicated shape is not required, and the circuit pattern can be easily changed simply by changing the exposure plane mask, and it is possible to flexibly respond to more complicated substrates depending on the exposure combination conditions. The degree of freedom in design increases.

【0022】本発明の請求項2に係るプリント配線板の
製造方法によると、平行光が光乱反射板に当たって乱反
射することによって散乱光となるので、この乱反射した
散乱光によって、露光用平面マスクに対して垂直な壁面
に形成された電着レジストが露光されるため、所定の略
垂直な壁面に形成された電着レジストへの露光をさらに
確実にする。しかも、照射された散乱光が光吸収板で吸
収され、露光不要の垂直な壁面等の面に、散乱光が照射
されるのを防止するので、露光不要の垂直な壁面等の面
に形成された電着レジストが露光され難いため、プリン
ト配線回路の精度がさらに向上する。すなわち、貫通孔
が段部を有し、1つの貫通孔が複数の略垂直な壁面を有
する場合であっても、これらの略垂直な壁面の中で所定
の略垂直な壁面を選択的に露光することができる。
According to the method for manufacturing a printed wiring board according to the second aspect of the present invention, since the parallel light hits the diffuse reflection plate and is diffusely reflected to become scattered light, the diffused scattered light causes the flat mask for exposure to be exposed. Since the electrodeposition resist formed on the vertical wall surface is exposed, the exposure to the electrodeposition resist formed on the predetermined substantially vertical wall surface is further ensured. Moreover, the scattered light that has been irradiated is absorbed by the light absorbing plate and is prevented from irradiating the scattered light onto the vertical wall surface that does not require exposure, so that it is formed on the vertical wall surface that does not require exposure. Since the electrodeposited resist is hard to be exposed, the accuracy of the printed wiring circuit is further improved. That is, even when the through hole has a step portion and one through hole has a plurality of substantially vertical wall surfaces, a predetermined substantially vertical wall surface is selectively exposed among these substantially vertical wall surfaces. can do.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係るプリント配線板の製造方法の第1
実施例を示す断面図である。
FIG. 1 is a first method of manufacturing a printed wiring board according to the present invention.
It is sectional drawing which shows an Example.

【図2】本発明に係るプリント配線板の製造方法の第2
実施例を示す断面図である。
FIG. 2 is a second method of manufacturing a printed wiring board according to the present invention.
It is sectional drawing which shows an Example.

【図3】従来例に係るプリント配線板の製造方法の断面
図である。
FIG. 3 is a cross-sectional view of a method for manufacturing a printed wiring board according to a conventional example.

【図4】従来例に係るプリント配線板の製造方法でポジ
型の電着レジストを使用した場合の断面図である。
FIG. 4 is a cross-sectional view when a positive electrodeposition resist is used in a method for manufacturing a printed wiring board according to a conventional example.

【図5】従来例に係るプリント配線板の製造方法でネガ
型の電着レジストを使用した場合の断面図である。
FIG. 5 is a cross-sectional view when a negative electrodeposition resist is used in a method for manufacturing a printed wiring board according to a conventional example.

【符号の説明】[Explanation of symbols]

1 立体成形品 2 導電層 2p プリント配線回路 3 電着レジスト 3a レジスト 4 露光用平面マスク 4a 露光部 4b 未露光部 5h 平行光 5s 散乱光 7 貫通孔 7k 小さい開口部 7t 大きい開口部 8h 光乱反射板 8k 光吸収板 DESCRIPTION OF SYMBOLS 1 Three-dimensional molded article 2 Conductive layer 2p Printed wiring circuit 3 Electrodeposition resist 3a Resist 4 Exposure plane mask 4a Exposed part 4b Unexposed part 5h Parallel light 5s Scattered light 7 Through hole 7k Small opening 7t Large opening 8h Light diffuse reflection plate 8k light absorption plate

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 絶縁性を有する立体成形品(1)の表面
に、導電層(2)を形成し、この導電層(2)に感光性
を有する電着レジスト(3)を形成するとともに、露光
用平面マスク(4)を介して光を照射し、電着レジスト
(3)を露光、現像してレジスト(3a)を形成するこ
とによりプリント配線回路(2p)を形成する貫通孔
(7)を備え、露光用平面マスク(4)に対して複数の
略垂直な壁面(1s)を有するプリント配線板の製造方
法において、立体成形品(1)に配設された露光部(4
a)と未露光部(4b)とを備えた露光用平面マスク
(4)を介して、平行光(5h)を照射して所定の電着
レジスト(3)を露光する平行光露光工程と、露光用平
面マスク(4)を介して、散乱光(5s)を照射して露
光用平面マスク(4)に対して所定の略垂直な壁面(1
s)に形成された電着レジスト(3)を露光する散乱光
露光工程とを有することを特徴とするプリント配線板の
製造方法。
1. A conductive layer (2) is formed on the surface of an insulating three-dimensional molded article (1), and a photosensitive electrodeposition resist (3) is formed on the conductive layer (2). Through holes (7) for forming a printed wiring circuit (2p) by irradiating light through an exposure plane mask (4) to expose and develop an electrodeposition resist (3) to form a resist (3a). In the method for manufacturing a printed wiring board having a plurality of substantially perpendicular wall surfaces (1s) with respect to the exposure flat mask (4), the exposure unit (4) provided on the three-dimensional molded product (1).
a parallel light exposure step of irradiating parallel light (5h) to expose a predetermined electrodeposition resist (3) through an exposure flat mask (4) including a) and an unexposed portion (4b); The scattered light (5 s) is irradiated through the exposure plane mask (4) and a predetermined substantially vertical wall surface (1) with respect to the exposure plane mask (4).
and a scattered light exposure step of exposing the electrodeposition resist (3) formed in s) to a method for producing a printed wiring board.
【請求項2】 前記貫通孔(7)が段部を有し、貫通孔
(7)の小さい開口部(7k)側の立体成形品(1)の
表面に光乱反射板(8h)を配設して小さい開口部(7
k)を覆い、貫通孔(7)の大きい開口部(7t)側の
立体成形品(1)の表面に露光用平面マスク(4)を配
設し、この露光用平面マスク(4)を介して平行光(5
h)を照射して所定の電着レジスト(3)を露光する平
行光露光工程と、前記大きい開口部(7t)側の立体成
形品(1)の表面に光吸収板(8k)を配設して大きい
開口部(7t)を覆い、前記小さい開口部(7k)側の
立体成形品(1)の表面に露光用平面マスク(4)を配
設し、この露光用平面マスク(4)を介して散乱光(5
s)を照射して所定の電着レジスト(3)を露光する散
乱光露光工程とを有することを特徴とする請求項1記載
のプリント配線板の製造方法。
2. The through hole (7) has a step, and a diffused reflection plate (8h) is arranged on the surface of the three-dimensional molded product (1) on the side of the opening (7k) where the through hole (7) is small. And a small opening (7
k), and a plane mask for exposure (4) is arranged on the surface of the three-dimensional molded article (1) on the side of the opening (7t) having a large through hole (7). Parallel light (5
parallel light exposure step of irradiating a predetermined electrodeposition resist (3) by irradiating h), and disposing a light absorbing plate (8k) on the surface of the three-dimensional molded product (1) on the side of the large opening (7t). To cover the large opening (7t), and dispose the exposure flat mask (4) on the surface of the three-dimensional molded product (1) on the side of the small opening (7k). Scattered light (5
The method for producing a printed wiring board according to claim 1, further comprising: a scattered light exposure step of irradiating a predetermined electrodeposition resist (3) by irradiating s).
JP01358995A 1995-01-31 1995-01-31 Manufacturing method of printed wiring board Expired - Fee Related JP3538937B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP01358995A JP3538937B2 (en) 1995-01-31 1995-01-31 Manufacturing method of printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP01358995A JP3538937B2 (en) 1995-01-31 1995-01-31 Manufacturing method of printed wiring board

Publications (2)

Publication Number Publication Date
JPH08204311A true JPH08204311A (en) 1996-08-09
JP3538937B2 JP3538937B2 (en) 2004-06-14

Family

ID=11837388

Family Applications (1)

Application Number Title Priority Date Filing Date
JP01358995A Expired - Fee Related JP3538937B2 (en) 1995-01-31 1995-01-31 Manufacturing method of printed wiring board

Country Status (1)

Country Link
JP (1) JP3538937B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113473746A (en) * 2021-05-21 2021-10-01 广州美维电子有限公司 Method for preventing resistance welding oil dropping of calendered copper

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113473746A (en) * 2021-05-21 2021-10-01 广州美维电子有限公司 Method for preventing resistance welding oil dropping of calendered copper

Also Published As

Publication number Publication date
JP3538937B2 (en) 2004-06-14

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