JPH08203833A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE: To form a single-crystal layer having no facet self-alignedly in an opening of an insulating film. CONSTITUTION: An insulating film 2 is formed on a substrate 1 and then an opening 3 is made (a). Material gas excluding etching gas is so supplied that there may be a region L where no polycrystalline particles 5 are deposited. At that time, a single-crystal layer 4 is formed by an epitaxial growth method with a growth temperature being raised and growth pressure being lowered (b). A resist film 7 is so formed as to cover the single-crystal layer 4 and a part of the undeposited region L. With the resist being used as a film, the polycrystalline particles are removed (c). Finally, the resist is removed (d). By this method, the polycrystalline particles are not left over on the insulating film formed just under the resist even if the polycrystalline particles are removed by etching with the resist being used as a mask since there is the region L where no polycrystalline particles are deposited.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a facet-free single crystal growth layer formed by epitaxial growth of silicon or silicon-germanium in an opening of an insulating film provided on a single crystal substrate. The present invention relates to a method for manufacturing a semiconductor device to be formed.

[0002]

2. Description of the Related Art In recent years, a transistor using a silicon epitaxial layer or a silicon-germanium epitaxial layer as a base has been researched and developed in response to a demand for higher speed devices. For example, the 1993 IEDM Technical Digest (1993 IEDM
There are devices described on pages 83 to 86 of Technical Digest). This high-speed device shows a structure in which the epitaxial base layer extends not only on the single crystal layer of the opening surrounded by the element isolation insulating film but also on the insulating film. Such an epitaxial base layer can be obtained by performing non-selective epitaxial growth.

Conventionally, as a method for forming a single crystal silicon or silicon-germanium layer in an opening of an insulating film by using this kind of non-selective epitaxial growth, a method as shown in FIG. 3 has been known. 3 (a) to (d)
The cross-sectional views shown in are schematic views showing an example of a conventional manufacturing method for forming an epitaxial growth layer in the opening of the insulating film in process order.

In FIG. 3A, reference numeral 1 indicates a silicon substrate, and an insulating film 2 formed on the silicon substrate 1 is partially etched and removed to form an opening 3.
Then, as shown in (b), a silicon-based or germane-based gas is caused to flow in a state where the silicon substrate 1 is heated to allow non-selective epitaxial growth of silicon, and a single crystal silicon or a single crystal silicon-germanium layer is formed in the opening 3. Simultaneously with the growth of 4, the polycrystalline silicon or polycrystalline silicon-germanium layer 10 is deposited on the insulating film 2. In addition, when the silicon-based and germane-based gas is supplied to deposit the single crystal silicon / germanium layer 4 and the polycrystalline silicon / germanium layer 10, and when the silicon-based gas is supplied to supply the single crystal silicon layer 4 and the polycrystalline silicon layer. Since the same applies to the case where 10 is deposited, only the case where a silicon-based gas is supplied will be described below. Furthermore, (c)
In order to leave the single crystal silicon layer 4 in the opening 3 as shown in FIG. 3, after the non-selective epitaxial growth, the opening 3 is masked by using a well-known photolithography technique.
The resist 7 is left so as to cover the. Finally, as shown in (d), the polycrystalline silicon layer 10 on the insulating film 2 is removed by etching using the resist 7 as a mask to remove the resist. At this time, a part of the polycrystalline silicon layer 10 remains under the resist 7.

If only the single crystal epitaxial base layer can be formed in the high speed device as described above, that is, if the single crystal can be selectively epitaxially grown only in the opening of the insulating film, it is caused by the polycrystalline layer which does not work as the base active region. Unnecessary parasitic capacitance can be reduced, and unnecessary polycrystals can be miniaturized, so that further improvement in device performance can be expected. For the method of performing selective epitaxial growth only on the opening of such an insulating film, see, for example, Semiconductor Research Vol. 21, Chapter 6, "Selective Epitaxial Growth-Element Separation", pages 127 to 155 (published by the Industrial Research Board in 1985). Are described in. Here, FIG. 4 shows a sectional view of the selective epitaxial growth process. The same applies to the case of using a silicon-based gas and germane-based gas, so the case of using a silicon-based gas will be described below.

FIG. 4A is a sectional view showing a state in which the insulating film 2 formed on the silicon substrate 1 is partially removed by etching to form the opening 3. By using silicon chloride as a raw material gas in a state where the silicon substrate 1 is heated, or by performing an epitaxial growth by flowing an etching gas such as a chlorinated gas in addition to the silicon-based raw material gas, the etching reaction is performed simultaneously with the epitaxial growth. Therefore, as shown in FIG. 4B, single crystal silicon epitaxial growth layer 4 is formed only in opening 3 without depositing polycrystalline silicon on insulating film 2, and selective epitaxial growth is performed.

[0007]

However, according to the former method using non-selective epitaxial growth described above, the single crystal silicon layer 4 grows in the opening 3 of the insulating film as shown in FIG. At the same time, the polycrystalline silicon layer 10 grows on the insulating film 2. Therefore, the polycrystalline silicon layer 10 needs to be removed by etching using mask alignment, and as a result, the polycrystalline silicon layer 10 remains under the resist 7, which causes a problem that the parasitic capacitance of the device increases. In addition, since mask alignment is used, a mask layout that considers mask alignment accuracy must be used, which further increases the parasitic capacitance of the device, lowers the operating speed, and increases power consumption due to charging and discharging of the parasitic capacitance. There are problems such as.

According to the latter method using selective epitaxial growth described above, the etching gas such as chlorinated gas is caused to flow simultaneously with the silicon-based source gas to perform the epitaxial growth. Therefore, the metal pipe portion of the growth apparatus using the etching gas is used. However, there is a problem that corrosion occurs in the metal and causes metal contamination, gas leakage, deterioration of durability of the growth apparatus, and the like. Furthermore, compared to hydrogenated gas, which is a raw material gas for epitaxial growth, chlorinated gas, etc., which is added to give selectivity, has a low vapor pressure, and therefore it is necessary to control the temperature of the gas cylinder and piping, which is not easy to control. is there. In addition, as compared with hydrogenated gas, the etching gas has no advanced purification technology, so the water contained in the gas,
There is a problem that contaminants such as oxygen, carbon, and metals are mixed into the epitaxial growth layer to deteriorate the crystallinity of the epitaxial layer. Further, as shown in FIG. 4B, facets 11 are generated at the boundary between the silicon substrate 1 and the insulating film 2 in the single crystal silicon layer 4 after epitaxial growth. When a substrate having a crystal orientation (100) plane is used as a single crystal substrate, selective epitaxial growth is performed (311).
It is known that facets of (111) plane and (111) plane are generated, and there is a problem that these facets deteriorate the characteristics of the semiconductor device.

Therefore, an object of the present invention is to provide a single crystal in which facets are not self-aligned in the openings of the insulating film even when a silicon-based or germane-based source gas containing no etching gas is supplied for epitaxial growth. It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of forming a layer.

[0010]

The object of the present invention is to form an insulating film on a single crystal substrate, to form an opening in the insulating film, and to supply a source gas containing no etching gas. Forming a single crystal layer in the opening by epitaxial growth, and forming a resist by mask alignment so as to cover the single crystal layer in the opening and the insulating film within the polycrystalline grain deposition start distance around the opening And a step of etching away the polycrystalline grains formed on the insulating film at the time of epitaxial growth using the resist as a mask. That is, even if epitaxial growth is performed using a silicon-based or germane-based source gas containing no etching gas in the opening of the insulating film formed on the silicon substrate, the insulating film is located at a position apart from the opening by a certain distance. By utilizing the deposition of polycrystalline silicon or polycrystalline silicon-germanium from the above, and by using a photo process and a processing process that have a mask alignment accuracy that is less than the polycrystalline grain deposition start distance, it is possible to perform self-alignment at the opening. It forms a crystalline silicon or single crystal silicon-germanium layer.

Further, according to the method of manufacturing a semiconductor device of the present invention, the step of forming an insulating film on a single crystal substrate, the opening of the insulating film and the position where the polycrystalline grain deposition start distance around the opening is not exceeded. And a step of forming a dummy opening in the substrate and a step of supplying a source gas containing no etching gas to form a single crystal layer in the opening and the dummy opening by epitaxial growth. Good. In this case, a step of covering the dummy opening with an insulating film can be added after the epitaxial growth. It is preferable that the single crystal substrate is a silicon substrate and the source gas is any one of a silicon type, a silicon type and a germane type, and a germane type. Further, it is preferable that the epitaxial growth temperature in the epitaxial growth step is in the range of 500 to 850 ° C. Further, in this case, it is desirable that the epitaxial growth pressure in the epitaxial growth step does not exceed 100 Pa. It is preferable that the polycrystalline grain deposition start distance is at least 0.2 μm.

[0012]

According to the method of manufacturing the semiconductor device of the present invention,
After the epitaxial growth is performed by supplying the source gas containing no etching gas, the resist is formed so as to cover the opening of the insulator on the single crystal substrate and the insulating film within the polycrystalline grain deposition start distance around the opening. Then, by using this resist as a mask and etching away the polycrystalline grains formed on the insulating film during epitaxial growth, it is possible to leave a facet-free single crystal layer only in the opening in a self-aligned manner. Since the parasitic capacitance due to the unnecessary polycrystalline layer at the time of doing so can be reduced, it is possible to achieve high speed operation and low power consumption of the device.

Further, after forming an insulating film on the single crystal substrate, an opening and a dummy opening are formed in the insulating film at positions not exceeding the polycrystalline grain deposition start distance around the opening, and etching gas is used. By supplying the source gas containing no gas, only the single crystal layer can be epitaxially grown in the opening and the dummy opening. In this case, by further adding a step of covering the dummy opening with an insulating film after the epitaxial growth, it is possible to prevent an unnecessary impurity layer from being formed in the dummy opening when forming an element in the opening.

Then, a silicon substrate is used as the single crystal substrate, and a silicon-based material, a silicon-based material and a germane-based material, or a germane-based material is used as a source gas, whereby a single crystal silicon layer or a single crystal silicon / germanium is formed in the opening. Layers can be formed.

Further, if the epitaxial growth temperature in the epitaxial growth step is in the range of 500 to 850 ° C. or the epitaxial growth pressure does not exceed 100 Pa, the polycrystalline grain deposition start distance from the opening is in a practical range of 0.2 μm or more. Can be within

[0016]

Embodiments of the method of manufacturing a semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings.

<Embodiment 1> FIG. 1 is a sectional view showing an embodiment of a method of manufacturing a semiconductor device according to the present invention. In addition,
The same components as those shown in the conventional example of FIG. 3 will be described with the same reference numerals. In FIG. 1A, an insulating film 2 made of SiO ₂ , Si ₃ N ₄ or the like is formed on a silicon substrate 1, and the insulating film 2 is partially removed by etching using a mask by a well-known photolithography technique to form an opening. Form part 3. Next, when the silicon substrate 1 is heated and epitaxial growth is performed in a state in which a silicon-based gas as a raw material gas is allowed to flow without being mixed with an etching gas such as a chlorinated gas, an opening 3 is formed as shown in FIG. A monocrystalline silicon layer 4 grows on the insulating film 2, and an island 5 of polycrystalline silicon (hereinafter, referred to as polycrystalline particles of silicon) 5 is deposited on the insulating film 2, but in a range of a length L from the opening 3. Has a non-deposited region 6 where the polycrystalline silicon particles 5 are not deposited.

The state of the opening 3 and the peripheral shape of the opening of the insulating film 2 after the epitaxial growth will be described with reference to the perspective views of FIGS. 5 and 6. By lowering the growth pressure of the epitaxial growth, as shown in FIG. 6, since the silicon molecules (or silicon atoms) 12 on the surface of the insulating film 2 easily move, the silicon molecules 12 in the vicinity of the opening 3 will not move to the opening 3. Single crystal silicon substrate 1
The single crystal silicon 4 grows on the upper surface, and when the number of silicon molecules 12 on the insulating film 2 exceeds a certain critical point, the polycrystalline silicon starts to be deposited, so that the polycrystalline particles 5 of silicon are formed. On the other hand, on the insulating film 2 around the opening 3, the silicon molecules 12 are reduced by the amount of flowing into the opening 3, and the number of the silicon molecules 12 does not reach the critical point. Non-deposited areas appear. For example, the silicon epitaxial growth layer 4 may be formed into 100% by using only Si ₂ H ₆ gas without flowing etching gas.
FIG. 8 shows the growth temperature dependence of the length L of the non-deposition region 6 (that is, the polycrystalline grain deposition start distance) when grown to a thickness of nm, and FIG. 8 shows the growth pressure dependence of the length L of the non-deposition region 6. Shown in. The movement of silicon molecules on the insulating film increases as the growth temperature becomes higher and the growth pressure becomes lower.
As can be seen from the above, as the growth temperature becomes higher and the growth pressure becomes lower, the length L of the non-deposition region also becomes larger. Note that this relationship is the same not only when only a silicon-based gas is flown, but also when a silicon-based gas and a germane-based gas are flowed.

For example, if the growth pressure is 50 Pa as shown in FIG. 7 and the growth temperature is 780 ° C. or higher, or if the growth temperature is 750 ° C. as shown in FIG. An epitaxial growth layer 4 made of single-crystal silicon or single-crystal silicon-germanium grows, and polycrystalline grains 5 of silicon or silicon-germanium are deposited on the insulating film 2 at a position separated by 0.6 μm or more from the opening 3. By lowering the growth pressure, the growth temperature can be lowered while maintaining the value of L, and the substrate 1 and the epitaxial growth layer 4 can be formed.
It is possible to suppress the diffusion of impurities contained in and to form a shallow junction, which is effective for increasing the speed of the device.

Si as a source gas for epitaxial growth
_{When 2} H ₆ is ₂ SCCM, GeH ₄ is 0.5 SCCM and the growth temperature is 750 ° C. and the growth pressure is 5 Pa, the insulating film is about 1.5 μm away from the end of the opening 3. 2 polycrystalline grains 5 of the silicon-germanium is deposited on the facet-free monocrystalline Si _0.8 Ge _0.2 layers as shown in FIG. 1 (b) composition ratio of 20% Ge in the opening 3 of the insulating film 4 grows.

Next, as shown in FIG. 1C, a resist 7 is formed using mask alignment. Here, when the overlapping width of the mask for removing the unnecessary polycrystalline grains 5 and the opening 3 is a, and the alignment accuracy of the mask is b,
If epitaxial growth conditions satisfying the condition of L> (a + b) are used, the single crystal silicon or the single crystal silicon-germanium layer 4 can be formed in the opening only in a self-aligned manner. For example, the overlap width a of the resist 7 and the opening 3 for removing the unnecessary silicon or silicon-germanium polycrystalline grains 5 on the insulating film 2
Is 0.4 μm and the mask alignment accuracy b is 0.2 μm
Then, the condition for the length L of the non-deposition region 6 is L>
It becomes 0.6 μm. Then, the polycrystalline grains 5 on the insulating film 2 are removed by etching, so that only the epitaxial growth layer 4 in the opening 3 remains as shown in FIG.

As described above, when it is intended to form the epitaxial base layer to have a thickness of 20 to 30 nm, at least about 100 nm, by performing the epitaxial growth by the method of supplying only the source gas without the etching gas and heating the substrate. The epitaxial growth temperature needs to be 500 ° C. or higher. Considering crystallinity, 550 ° C. or higher is preferable. On the other hand, if the temperature exceeds 850 ° C., the base thickness of 20 to 30 nm cannot be substantially secured due to diffusion into the underlying single crystal layer, that is, the collector layer. Further, considering that the above-mentioned overlap width a and mask alignment accuracy b can technically be about 0.1 μm, the growth pressure during epitaxial growth is the length of the non-deposition region, that is, the polycrystalline grain. The growth pressure at which the deposition start distance L can satisfy L> 0.2 μm is 100 Pa at the growth temperature of 550 ° C., and may exceed 1000 Pa at 850 ° C.

As shown in the present embodiment, since facet-free single crystal silicon or single crystal silicon-germanium can be formed only in the opening, if this is applied to an epitaxial-based device, the device capacitance is reduced. At the same time, deterioration of device characteristics can be prevented.

<Embodiment 2> FIG. 2 is a sectional view showing another embodiment of the method for manufacturing a semiconductor device according to the present invention. The same components as those shown in the embodiment of FIG. 1 will be described with the same reference numerals. Figure 2
As shown in (a), SiO ₂ , S on the silicon substrate 1
An insulating film 2 such as i ₃ N ₄ is formed, and the insulating film 2 is formed using a mask.
Is partially removed by etching to form a dummy opening 8 at the same time as the opening 3. At this time, the opening 3
And the dummy opening 8 are separated from each other by a polycrystalline grain deposition start distance L
Shorter interval than. That is, the opening 3 is patterned so as to be surrounded by an insulating film having a width shorter than the polycrystalline grain deposition start distance L.

In FIG. 2B, under the epitaxial growth condition that the length L of the polycrystalline non-deposition region 6, that is, the polycrystalline grain deposition start distance L is larger than the distance between the opening 3 and the dummy opening 8. A single crystal silicon or single crystal silicon-germanium layer 4 is formed. For example, the gap between the opening 3 and the dummy opening 8 is 1.0 μm, and ₂ SCCM of Si ₂ H ₆ and 0.5 SC of GeH ₄ are used as source gases.
The growth temperature is set to 75 by flowing without including CM and etching gas.
When epitaxial growth is performed under the conditions of 0 ° C. and a growth pressure of 5 Pa, L becomes about 1.5 μm as shown in FIG. 8, so that polycrystalline silicon / germanium grains are not deposited on the insulating film 2. In addition, single crystal Si _0.8 G having a Ge composition ratio of 20% is present only in the openings 3 of the insulating film and the openings 8 of the dummy.
e _0.2 Layer 4 grows.

Next, as shown in FIG. 2C, an insulating film 9 is formed on the dummy opening 8 to fill the dummy opening 8.
To form. In this case, the insulating film 9 made of SiO ₂ or the like
After depositing by the VD method, photoetching may be performed.

As described above, according to the present embodiment, the dummy opening is provided in the insulating film, so that the polycrystalline grains formed on the insulating film by mask alignment as in the first embodiment are not removed. The single crystal layer can be formed in the opening in a self-aligning manner. Therefore, a facet-free single crystal layer can be formed only in the opening without considering the alignment accuracy of the mask for removing unnecessary polycrystalline grains. The capacity of the device can be reduced by the process, and the deterioration of the device characteristics can be prevented.

<Embodiment 3> FIG. 9 is a sectional view showing still another embodiment of the method for manufacturing a semiconductor device according to the present invention.
In this embodiment, the method for manufacturing a semiconductor device of the present invention is applied to a bipolar transistor to form an epitaxial base layer in a self-aligned manner.

In FIG. 9A, reference numeral 21 indicates a p-type silicon substrate, and an n-type impurity is introduced into this silicon substrate 21 by ion implantation or diffusion to form a buried layer 22, and then n-type is formed by epitaxial growth. The low concentration collector layer 23 is formed. Then, the collector / base isolation insulating film 24, the base extraction polycrystalline silicon layer 25, and the first emitter / base isolation insulating film 26.
After sequentially forming the three-layer structure, the opening 27 reaching the n-type collector layer 23 is formed.

Next, the p-type epitaxial base layer 28 is formed.
Are formed in the opening 27. For example, as a source gas, Si
The ₂ H ₆ 2SCCM, 0.5SCCM the GeH _4, a B ₂ H ₆ of 60PpmH ₂ diluted for doping 50SCC
M, flow without etching gas, growth temperature 750
By performing the epitaxial growth at a temperature of 5 ° C. and a growth pressure of 5 Pa, the polycrystalline silicon / germanium grains 30 are deposited from a position separated by the polycrystalline grain deposition start distance L. That is, on the insulating film 26, as shown in FIG.
Polycrystalline grains 30 of silicon-germanium are deposited at a distance of about 1.5 μm from the end of 7. On the other hand, the opening 2
7 is a p-type single crystal Si _0.8 Ge _0.2 layer 2 having a Ge composition ratio of 20% and a carrier concentration of 2 × 10 ¹⁸ / cm ^{3 as} a base layer.
8 grows. Further, since the polycrystalline silicon-germanium layer 29 serving as a connecting base grows on the polycrystalline silicon layer 25 for drawing out the base at the same time as the epitaxial growth in the opening 27, as shown in FIG. 9B, the single crystal serving as the intrinsic base is formed. The Si _0.8 Ge _0.2 layer 28 and the base extraction polycrystalline silicon 25 are connected via the polycrystalline silicon-germanium layer 29.

Next, as shown in FIG. 9C, a resist 31 is left in the polycrystalline grain deposition start distance L so as to cover the opening by a photo process. By protecting the opening 27 with this resist 31 and etching away the polycrystalline silicon-germanium grains 30 deposited on the insulating film 26,
Only the intrinsic base 28 and the tethered base 29 can be formed.

After that, as shown in FIG. 9D, an insulating film 32 for separating the connecting base 29 and the emitter is formed. This is because after the insulating film 32 is deposited by the CVD method,
The anisotropic dry etching can be formed by utilizing the fact that the insulating film 32 remains only on the side wall of the opening.
Next, as shown in FIG. 9E, an npn transistor can be formed by depositing high-concentration polycrystalline silicon 33 doped with n-type impurities and performing photoetching to form an emitter.

As described above, according to the present embodiment, only the intrinsic base 28 and the connecting base 29 can be formed in the opening 27 without unnecessary polycrystal layer remaining on the insulating film, so that the capacitance of the transistor is increased. Can be reduced. Furthermore, since facets are not generated in the intrinsic base 28 as in the case of using the conventional selective epitaxial method, the resistance between the intrinsic base 28 and the connecting base 29 can be reduced.
In addition, the intrinsic base 28 of the bipolar transistor is made of Si.
Introducing a hetero interface as -Ge also has the advantage of increasing the current amplification factor. Although the npn transistor is formed using the p-type silicon substrate in the present embodiment, the pnp transistor is also formed by using the n-type silicon substrate and reversing the conductivity types of the other layers. Of course, you can do that. Needless to say, the source gas for growing the epitaxial base layer may be silicon-based and the single crystal silicon layer may be the base layer.

<Embodiment 4> FIG. 10 is a sectional view showing still another embodiment of the semiconductor device according to the present invention. The present embodiment is a case where the method for manufacturing a semiconductor device described in the first embodiment is used to form a single crystal layer in a self-aligned manner, and is applied to element isolation of a device. In FIG. 10A, reference numeral 41 represents a p-type silicon substrate, and an insulating film 42 for element isolation such as SiO ₂ , Si ₃ N ₄ or the like is formed on the silicon substrate 41, and an opening portion is formed by well-known photo etching. Four
3 is formed.

Next, as shown in FIG. 10B, epitaxial growth is performed in the opening 43 to form a single crystal region 44. Here, the epitaxial growth conditions are, for example, ₂ SCCM of Si ₂ H ₆ as a raw material gas for epitaxial growth.
At the same time, a doping gas containing p-type impurities is allowed to flow without an etching gas, the growth temperature is 750 ° C., and the growth pressure is 5 Pa.
μm (that is, polycrystalline grain deposition start distance L≈1.5 μ
m) Silicon polycrystalline grains 45 are deposited on the insulating film 42 from a distance, while a p-type single crystal silicon layer 44 is grown in the opening 43 of the insulating film.

Further, as shown in FIG. 10C, the resist 46 is left within the polycrystalline grain deposition start distance L so as to cover the single crystal silicon layer 44 by a photo process, and the single crystal region 44 is left.
After the protection, the polycrystalline silicon particles 45 of silicon deposited on the insulating film 42 are removed by etching.

Next, as shown in FIG. 10D, after the surface of the single crystal silicon layer 44 is covered with a thin oxide film 47 so as not to be damaged by the next ion implantation, as shown in FIG. As shown by the arrow, with the insulating film 48 as a mask, an impurity which becomes an n-type is introduced into one island of single crystal silicon by ion implantation. Finally, as shown in FIG. 10E, by removing the insulating film 48 and the oxide film 47, the conductivity of the islands 49 of single crystal silicon in the p-type region and the islands 50 of single crystal silicon in the n-type region is reduced. Regions of different sex are formed.

As described above, according to this embodiment, the conventional L
As compared with the case of OCOS (Local Oxidation of Silicon) oxidation, element isolation without so-called bird's beak can be performed, so element isolation separating single crystal regions having different conductivity can be reduced, and islands of this single crystal region can be reduced. By forming the transistor, high integration of the circuit can be achieved. Further, since no stress such as element isolation due to the conventional LOCOS oxide film is generated between the element isolation insulating film and the single crystal region which is the device region, deterioration of the characteristics of the device formed in the single crystal region can be prevented. .

An n-type silicon substrate is used as the substrate 41, an n-type epitaxial layer is formed in place of the p-type epitaxial layer 44, and single crystal regions 49 and 50 of different conductivity types are formed by p-type ion implantation. Alternatively, the silicon-germanium single crystal layer 44 may be formed by flowing a silicon-based gas and a germane-based gas as a source gas during the epitaxial growth. Of course, a resist can be used instead of the insulating film 48 as a mask for ion implantation.

<Embodiment 5> FIG. 11 is a sectional view showing another embodiment of the method for manufacturing a semiconductor device according to the present invention. In this embodiment, a single crystal layer is formed in the opening of an insulating film in a self-aligning manner by using the method for manufacturing a semiconductor device shown in the first embodiment to reduce the resistance of the source / drain of a MOS transistor. That is the case. In FIG. 11A, reference numeral 61 indicates a p-type single crystal silicon substrate, and a well-known LO is formed on the silicon substrate 61 except the opening 63.
An element isolation insulating film 62 is formed by the COS method, and a gate oxide film 64, a gate polycrystalline silicon 65, a gate cap layer 66 of an insulating film, and a gate sidewall insulating film 67 are formed.

Next, as shown in FIG. 11B, before forming the source / drain by ion implantation, the single crystal silicon layer 68 is formed by epitaxial growth only on the exposed portion of the single crystal silicon substrate 61. To form. At this time, the epitaxial growth conditions are, for example, when Si ₂ H ₆ as a raw material gas for epitaxial growth is flowed at ₂ SCCM without etching gas, the growth temperature is 750 ° C., and the growth pressure is 5 Pa, from the end of the element isolation insulating film 62. While the polycrystal grain 69 of silicon is deposited on the insulating film 62 from the position where the polycrystal grain deposition start distance L is about 1.5 μm, the single crystal silicon layer 68 is formed on the exposed single crystal silicon substrate 61. grow up.

Further, as shown in FIG. 11C, a single crystal region 68 is left in the polycrystalline grain deposition start distance L so as to cover the single crystal silicon layer 68 by a photo process, leaving a resist 70.
After the protection, the polycrystalline silicon particles 69 of silicon deposited on the element isolation insulating film 62 are removed by etching.

Finally, as shown in FIG. 11D, after an n-type source 71 and an n-type drain 72 are formed by, for example, ion implantation, a refractory metal 73 such as titanium or tungsten is formed into a single crystal silicon layer. Selectively grow on 68,
The metal silicide layer 74 is formed by reacting with the single crystal silicon layer 68. This reduces the contact resistance between the source 71 and the drain 72.

As described above, according to the present embodiment, since the single crystal silicon layer 68 for reducing the resistance can be formed only on the source / drain, the single crystal silicon to be the source / drain regions by the silicide reaction. The reduction of the layer 61 can be prevented. Therefore, the source / drain regions can be downsized, and the capacitance can be reduced. Further, since the facet-free single crystal silicon layer 68 can be formed, impurities can be uniformly introduced when forming the source / drain, which is effective in improving the device capacity and performance. It is needless to say that the present invention can be applied to a case where an n-type silicon substrate is used instead of the p-type silicon substrate 61 and a p-channel MOS transistor is formed as p-type source / drain instead of n-type source / drain.

<Embodiment 6> FIG. 12 is a sectional view showing still another embodiment of the method for manufacturing a semiconductor device according to the present invention. In this embodiment, a single crystal layer is formed in the opening of the insulating film in a self-aligning manner by using the method for manufacturing a semiconductor device shown in the first embodiment, so that an epitaxial channel (hereinafter referred to as an epi channel) MOS is formed. It is applied when manufacturing a transistor. In FIG. 12A, reference numeral 81 indicates a p-type silicon substrate, and an element isolation insulating film 82 is formed on the silicon substrate 81 by the well-known LOCOS method.
After forming, the single crystal layer 84 to be the channel layer is formed in the opening 83 by epitaxial growth. This time,
The conditions for the epitaxial growth include, for example, flowing Si ₂ H ₆ as a raw material gas without containing 2SCCM etching gas,
If the growth temperature is 750 ° C. and the growth pressure is 5 Pa, the polycrystalline grain deposition start distance L from the end of the opening 83 is about 1.5 μm.
Polycrystalline grains 85 of silicon are deposited on the element isolation insulating film 82 from the position m, while a single crystal silicon layer 84 to be a channel layer is epitaxially grown on the single crystal silicon substrate 81 where the opening 83 is exposed. .

Next, as shown in FIG. 12B, a single crystal region 84 is left in the polycrystalline grain deposition start distance L so as to cover the single crystal silicon layer 84 by a photo process, leaving a resist 86.
After that, the polycrystalline silicon particles 85 deposited on the element isolation insulating film 82 are removed by etching.

Further, as shown in FIG. 12C, after removing the resist 86, a gate oxide film 87, a gate polycrystalline silicon 88, a gate cap layer 89, and a gate sidewall insulating film 90 are formed, and thereafter, ions are formed. By implantation, an n-type source region 91 and an n-type drain region 92 are formed.

As described above, according to the present embodiment, the single crystal silicon layer 84 can be formed only in the opening portion 83 without leaving the polycrystalline silicon particles 85 of silicon on the element isolation insulating film 82. The capacity of the transistor can be reduced. Furthermore, by using the epitaxially grown layer 84 as the channel layer, the concentration of the channel layer can be easily controlled, so that the performance of the MOS transistor can be improved. Needless to say, if the conductivity types described in the present embodiment are made opposite to each other, it can be applied to a p-channel MOS transistor, and a silicon-based gas and a germane-based gas can be supplied as source gases during epitaxial growth. It goes without saying that a single crystal silicon-germanium epichannel can be formed.

<Embodiment 7> FIG. 13 is a sectional view showing still another embodiment of the semiconductor device according to the present invention. The present embodiment is a case where a bipolar transistor is manufactured by forming a single crystal layer in a self-aligned manner using a dummy opening. For convenience of explanation, the same components as those shown in FIG. 9 of the third embodiment are designated by the same reference numerals, and detailed description thereof will be omitted. That is, the present embodiment is different in that dummy openings 34 are provided adjacent to the opening 27 shown in FIG. 9 of the third embodiment at intervals shorter than the polycrystalline grain deposition start distance L. Accordingly, the step of FIG. 13C, which is a step corresponding to FIG. 9C, is different.

In this way, the dummy opening 34 is provided so that the opening 27 is surrounded by the insulating film 26 having a width shorter than the polycrystalline grain deposition start distance L, and the epitaxial growth condition is set to the polycrystalline deposition start distance. By forming the single crystal layer 28 so that L is larger than the width of the insulating film 26, unlike the case of the third embodiment, polycrystalline grains 30 are not formed on the insulating film 26. For example, the distance between the opening 27 and the dummy opening 34 is 1.0 μm, and the source gas is Si ₂ H ₆
2 SCCM, GeH ₄ 0.5 SCCM, ₆₀ ppm H ₂ diluted B ₂ H ₆ 50 SCCM for doping,
Flow without etching gas, growth temperature 750 ℃,
When epitaxial growth is performed under the condition of a growth pressure of 5 Pa, L becomes about 1.5 μm as shown in FIG. 8, so that the polycrystalline silicon / germanium grains are not deposited on the insulating film 2 and the opening portion is not formed. 27 and the dummy opening 34 have a Ge composition ratio of 20% as a base layer and a carrier concentration of 2 × 1.
A 0 ¹⁸ / cm ³ p-type single crystal Si _0.8 Ge _0.2 layer 28 is grown. At this time, since the polycrystalline silicon-germanium layer 29 grows on the base-extracted polycrystalline silicon layer 25 at the same time in the openings 27 and 34, the single-crystal Si _0.8 Ge _0.2 layer 28 serving as an intrinsic base and the base-extracted polycrystalline layer 29 are formed. As shown in FIG. 13B, the silicon layer 25 is connected via the polycrystalline silicon-germanium layer 29 as in the third embodiment. However, unlike the third embodiment, since the polycrystalline grains are not deposited on the insulating film, the photoetching step of FIG. 9C in the third embodiment is unnecessary. Instead, in order to inactivate the dummy opening 34, an insulating film 35 such as SiO _{2 is} deposited by, for example, the CVD method, and then the insulating film 35 is formed by photoetching so as to cover only the dummy opening 34. And then move on to the next step. FIG.
The steps of (d) and FIG. 13 (e) are the same as those of FIG. 9 (d) and FIG.
The same as (e). Reference numeral 36 is a sidewall insulating film 3 that separates the connecting base 29 and the emitter 33.
2 is a side wall insulating film formed in the dummy opening 34 at the same time when 2 is formed.

As described above, according to the present embodiment, a facet-free single crystal layer can be formed only in the opening without considering the alignment accuracy of the mask for removing unnecessary polycrystalline grains. The capacitance of the transistor can be reduced by various processes. Furthermore, since facets do not occur in the intrinsic base 28, the intrinsic base 28 and the connecting base 29
The resistance between them can be reduced. During the growth of the epitaxial base layer, a silicon-based gas is flown as a source gas,
A single crystal silicon layer may be used as an epitaxial base.

<Embodiment 8> FIG. 14 is a sectional view showing a semiconductor device according to still another embodiment of the present invention. The present embodiment is a case where device isolation is performed by forming a single crystal layer in a self-aligned manner using a dummy opening. For convenience of explanation, the same components as those shown in FIG. 10 of the fourth embodiment will be designated by the same reference numerals, and detailed description thereof will be omitted. That is, in this embodiment, the dummy openings 51, 51 are provided adjacent to the openings 43, 43 shown in FIG. 10 of the fourth embodiment at intervals shorter than the polycrystalline grain deposition start distance L. The difference is
Accordingly, FIG. 14 which is a process corresponding to FIG.
The step (c) is different.

As described above, the dummy opening 51 is provided so that the opening 43 is surrounded by the insulating film 42 having a width shorter than the polycrystalline grain deposition start distance L, and the epitaxial growth conditions are set to start the polycrystalline grain deposition. By forming the single crystal layers 44 and 52 so that the distance L is larger than the width of the insulating film 42, polycrystalline grains 45 are not formed on the insulating film 42 unlike the case of the fourth embodiment. For example, the gap between the opening 43 and the dummy opening 51 is set to 1.0 μm, Si ₂ H ₆ is used as a raw material gas for epitaxial growth together with 2SCCM, and a doping gas containing an impurity exhibiting a p-type is allowed to flow without etching gas to grow. By setting the temperature to 750 ° C. and the growth pressure to 5 Pa, the length L of the non-deposited region of polycrystalline grains becomes about 1.5 μm as shown in FIG.
Polycrystal grains of silicon are not deposited on the second layer 2, and the p-type single crystal silicon layers 44 and 5 are formed in the opening 43 and the dummy opening 51.
2 grows.

Unlike the fourth embodiment, the polycrystalline grains 45 are the insulating film 4.
2 in Example 4, as it does not deposit on FIG.
The photoetching step of (c) becomes unnecessary. Instead, an insulating film 53 of SiO ₂ or the like is deposited to cover the dummy opening 52 by, for example, a CVD method, and then the insulating film 53 is left by photoetching so as to cover only the dummy opening 52. , Move to the next step. Note that FIG.
The steps of (d) and FIG. 14 (e) are the same as those of FIG. 10 (d) and FIG. 10 (e), respectively.

As shown in FIG. 14D, an insulating film 48 which is a mask for introducing impurities is formed on only one side of the single crystal silicon region 44 in the same manner as the insulating film 53, and the n-type impurity is ion-implanted. Introduced using FIG.
As shown in (e), a p-type region 49 and an n-type region 50 having different conductivity are formed.

As described above, according to this embodiment, a facet-free single crystal layer can be formed only in the opening without considering the alignment accuracy of the mask for removing unnecessary polycrystalline grains. Element isolation that separates single crystal regions with different conductivity can be performed by various processes.
Since there is no extra element isolation region due to the occurrence of so-called bird's beak unlike the element isolation by the method, the size can be reduced accordingly. Therefore, by forming a transistor in these single crystal regions, high integration of the circuit can be achieved. Further, since no stress is generated between the element isolation insulating film and the single crystal region which is the device region as in the case of the LOCOS method, it is possible to prevent the characteristic deterioration of the device formed in the single crystal region.

An n-type silicon substrate is used as the substrate 41, an n-type epitaxial layer is formed instead of the p-type epitaxial layer 44, and single crystal regions 49 and 50 of different conductivity types are formed by p-type ion implantation. You can
During the epitaxial growth, a silicon-based and germane-based gas may be flown as a source gas to form the silicon-germanium single crystal layer 44. Of course, a resist can be used instead of the insulating film 48 as a mask for ion implantation.

<Embodiment 9> FIG. 15 is a sectional view showing still another embodiment of the method for manufacturing a semiconductor device according to the present invention. The present embodiment is a case where the resistance of the source / drain of the MOS transistor is reduced by forming a single crystal layer in a self-aligned manner using a dummy opening. still,
For convenience of explanation, the same components as those shown in FIG. 11 of the fifth embodiment are designated by the same reference numerals, and detailed description thereof will be omitted. That is, the present embodiment is different in that dummy openings 75 are provided adjacent to the opening 63 shown in FIG. 11 of the fifth embodiment at intervals shorter than the polycrystalline grain deposition start distance L. Accordingly, the step of FIG. 15C, which is a step corresponding to FIG. 11C, is different.

As described above, the dummy opening 75 is provided so that the opening 63 is surrounded by the element isolation insulating film 62 having a width shorter than the polycrystalline grain deposition start distance L, and the epitaxial growth condition is set to polycrystalline. The grain deposition start distance L is the insulating film 62.
By forming the single crystal layer 68 so as to have a width larger than that of No. 6, unlike in the case of Example 5, polycrystalline grains 69 are not formed on the insulating film 62, as shown in FIG. 15B.
For example, the distance between the opening 63 and the dummy opening 75 is 1.
0 μm, and Si as a raw material gas for epitaxial growth
By flowing ₂ H ₆ without using a 2SCCM etching gas, setting the growth temperature to 750 ° C. and the growth pressure to 5 Pa,
As shown in FIG. 8, since the length L of the non-deposited region of the polycrystalline grains is about 1.5 μm, the polycrystalline grains of silicon are not deposited on the element isolation insulating film 62 and the openings 63 and A single crystal silicon layer 68 grows in the dummy opening 75.

Unlike the fifth embodiment, the polycrystalline grains 69 are the insulating film 6.
2 in Example 5, as it does not deposit on FIG.
The photoetching step of (c) becomes unnecessary. Instead, an insulating film 76 of SiO ₂ or the like is deposited to cover the dummy opening 75 by, for example, a CVD method, and then the insulating film 76 is left by photoetching so as to cover only the dummy opening 75. , Move to the next step. Note that FIG.
The step (d) is the same as the step shown in FIG. 11 (d). After the n-type source 71 and the n-type drain 72 are formed by, for example, ion implantation, a refractory metal 73 such as titanium or tungsten is selectively grown on the single crystal silicon layer 68 and reacted with the single crystal silicon layer 68. Thus, the metal silicide layer 74 is formed. This reduces the contact resistance between the source 71 and the drain 72.

As described above, according to the present embodiment, a facet-free single crystal layer can be formed only in the opening portion without considering the alignment accuracy of the mask for removing unnecessary polycrystalline grains. Since a single crystal silicon layer for reducing the resistance can be formed only on the source / drain by various processes, it is possible to prevent the reduction of the single crystal silicon layer 61 to be the source / drain region due to the silicide reaction. Therefore, the source / drain regions can be downsized, and the capacitance can be reduced. Further, since the facet-free single crystal silicon layer 68 can be formed, impurities can be uniformly introduced when forming the source / drain,
It is effective for improving the device capacity and performance. It is needless to say that the present invention can be applied to a case where an n-type silicon substrate is used instead of the p-type silicon substrate 61 and a p-channel MOS transistor is formed as p-type source / drain instead of n-type source / drain.

<Embodiment 10> FIG. 16 is a sectional view showing still another embodiment of the method for manufacturing a semiconductor device according to the present invention. The present embodiment is a case where an epi channel MOS transistor is manufactured by forming a single crystal layer in a self-aligned manner using a dummy opening. For convenience of explanation,
The same components as those shown in FIG. 12 of the sixth embodiment are designated by the same reference numerals, and detailed description thereof will be omitted. That is, the present embodiment is different in that dummy openings 93 are provided at intervals shorter than the polycrystalline grain deposition start distance L adjacent to the opening 83 shown in FIG. 12 of the sixth embodiment, Along with this, the step of FIG. 16B, which is a step corresponding to FIG. 12B, is different.

Thus, the dummy opening 93 is provided so that the opening 83 is surrounded by the element isolation insulating film 82 having a width shorter than the polycrystalline grain deposition start distance L, and the epitaxial growth conditions are set to the polycrystalline grain. By forming the single crystal layer 84 so that the deposition start distance L is larger than the width of the insulating film 82, as shown in FIG. 16B, unlike the case of the sixth embodiment, the single crystal layer 84 is formed on the insulating film 82. The polycrystalline grains 85 do not occur.
For example, the distance between the opening 83 and the dummy opening 93 is 1.
0 μm, and Si as a raw material gas for epitaxial growth
By flowing ₂ H ₆ without using a 2SCCM etching gas, setting the growth temperature to 750 ° C. and the growth pressure to 5 Pa,
As shown in FIG. 8, since L is about 1.5 μm, polycrystalline particles are not deposited on the insulating film 82 and the opening 83 is formed.
The single crystal silicon layer 84 grows only in the dummy opening 93.

Unlike the sixth embodiment, the polycrystalline grains 85 are the insulating film 8.
2 (b) in the sixth embodiment because it is not deposited on FIG.
The photo-etching step is unnecessary. Instead, an insulating film 95 such as SiO ₂ is formed to cover the dummy openings 96.
Is deposited by, for example, a CVD method, and then the insulating film 9 is formed by photoetching so as to cover only the dummy opening 93.
After leaving 5, move to the next step. Since the process of FIG. 16C is the same as the process shown in FIG. 12C, description thereof will be omitted.

As described above, according to the present embodiment, a facet-free single crystal layer can be formed only in the opening without considering the alignment accuracy of the mask for removing unnecessary polycrystalline grains. The capacitance of the MOS transistor can be reduced by various processes. Furthermore, by using the epitaxial growth layer for the channel layer, the concentration of the channel layer can be easily controlled, and thus the performance of the MOS transistor can be improved. If the conductivity types described in the present embodiment are made to be opposite conductivity types, the p-channel MO
Needless to say, it can be applied to an S transistor, and if a silicon-based gas and a germane-based gas are supplied as a source gas during epitaxial growth, an epi channel of single crystal silicon / germanium can be formed.

The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above embodiments, and various design changes can be made without departing from the spirit of the present invention. Is.

[0067]

As is apparent from the above-described embodiments, according to the present invention, epitaxial growth is carried out without flowing an etching gas for producing selectivity, so that corrosion of a manufacturing apparatus can be prevented and safety can be ensured. You can work. Further, as compared with the selective epitaxial growth in which an etching gas of low purity is passed, contaminants mixed in the epitaxial layer can be reduced. Further, since the single crystal layer can be formed only in the opening portion of the insulating film in a self-aligning manner, a semiconductor device having a small parasitic capacitance can be formed. Furthermore, since the selectivity is smaller than that when epitaxial growth is performed by flowing an etching gas, it is possible to form a single crystal layer without generating facets at the boundary between the single crystal and the insulating film, thus preventing deterioration of device characteristics. be able to.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a main part of a main process showing a first embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a cross-sectional view of main parts of main steps showing a second embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 3 is a cross-sectional view of a main part of a main step showing a method for forming a single crystal layer in an opening of an insulating film according to a conventional example.

FIG. 4 is a cross-sectional view of a main part of a main step showing a method for forming a single crystal layer in an opening of an insulating film according to another conventional example.

5 is a perspective view schematically showing a deposition state of polycrystalline grains on an insulating film after the epitaxial growth of the embodiment shown in FIG.

6 is a perspective view schematically showing the movement of silicon molecules or germane molecules on the insulating film during the epitaxial growth of the embodiment shown in FIG.

FIG. 7 is a characteristic diagram showing the growth temperature dependence of the length L of the non-deposited region of polycrystalline grains on the insulating film in the method for manufacturing a semiconductor device according to the present invention.

FIG. 8 is a characteristic diagram showing the growth pressure dependency of the length L of the non-deposited region of polycrystalline particles on the insulating film in the method for manufacturing a semiconductor device according to the present invention.

FIG. 9 is a main-portion cross-sectional view of the main steps of the third embodiment of the method of manufacturing the semiconductor device according to the invention.

FIG. 10 is a main-portion cross-sectional view of the main step of the fourth embodiment of the method of manufacturing the semiconductor device according to the invention.

FIG. 11 is a main-portion cross-sectional view of the main step of the fifth embodiment of the method of manufacturing the semiconductor device according to the invention.

FIG. 12 is a main-portion cross-sectional view of the main step of the sixth embodiment of the method of manufacturing the semiconductor device according to the invention.

FIG. 13 is a main-portion cross-sectional view of the main steps of the seventh embodiment of the method of manufacturing the semiconductor device according to the invention.

FIG. 14 is a main-portion cross-sectional view of the main steps of the eighth embodiment of the method of manufacturing the semiconductor device according to the invention.

FIG. 15 is a main-portion cross-sectional view of the main steps of the ninth embodiment of the method of manufacturing the semiconductor device according to the invention.

FIG. 16 is a tenth method of manufacturing a semiconductor device according to the present invention.
FIG. 6 is a cross-sectional view of a main part of a main process showing the embodiment of.

[Explanation of symbols]

 1 ... Silicon substrate, 2, 47, 48 ... Insulating film, 3, 27, 43, 63, 83 ... Opening of insulating film, 4, 68 ... Epitaxial growth layer (single crystal layer), 5, 30, 45, 69, 85 ... Polycrystalline grain, 6 ... Non-deposited region of polycrystalline grain (polycrystalline grain deposition start distance), 7, 31, 46, 70, 86 ... Resist, 8 ... Dummy insulating film opening, 9, 35, 53, 76, 95 ... Insulating film, ... Insulating film, 10 ... Polycrystalline layer, 11 ... Facet, 12 ... Silicon molecule (atom), 21, 41, 61, 81 ... P-type silicon substrate, 22 ... N-type buried Layers, 23 ... N-type low-concentration collector layer, 24 ... Collector / base isolation insulating film, 25 ... Base extraction polycrystalline layer, 26 ... First emitter / base isolation insulating film, 28 ... N-type epitaxial base layer, 29 ... Tethered base, 32 ... second d Isolation insulating film 33, n-type emitter polycrystalline silicon, 34, 51, 75, 93 ... Opening of dummy insulating film, 36 sidewall insulating film, 42, 62, 82 element isolation insulating film, 44, 49 ... N-type single crystal region, 50 ... P-type single crystal region, 52, 94 ... Single crystal layer, 64, 87 ... Gate oxide film, 65, 88 ... Gate polycrystalline silicon, 66, 89 ... Gate cap layer , 67, 90 ... Gate sidewall insulating film, 71, 91 ... N-type source region, 72, 92 ... N-type drain region, 73 ... Metal layer, 74 ... Metal silicide layer, 84 ... Epitaxial channel layer.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location // H01L 21/3065 (72) Inventor Eiji Oue 1-280, Higashi Koikeku, Kokubunji, Tokyo Hitachi, Ltd. (72) Inventor Katsuyoshi Washio 1-280, Higashi Koigokubo, Kokubunji, Tokyo

Claims (7)

[Claims] 1. A step of forming an insulating film on a single crystal substrate, a step of forming an opening in the insulating film, and a source gas containing no etching gas being supplied to form a single crystal layer in the opening by epitaxial growth. And a step of forming a resist using a mask alignment so as to cover the single crystal layer of the opening and the insulating film within the polycrystalline grain deposition start distance around the opening, and the insulating film during the epitaxial growth using the resist as a mask. A method of manufacturing a semiconductor device, comprising at least a step of etching away the polycrystalline grains formed above. 2. A step of forming an insulating film on a single crystal substrate; a step of forming an opening in the insulating film and a dummy opening at a position not exceeding a polycrystalline grain deposition start distance around the opening. And a step of supplying a source gas containing no etching gas to form a single crystal layer in the opening and the dummy opening by epitaxial growth. 3. The method of manufacturing a semiconductor device according to claim 2, further comprising a step of covering the dummy opening with an insulating film after the epitaxial growth. 4. The single crystal substrate is a silicon substrate, and the source gas is any one of a silicon type, a silicon type and a germane type, and a germane type. A method for manufacturing a semiconductor device as described above. 5. The epitaxial growth temperature in the epitaxial growth step is in the range of 500 to 850 ° C.
5. The method for manufacturing a semiconductor device according to any one of items 4 to 4. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the epitaxial growth pressure in the epitaxial growth step is a pressure not exceeding 100 Pa. 7. The method of manufacturing a semiconductor device according to claim 1, wherein the polycrystalline grain deposition start distance is at least 0.2 μm.