JPH08201111A - Interpolation apparatus - Google Patents

Abstract

PURPOSE: To prevent the lowering of accuracy attributed to fluctuation of a low-order bit of an output signal of an A/D converter in an interpolation apparatus in which a signal from an encoder is converted into a digital signal by an A/D convertor to be supplied to an interpolation circuit. CONSTITUTION: An analog signal to be supplied from a displacement detector is converted into a digital signal by an analog/digital convertor A/D and the digital signal is supplied to a digital lowpass filter DF to remove the fluctuation of a high frequency component, namely, a low-order bit in the signal. Then, the results are supplied to an interpolation circuit IPL. When a hysteresis circuit is provided after the digital lowpass filter, noise left without being removed by the filter only can be removed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interpolating device for linear encoders and rotary encoders used in machine tools, industrial machines, precision length measuring devices, angle measuring devices and the like.

[0002]

2. Description of the Related Art In order to obtain a high interpolation of 100 divisions or more by an interpolation circuit of a linear encoder or a rotary encoder,
A method of obtaining a phase modulation signal by using a balanced modulator and interpolating it (see Japanese Patent Publication No. 5-18364), an arctan by combining an A / D converter and a digital computer.
(Inverse tangent) calculation and interpolation method, interpolation method by A / D converter and lookup table (Japanese Patent Laid-Open No. 49-10)
6744), and a dedicated polar coordinate conversion IC
(DPSP16330: released in May 1987, manufactured by British Pressy Co., Ltd.).

[0003]

When interpolating with a phase-modulated signal, an interpolation clock having a relatively high frequency, which is a multiple of the carrier frequency to be balanced-modulated, is required, and a high-speed logic circuit is required. In addition, the response frequency was only ± 5% of the carrier frequency for balanced modulation, which was not suitable for high-interpolation high-speed response.

The interpolation method using the A / D converter has the following drawbacks. That is, since the A / D converter does not have a hysteresis characteristic, when the signal from the encoder is input to the A / D converter, the digital data output from the A / D converter often has several lower bits for each sample. As a result, the fluttering occurs in the interpolated output and the noise is output as higher-order noise, so that a stable interpolated value cannot be obtained.

As a measure to prevent this, only the stable upper bits are used without using the lower bits that change frequently, or interpolation is performed twice or more the required number of divisions.
A method of applying a hysteresis of 1 resolution or less is adopted.

However, these methods require a higher resolution than the required resolution, or if the computer calculates arctan (inverse tangent of the phase angle of the sinusoidal analog signal) and interpolates, the calculation is performed. Since it is necessary to increase the accuracy, a more expensive CPU with a high processing speed is required.

In the case of the method using the lookup table, a capacity several times larger than the capacity of the required resolution is required. Also, a high resolution A / D converter is required. In general, a high-resolution A / D converter has a low conversion speed and is expensive, and is unsuitable for high-interpolation high-speed response in consideration of cost.

An object of the present invention is to overcome the above-mentioned drawbacks of the conventional interpolating device and obtain a high-resolution and high-speed interpolating circuit with a simple circuit.

[0009]

In order to solve the above problems, according to the present invention, there is provided an interpolation device for interpolating at least one periodic analog signal obtained from a displacement detector. A / D conversion means for converting an analog signal having an amplitude that cyclically changes as a function of the position of the displacement supplied from the device into a digital signal, a digital filter for removing high frequency components of the digital signal, and the digital signal An interpolation device provided with an interpolation means to which the output of the filter is supplied.

In this interpolation device, the digital filter can be constructed by a microcomputer. Further, in this interpolation device, it is preferable to provide a hysteresis circuit between the digital filter and the interpolation circuit. Furthermore, in this interpolation device, the digital filter and the hysteresis circuit can be configured by a microcomputer.

[0011]

According to the present invention, in an interpolating device configured to convert an analog signal into a digital signal and guide it to an interpolating circuit, fluctuations of lower bits of the digital signal are removed by a digital low pass filter. Therefore, the resolution of the A / D converter can be fully utilized, and a highly accurate interpolation device can be obtained with a simple configuration.

Further, since the hysteresis circuit is provided to suppress the change of the lower bits of the digital signal, the fluttering of the output can be further reduced.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION The interpolating device of the present invention supplies data obtained from an A / D converter directly to an interpolating circuit (look-up table or polar coordinate conversion IC) to perform interpolation, or a computer The interpolation calculation is not performed, and the data obtained from the A / D converter is once passed through a digital filter to remove the high frequency noise component from the data before being interpolated.

Further, it is characterized in that a hysteresis circuit, which will be described later, suppresses a momentary fluctuation of the data to make it more stable data and guide it to the interpolating section.

In this type of device, the lower few bits of the output of the A / D converter always fluctuate even if its input does not change. For example, when the full scale is 2Vp-p, 8
If it is a bit A / D converter, it is about 8m per resolution.
There will be V resolution. In audio signals and video signals, the influence of such noise is determined by the ratio (S / N) to the amplitude value of the entire signal, and since it is compared by the effective value, 1 resolution of 8 mV is not often regarded as a problem. In the case of encoder-like signals, this noise becomes a problem.

When the signal of the encoder is interpolated by the comparator, a hysteresis of about 20 to 30 mV is applied so that the output value does not fluctuate. Therefore, in the case of an A / D converter having a resolution of 8 mV, 3 to 4 values, that is, the lower 2 bits, fluctuate.

The fluctuation of this data is suppressed by using a digital filter, interpolation by calculation of arctan,
If it is introduced to an interpolation circuit such as a look-up table, a stable interpolation signal without fluctuation can be obtained. This embodiment is shown in FIG.

In FIG. 1, the input analog signal is A /
The digital signal is converted by the D converter and supplied to the digital filter circuit DF, where it is filtered to obtain a digital signal from which high frequency components have been removed, that is, the lower bits have been rounded and sent to the interpolation circuit IPL.

The digital filter DF is basically a low-pass filter, and as a simple method, addition average may be used. In this case, it is well known that it is particularly easy to realize hardware. FIG. 2 shows an example of a digital filter, which can be constructed by adding signals delayed at the input in synchronization with the system clock with an adder.

Further, as a matter of course, the digital filter characteristic may be calculated by a computer, and in this case, it is needless to say that various filters can be configured as needed. Even if an analog filter is applied to the analog input of the A / D converter, the fluctuation of the A / D converter cannot be suppressed.

FIG. 5 shows an operation flow for obtaining an arithmetic mean. Briefly explaining this flow,
First, the calculation starts in step S1, the head address of the memory is set to n = 1 in step S2, and the address n is set in step S3.
Enter new data into the memory location of. Step S4
Then, add the data of addresses 1 to m (however, m
And the data addition of the stage). In step S5, the addition result is output. As a result, one operation is completed, and when ending the operation, the process proceeds to step S9 and ends.

When the operation is continued, the time T is delayed in the next step S6. In S7, n = n + 1 is calculated.
In step S8, n is compared with m, and if n is larger than m, the process returns to step S2, n = 1 is set, and the above-described operation is repeated. If n is not larger than m in step S8, the process returns to step S3 to continue the addition.

The averaging of digital data has been described above, but the averaging of data is performed by this calculation, and a digital signal with a small change in the lower bits can be obtained. Since the fluttering of the data output from the A / D converter is almost a white noise component, the noise component becomes 1/16 when the digital filter is performed by the arithmetic mean of 16 steps, and the fluttering of the 4-bit width is 1 bit or less. Stable data can be obtained.

Normally, a digital filter requires a considerable number of samples, and there is a concern that the group delay will be long. However, since the video band A / D converter is being digitized in home video cameras today, , A / D converter (up to about 20 Msps) of relatively low price and high speed is available. If these A / D converters are used, a group delay of 1 μsec or less can be realized even with a 16-stage averaging digital filter, and there is almost no problem in applications such as encoders.

In order to remove the noise contained in the output of the A / D converter, there is essentially no problem with only a digital filter, but when the signal is located at the transition of the value of the A / D converter, 1 bit of Changes occur frequently. This is also because the A / D converter has no hysteresis characteristic.

A hysteresis circuit is used to suppress this fluctuation, but this is not an analog hysteresis in which a normal comparator is fed back, but an A / D converter,
This is digital hysteresis performed on digital data after digital filtering, and an interpolation device using this hysteresis circuit is shown in FIG.

In the interpolation apparatus of FIG. 3, the input analog signal is converted into a digital signal in the analog-digital conversion circuit ADC and supplied to the digital filter DF, and as a signal from which high frequency components have been removed by this digital filter. , To the next stage hysteresis circuit HY. The hysteresis circuit HY imparts a hysteresis characteristic to the change of the signal, which will be described in detail below. By passing through this circuit, a stable digital signal can be obtained even with a sudden change. The signal thus obtained is supplied to the interpolation circuit IPL, and a highly accurate and stable interpolation signal is obtained.

FIG. 4 shows an example of the digital hysteresis circuit. The output of the digital filter is supplied to the input terminal 1, and this signal is applied to the 1 input A of the subtractor 7 and also to the input B of the comparator 4 and the input A of the comparator 5.

On the other hand, a hysteresis value is supplied to the input terminal 2, and this signal is applied to the selector 6 and
It is applied to the input B of the adder 3. This hysteresis value is a value determined by how many lower bits of the digital signal are rounded. 0 is applied to the other input B of the selector 6, and when a high signal is applied to the control terminal S, the input signal A is output, and when a low signal is applied, a 0 signal is output. .

The output of the selector 6 is applied to the other input B of the subtracter 7 and subtracted from the output digital signal from the above-mentioned filter applied to the input A, and the difference output is registered circuit (flip-flop). B) 9).

The output of the register circuit 9 is provided as the output of the digital hysteresis circuit, and
It is applied to the input A of the comparator 4. The comparator 4 is a comparator for comparing the value stored in the register circuit 9 with the input digital signal. If the value stored in the register is larger than the input (A> B), the output logic 1 Issue O
The register circuit 9 is enabled through the R circuit 8 and the signal from the subtractor 7 is stored. Note that this accumulation is performed in synchronization with the system clock.

If the signal from the register circuit 9 is smaller than the input digital signal, the output logic of the comparator 4 is 0.
Therefore, since the enable signal is not output to the register circuit 9,
The contents of the register circuit 9 are not changed by this route.

On the other hand, the output signal from the register circuit 9 is
The hysteresis value applied to the input A of the adder 3 and the input B is added, and the result is applied to the input B of the comparison circuit 5. The comparator circuit 5 compares the input digital data with the output of the adder 3, outputs an output logic 1 if the input digital signal is larger, gives a high level signal to the selector 6, and outputs a hysteresis value from the selector 6. Output.

The subtractor 7 subtracts the hysteresis value from the input digital signal and outputs the signal after the subtraction to the register circuit 9
Supply to. At this time, since the output logic of the comparator 5 is 1, the enable signal is given to the register circuit 9 through the OR circuit 8, and therefore, the digital signal whose hysteresis value is subtracted is stored in the register circuit 9. To be done.

If the input digital signal is smaller than the value stored in the register circuit 9 plus the hysteresis, the output logic of the comparator 5 is 0, so the register circuit maintains the previous value.

FIG. 6 shows an outline of the operation flow of this circuit. First, start in step S1 and compare the previous data with the current data in step S2. If the current data is smaller than the previous data, step S1.
In step 5, the data is held as new data this time.

If the present data is larger than the previous data in step S2, the process proceeds to step S3 to compare the value obtained by adding hysteresis to the previous data and the present data, and if the present data is larger, Proceeding to step S4, the hysteresis is subtracted from the current data.

The current data from which this hysteresis has been subtracted is held as new data in step S5, and the process proceeds to step S6 to end the processing. Step S3
If it is determined that the current data is not larger than the previous data, the process proceeds to step S6 and ends.

In this example, a comparator, an adder, a subtractor, and a flip-flop (register circuit) are used to compare the data held in the previous flip-flop for each sample. , This data is unconditionally held in the flip-flop, and compared with the value held in the previous flip-flop plus the hysteresis value. The subtracted value is held in the flip-flop and hysteresis processing can be performed. Note that this hysteresis circuit can also be implemented by software using a computer.

FIG. 7 shows the system configuration when the input to the interpolation circuit is a polyphase signal. As shown in the figure, the signals of each phase are A / D-converted separately, passed through a digital filter and a hysteresis circuit, and then supplied to an interpolation circuit.
Since the processing for the signals of each phase is apparent from the above description, detailed description will be omitted.

FIG. 8 shows that an A / D converter, a digital filter, and a hysteresis circuit are commonly used for polyphase signals.
It is an example of a system configuration of an interpolating device that switches and uses inputs. The analog signals of the respective phases are sample-held in the sampling holding circuits SH1 to SHn, and the switch SW is operated by the selection signal from the timing signal generator TG to make the sampling holding circuits SH1 to SHn.
The contents of Hn are sequentially read, supplied to an A / D converter, converted into a digital signal and sent to a digital filter to remove high frequency components, and sent to a hysteresis circuit, and the hysteresis processed signal is sent to the corresponding registers R1 to R1. Store in Rn.

The accumulated signals of the respective phases are supplied in parallel to the interpolation circuit, where the interpolated signals are produced and output. As described above, if the time-division multiplexing processing is performed on the polyphase signal, the number of A / D converters, digital filters, and hysteresis circuits required can be reduced, and the cost can be reduced.

[0043]

EFFECTS OF THE INVENTION Since the interpolation device of the present invention has the above-mentioned structure, the fluttering of the output signal is reduced,
Or completely excluded. Further, since the resolution of the A / D converter can be effectively used, the number of bits of the A / D converter can be reduced as compared with the conventional method, and the cost can be reduced. In addition, the same A as the conventional device of the same type
If a / D converter is used, high resolution and high speed response can be easily realized.

[Brief description of drawings]

FIG. 1 is a system configuration diagram showing an example of an interpolation device of the present invention.

FIG. 2 is a circuit diagram showing an example of a digital filter applicable to the interpolation device of the present invention.

FIG. 3 is a system configuration diagram showing another example of the interpolation device of the present invention.

FIG. 4 is a circuit diagram of an example of a hysteresis circuit applied to the interpolation device of the present invention.

FIG. 5 is a flowchart showing an arithmetic mean calculation flow applicable to the interpolation device of the present invention.

FIG. 6 is a flowchart showing a calculation flow of hysteresis applicable to the interpolation device of the present invention.

FIG. 7 is a system configuration diagram showing another example of the interpolation device of the present invention.

FIG. 8 is a system configuration diagram showing still another example of the interpolation device of the present invention.

[Explanation of symbols]

 IN input OUT output A / D A / D converter IPL interpolation circuit

Claims (4)

[Claims] 1. An interpolating device for interpolating at least one periodic analog signal obtained from a displacement detector, the amplitude varying periodically as a function of the position of the displacement amount supplied from the displacement detector. A / D conversion means for converting the analog signal to a digital signal, a digital filter for removing high frequency components of the digital signal, and an interpolation means to which an output of the digital filter is supplied,
An interpolator equipped with. 2. The interpolation device according to claim 1, wherein the digital filter is constituted by a microcomputer. 3. The interpolation device according to claim 1, wherein a hysteresis circuit is provided between the digital filter and the interpolation circuit. 4. The interpolation apparatus according to claim 3, wherein the digital filter and the hysteresis circuit are composed of a microcomputer.