JPH08195964A - Voltage controlled oscillation circuit in color television receiver - Google Patents

Abstract

PURPOSE: To prevent hue change caused by the temporary operation of an APC filter voltage lock circuit when burst signals temporarily run out or when the burst signals are shifted due to skews or the like at the time of demodulating the video output of a VTR. CONSTITUTION: This circuit controls the phase of a VCO 6 so as to match the oscillation frequency of the VCO 6 with the phase of the burst signals. When a discrimination circuit 10 discrimiates that the burst signal is present at least once in one vertical period, the APC filter voltage lock circuit 11 is turned off in the next one vertical period and an f0 center voltage generated by an APC circuit 5 and held in an APC filter 4 is used as the control voltage of the VCO 6. Thus, even when the burst signals temporarily run out or when the phases of the burst signals and burst gate signals are shifted during the one vertical period, the APC filter voltage lock circuit 11 is not operated and the APC filter voltage is maintained at the f0 center voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage controlled oscillator circuit used for a color synchronizing circuit of a color television receiver.

[0002]

2. Description of the Related Art A color synchronizing circuit of a color television receiver is constructed as shown in FIG.

In FIG. 2, a color subcarrier modulated by a color difference signal component (hereinafter referred to as a carrier color signal) is input to an input terminal 1, and an automatic phase consisting of a burst gate circuit 2, a phase detection circuit 3 and a filter circuit 4 is provided. Control circuit (hereinafter AP
(Referred to as C circuit) 5. Burst gate circuit 2
Then, the burst signal is extracted from the input carrier color signal using the burst gate pulse from the terminal 8 and supplied to one input end of the phase detection circuit 3. Phase detection circuit 3
A color subcarrier oscillated by a voltage controlled oscillator (hereinafter referred to as VCO) 6 is supplied to the other input terminal of the. The phase detection circuit 3 detects the phase difference between the burst signal and the color subcarrier from the VCO 6 and supplies it to the filter circuit 4.
The filter circuit 4 is composed of a low-pass filter circuit, integrates the voltage from the phase detection circuit 3 and supplies it to the VCO 6 as an oscillation control voltage. The VCO 6 is composed of an oscillation circuit including a crystal oscillator, and the filter circuit 4
The oscillating frequency is controlled based on the control voltage from the output terminal 7 of the reference color subcarrier in phase with the burst signal.
Output to. A hue adjustment circuit is inserted in a feedback loop that feeds back the output of the VCO 6 to the phase detection circuit 3.
If the phase is rotated by a predetermined angle, the VCO 6 oscillates with that phase difference, and if the color is demodulated using that as a reference subcarrier, the hue can be adjusted.

As described above, in the color synchronizing circuit, the phase difference between the burst signal and the color subcarrier oscillated by the VCO 6 is detected by the phase detecting circuit 3, and the error signal is integrated by the filter circuit 4 to obtain VCO 6 It controls and reproduces the reference color subcarrier exactly in phase with the burst signal.

FIG. 3 shows a specific circuit example of the color synchronizing circuit. The same circuit elements as those in FIG. 2 will be described with the same reference numerals.

In FIG. 3, the VCO 6 is composed of a voltage controllable oscillation circuit 6a and a crystal oscillator (X'tal) connected (externally) to its terminal P1 via a capacitor C3. A control voltage is supplied to the control terminal from the filter circuit 4, and a reference color subcarrier required for color demodulation is output from the output terminal. On the other hand, APC
The circuit 5 includes a burst gate circuit 2 for extracting the burst gate signal from the carrier color signal at the terminal 1 by using the burst gate pulse, and a phase for phase detection of the extracted burst gate pulse and the reference color subcarrier from the VCO 6. It is composed of a detection circuit 3, a current conversion means for converting the phase detection signal into a current amount, and a filter circuit 4 for charging and discharging with this current to generate a control voltage. The burst gate circuit 2 connects the emitters of two transistors Q4 and Q7 in common, connects a constant current source I1 between this common emitter and the reference potential point GND, and connects the base of the transistor Q4 to the carrier from the terminal 1. Supply color signal, transistor Q7
A biasing DC voltage source V1 is connected to the base of the transistor, and a switching transistor Q for operating these transistors only in the burst period is provided between the DC power supply line VCC and the common emitter of the transistors Q4 and Q7.
1 is connected in series, and a negative burst gate pulse from the terminal 8 is supplied to the base of the transistor Q1. That is, the period during which the burst gate pulse is supplied is
The transistor Q1 is turned off, the burst gate circuit 2 or the APC circuit 5 is in the operating state (on), the transistor Q1 is turned on and the burst gate circuit 2 or the APC circuit 5 is in the non-operating state during the period other than the burst gate pulse period. (Off).

In the phase detection circuit 3, the emitters of two transistors Q3 and Q5 are connected in common to form a differential pair, and the emitters of two transistors Q6 and Q9 are connected in common to form a differential pair. , Transistors Q5, Q6
The bases of transistors Q3 and Q9 are connected in common, the collectors of transistors Q3 and Q6 are connected in common, the collectors of transistors Q5 and Q9 are connected in common, and the transistors Q3 and Q5 are connected in common. The emitter is connected to the collector of the transistor Q4, and the common emitter of the transistors Q6 and Q9 is connected to the transistor Q4.
The reference color subcarrier from the VCO 6 is connected between the common bases of the transistors Q3 and Q9 and the common bases of the transistors Q5 and Q6.

The current converting means is a DC power supply line VCC
And a common collector of the transistors Q3 and Q6, a resistor R1 and an emitter and collector of the transistor Q2 are connected in series, and the base and collector of the transistor Q2 are connected in common while the DC power supply line VCC and the transistor Q5, A resistor R2 and the emitter and collector of a transistor Q8 are connected in series between the common collector of Q9, and the base and collector of the transistor Q8 are commonly connected.
Furthermore, a resistor R is placed between the DC power supply line VCC and the reference potential point GND.
3 and the emitter and collector of the transistor Q10, the collector and emitter of the transistor Q11 and the resistor R4 are connected in series, while the resistor R5 and the emitter and collector of the transistor Q13 and the collector of the transistor Q14 are connected between the DC power supply line VCC and the reference potential point GND. , An emitter and a resistor R6 are connected in series, the bases of the transistors Q2 and Q10 are commonly connected, the bases of the transistors Q8 and Q13 are commonly connected, and the bases of the transistors Q11 and Q14 are commonly connected. , And a switching transistor Q between the DC power line VCC and the common base of the transistors Q11 and Q14.
The collector and the emitter of 12 are connected in series, the base of the transistor Q12 is connected to the collector of the transistor Q10, and the current is output from the collector of the transistor Q13 and supplied to the terminal P2. The switching transistor Q12 is turned on / off depending on whether the current output from the transistor Q10 is the positive side or the negative side, thereby turning on / off the transistors Q11 and Q14 at the same time and outputting from the collector of the transistor Q13. The phase detection current on the positive electrode side can be quickly charged to the filter circuit 4. The resistors R1 and R3 have the same resistance value, and the transistors Q2 and Q10 have the same resistance.
And a current mirror circuit, and resistors R2 and R5
Have the same resistance value, and the transistors Q8 and Q13 form a current mirror circuit.

The filter circuit 4 is constructed by connecting a series circuit of a resistor R9 and a capacitor C2 and a capacitor C1 in parallel between the terminal P2 and a reference potential point GND.

In addition to the above configuration, the collector voltage of the transistor Q13, that is, the control voltage of the terminal P2, is determined by the discrimination circuit 10.
APC for locking (fixing) based on the judgment result of
A filter voltage lock circuit 9 is provided. The determination circuit 10 outputs a low level (hereinafter, referred to as L level) when there is a burst signal in the input signal, and outputs a high level (hereinafter, referred to as H level) when there is no burst signal. In the figure, the carrier color signal is input to determine the presence or absence of a burst signal. The burst presence / absence determination signal from the determination circuit 10 is supplied to the APC filter voltage lock circuit 9 through the inverter G1. The APC filter voltage lock circuit 9 determines whether or not there is a burst signal in the determination circuit 10, and operates (ON) when there is no burst signal.
Then, it is a circuit for locking (fixing) the APC filter voltage to a predetermined value (center value of the oscillation frequency of the VCO 6). The APC filter voltage lock circuit 9 is in a non-operation (OFF) state when the determination circuit 10 determines that there is a burst signal.

The APC filter voltage lock circuit 9 is constructed as follows. That is, the output terminal of the inverter G1 is connected to the positive side of the biasing DC voltage source V4 via the resistor R9, and is connected to the base of the transistor Q17, and the emitter of the transistor Q17 is connected to the reference potential point GND via the resistor R8. The common emitter of the two transistors Q16 and Q19 is connected to the collector of the transistor Q17. Two transistors Q16, Q
Among the transistors 19, the base and collector of the transistor Q16 are commonly connected, the base is connected to the APC filter voltage terminal P2 via the resistor R7, and the DC voltage source V3 is connected to the base of the transistor Q19. The emitter and collector of the transistor Q15 are connected in series between the DC power supply line VCC and the collector of the transistor Q16, and the emitter and collector of the transistor Q18 are connected in series between the DC power supply line VCC and the collector of the transistor Q19. Connect to
The bases of the transistors Q15 and Q18 are commonly connected, and the base and collector of the transistor Q18 are commonly connected. Furthermore, the DC power supply line VCC and the transistor Q1
A switching transistor Q20 for turning on and off the operation of the APC filter voltage lock circuit is connected in series between the common emitter of 6 and Q19, and a negative polarity burst from the terminal 8 is connected to the base of the transistor Q20. A gate pulse is supplied. That is, while the burst gate pulse is being input to the transistor Q20, the transistor Q20 is off and the APC filter voltage lock circuit is in an operating state (on). During the period other than the burst gate pulse period, the transistor Q20 is on and the APC filter voltage lock circuit is on. The filter voltage lock circuit becomes inactive (off).

Here, in order to explain the role of the APC filter voltage lock circuit 9, a case where the APC filter voltage lock circuit 9 is not provided will be described. When there is no burst signal in the input signal of the color television receiver, that is, when no burst signal is detected in the carrier color signal, A
Since the phase detection cannot be performed by the PC circuit 5, the control by the APC filter voltage V2 cannot be normally performed, and the VCO oscillation frequency deviates from the center value (f0). When the input signal changes to a signal having a burst signal, it takes time to pull in f0 of the VCO 6, and the hue change appears on the screen.

Therefore, in the conventional circuit of FIG. 3, in order to prevent this hue change as much as possible, the APC filter voltage (V2) is set so that the oscillation frequency of the VCO is near the center (f0) even when there is no burst signal. Is the APC filter voltage at the VCO oscillation frequency center (f0) (hereinafter, f
An APC filter voltage lock circuit 9 for setting the voltage near the 0 center voltage is provided so that the f0 pull-in time can be shortened when the state without a burst signal is changed to a certain state.

The control of the operation of the APC filter voltage lock circuit 9 uses the output signal of the discrimination circuit 10 for discriminating the mode of the input signal as shown in FIG.
That is, in the burst gate period, when the determination circuit 10 determines that there is no burst signal in the input signal, the transistor Q20 is off and Q17 is on, the APC filter voltage lock circuit 9 is in the operating state (on), and the resistor R7 is used. Therefore, the APC filter voltage V2 is set to the voltage (hereinafter referred to as the APC lock voltage) V3 determined by the APC filter voltage lock circuit 9. In the burst gate period, when the determination circuit 10 determines that there is a burst signal, the transistor Q20 is turned off and the transistor Q17 is turned off.
When it is off, the APC filter voltage lock circuit 9 is in a non-operating state (off).

As a result, even when the input signal has no burst signal as shown in FIG. 4, the APC filter voltage lock circuit 9 sets the APC filter voltage to the APC lock voltage V3 close to the f0 center voltage.
The oscillation frequency of was always kept near the center (f0). FIG. 4 shows an ideal oscillation frequency control characteristic, where the horizontal axis shows the APC filter voltage and the vertical axis shows the VCO oscillation frequency.

By the way, when the discrimination circuit 10 discriminates that there is no burst signal, the APC filter voltage V2 is A
The APC lock voltage V3, that is, the f0 center voltage should be set by the PC filter voltage lock circuit 9,
APC lock voltage V3 is VCO
It does not always match the f0 center voltage of 6.

In such a case, the output of the discriminating circuit 10 for discriminating the presence / absence of the burst signal as described above is directly applied to the AP.
In the system used for controlling the C filter voltage lock circuit 9, when the burst signal disappears temporarily,
When the phase of the burst signal and the burst gate pulse are deviated due to the skew during VTR special reproduction during demodulation of the R video output, the APC filter voltage lock circuit 9 operates (turns on) to set the APC filter voltage to the APC filter voltage. In order to set the lock voltage V3, as shown in FIG.
The oscillation frequency of (f0) deviates from the center value (f0).
0 + Δf). When the skew is eliminated, the APC filter voltage lock circuit 9 does not operate (OFF).
At this time, the APC circuit 5 starts the pulling operation so that the oscillation frequency of the VCO 6 becomes the center value (f0). Therefore, the APC circuit 5 starts the pull-in operation,
Until the oscillation frequency of the VCO 6 is pulled to the center value (f0), the output phase of the VCO 6 is out of phase.
It appears as a hue change on the screen.

[0018]

As described above, conventionally,
When the burst signal disappears temporarily, or when the phase of the burst signal and the burst gate pulse deviates due to the influence of skew etc. while demodulating the video output of the VTR, the APC filter voltage lock circuit is temporarily operated. There is a problem in that the operation causes a hue change to appear on the screen.

Therefore, in view of the above problems, the present invention temporarily addresses when the burst signal disappears temporarily, or when the burst signal is deviated due to skew or the like during demodulation of the video output of the VTR. Another object of the present invention is to provide a voltage controlled oscillator circuit in a color television receiver which can prevent a hue change on the screen due to the operation of the APC filter voltage lock circuit.

[0020]

According to a first aspect of the present invention, there is provided a voltage controlled oscillating circuit for a color television receiver according to the first aspect of the present invention, an oscillator whose oscillation frequency can be controlled by a control voltage, an output of the oscillator, and a carrier color signal. Phase control means for detecting a phase difference from the burst signal extracted from the control circuit, integrating the detection signal and supplying it as a control voltage to the oscillator, and control voltage fixing means capable of fixing the control voltage to a certain value. And a discrimination means for discriminating the presence / absence of a burst signal included in the carrier color signal, and an output signal of this discrimination means is inputted, and only when it is determined that there is no burst signal for one vertical period, the next one vertical period is When the control voltage fixing means is operated and it is determined that there is a burst signal even once in one vertical period, the control voltage fixing means is made inoperative in the next vertical period. Gosuru is characterized in that and means.

According to another aspect of the voltage controlled oscillator circuit in the color television receiver of the present invention, the discrimination circuit outputs a discrimination signal of a high level when there is a burst signal and discriminates a low level when there is no burst signal. A signal is output, and the means for controlling the operation of the control voltage fixing means is reset by a first inverting circuit for inverting the discrimination signal from the discrimination circuit and a pulse obtained by delaying the vertical synchronizing pulse by a predetermined time. A latch circuit for inputting and latching a signal from the first inverting circuit, a second inverting circuit for inverting the vertical synchronizing pulse, and a pulse from the second inverting circuit for CK input, and the latch A D-type flip-flop which receives a signal from the circuit as a D input to obtain a Q output, and an output of the flip-flop which is inverted and supplied as a control signal to the control voltage fixing means. The control voltage fixing means operates when the output of the third inverting circuit is a high level signal, and is inactive when the output of the third inverting circuit is a low level signal. It is characterized by that.

[0022]

According to the present invention, when the phase of the oscillator is controlled so that the oscillation frequency of the oscillator and the phase of the burst signal match, if the discriminating means discriminates that there is a burst signal even once in one vertical period, the following 1 During the vertical period, the control voltage fixing means is turned off, and the control voltage of the oscillator is set to the f0 center voltage generated by the phase control means. In other words, 1
Even if the burst signal temporarily disappears during the vertical period (including the case where the burst signal and the burst gate signal are out of phase due to skew during VTR special reproduction), the control voltage fixing means does not operate and is controlled. Voltage can be maintained at f0 center voltage. However, when the determining means determines that there is no burst signal in all the one vertical period, the control voltage fixing means is turned on and the control voltage is fixed to the set voltage by the control voltage fixing means in the next one vertical period.

Therefore, even if the burst signal disappears temporarily or the phase of the burst signal and the burst gate pulse deviates due to skew or the like, the control voltage fixing means does not operate, and the oscillation frequency of the oscillator is in phase. It is held at the f0 center voltage generated by the control means, and the hue change on the screen can be prevented.

[0024]

EXAMPLES Examples will be described with reference to the drawings. FIG. 1 is a block diagram showing a voltage controlled oscillator circuit in a color television receiver according to an embodiment of the present invention. The same elements as those of FIG. 3 are described with the same reference numerals.

In the embodiment shown in FIG. 1, a logic processing circuit 1 is provided between an APC filter voltage lock circuit 9 as a control voltage fixing means and a discrimination circuit 10 in the conventional circuit of FIG.
1 is provided, and the operation control of the APC filter voltage lock circuit 9 is performed according to the result of the logic processing of the output signal of the determination circuit 10 by the circuit 11. Therefore, the logic processing circuit 11 functions as a means for controlling the operation of the APC filter voltage lock circuit 9 which is a control voltage fixing means.

The configuration of FIG. 1 will be described in detail below. V
CO6 is a voltage controllable oscillator circuit 6a and its terminal P1.
And a crystal oscillator (X'tal) connected (externally) via a capacitor C3 to the VCO6. The control voltage is supplied from the filter circuit 4 to the control terminal of the VCO6, and the color voltage is output from the output terminal. The reference color subcarrier required for demodulation is output. On the other hand, the APC circuit 5 uses the burst gate circuit 2 for extracting the burst gate signal from the carrier color signal of the terminal 1 using the burst gate pulse, the extracted burst gate pulse and the reference color subcarrier from the VCO 6 in phase. It is composed of a phase detection circuit 3 for detecting, a current conversion means for converting the phase detection signal into a current amount, and a filter circuit 4 for charging and discharging with this current to generate a control voltage. The burst gate circuit 2 connects the emitters of two transistors Q4 and Q7 in common, connects a constant current source I1 between this common emitter and the reference potential point GND, and connects the base of the transistor Q4 to the carrier from the terminal 1. A color signal is supplied, a bias DC voltage source V1 is connected to the base of the transistor Q7, and these transistors are operated only during the burst period between the DC power supply line Vcc and the common emitter of the transistors Q4 and Q7. A switching transistor Q1 for switching is connected in series, and a negative burst gate pulse from the terminal 8 is supplied to the base of the transistor Q1. That is, during the period in which the burst gate pulse is supplied, the transistor Q1 is turned off and the burst gate circuit 2, that is, the APC circuit 5 is in the operating state (on).
Then, in the period other than the burst gate pulse period, the transistor Q1 is turned on, and the burst gate circuit 2 or A
The PC circuit 5 is in a non-operating state (OFF).

In the phase detection circuit 3, the emitters of the two transistors Q3 and Q5 are connected in common to form a differential pair, and the emitters of the two transistors Q6 and Q9 are connected in common to form a differential pair. , Transistors Q5, Q6
The bases of transistors Q3 and Q9 are connected in common, the collectors of transistors Q3 and Q6 are connected in common, the collectors of transistors Q5 and Q9 are connected in common, and the transistors Q3 and Q5 are connected in common. The emitter is connected to the collector of the transistor Q4, and the common emitter of the transistors Q6 and Q9 is connected to the transistor Q4.
The reference color subcarrier from the VCO 6 is connected between the common bases of the transistors Q3 and Q9 and the common bases of the transistors Q5 and Q6.

The current converting means is a DC power supply line VCC
And a common collector of the transistors Q3 and Q6, a resistor R1 and an emitter and collector of the transistor Q2 are connected in series, and the base and collector of the transistor Q2 are connected in common while the DC power supply line VCC and the transistor Q5, A resistor R2 and the emitter and collector of a transistor Q8 are connected in series between the common collector of Q9, and the base and collector of the transistor Q8 are commonly connected.
Furthermore, a resistor R is placed between the DC power supply line VCC and the reference potential point GND.
3 and the emitter and collector of the transistor Q10, the collector and emitter of the transistor Q11 and the resistor R4 are connected in series, while the resistor R5 and the emitter and collector of the transistor Q13 and the collector of the transistor Q14 are connected between the DC power supply line VCC and the reference potential point GND. , An emitter and a resistor R6 are connected in series, the bases of the transistors Q2 and Q10 are commonly connected, the bases of the transistors Q8 and Q13 are commonly connected, and the bases of the transistors Q11 and Q14 are commonly connected. , And a switching transistor Q between the DC power line VCC and the common base of the transistors Q11 and Q14.
The collector and the emitter of 12 are connected in series, the base of the transistor Q12 is connected to the collector of the transistor Q10, and the current is output from the collector of the transistor Q13 and supplied to the terminal P2. The switching transistor Q12 is turned on / off depending on whether the current output from the transistor Q10 is the positive side or the negative side, thereby turning on / off the transistors Q11 and Q14 at the same time and outputting from the collector of the transistor Q13. The phase detection current on the positive electrode side can be quickly charged to the filter circuit 4. The resistors R1 and R3 have the same resistance value, and the transistors Q2 and Q10 have the same resistance.
And a current mirror circuit, and resistors R2 and R5
Have the same resistance value, and the transistors Q8 and Q13 form a current mirror circuit.

The filter circuit 4 is constructed by connecting a series circuit of a resistor R9 and a capacitor C2 and a capacitor C1 in parallel between the terminal P2 and a reference potential point GND.

In addition to the above configuration, the collector voltage of the transistor Q13, that is, the control voltage of the terminal P2, is determined by the discrimination circuit 10.
An APC filter voltage lock circuit 9 is provided for locking the determination output of (1) based on the result of logic processing by the logic processing circuit 11. The determination circuit 10 determines the presence / absence of a burst signal, and outputs an L level when there is a burst signal in the input signal, and outputs an H level when there is no burst signal. In the figure, the carrier color signal is input to determine the presence or absence of a burst signal. The burst presence / absence determination signal from the determination circuit 10 is supplied to the APC filter voltage lock circuit 9 through the logic processing circuit 11. The operation of the APC filter voltage lock circuit 9 is controlled by the result of logic processing of the burst signal presence / absence determination signal by the determination circuit 10 by the logic processing circuit 11. The APC filter voltage lock circuit 9 determines the next 1 only when the determination circuit 10 determines that there is no burst signal in one vertical period based on the output of the logic processing circuit 11.
It is a circuit for operating (turning on) during the vertical period to lock the APC filter voltage at the terminal P2 at a predetermined value (center value of the oscillation frequency of the VCO 6). If the determination circuit 10 determines that there is a burst signal even once in one vertical period, the APC filter voltage lock circuit 9 is in a non-operation state (OFF) in the next one vertical period.

The logic processing circuit 11 is constructed as follows. That is, the determination signal of the determination circuit 10 is supplied to the latch circuit L1 via the inverter G4. The latch circuit L1 is formed by connecting two inverters G2 and G3 in a plow shape. That is, by connecting the input end of the inverter G2 and the output end of the inverter G3,
The output terminal of 2 and the input terminal of the inverter G3 are connected, and the signal from the inverter G4 is used as an input signal for the inverter G.
The vertical synchronizing pulse (hereinafter referred to as V pulse) from the terminal 12 is supplied to the input end of the inverter G3 as a reset signal, and is input to the input end of the inverter G3. The output signal is output from the output terminal of the D-type flip-flop F1 and supplied to the input terminal D of the D-type flip-flop F1. D-type flip-flop F
A signal obtained by inverting the V pulse from the terminal 1 by the inverter G6 is supplied to the clock terminal CK of 1. In addition,
The delay amount of the delay circuit D1 is set to a predetermined value exceeding the pulse width of the V pulse. Also, the D-type flip-flop F
1 uses the negative trigger method. As a result, the output of the D-type flip-flop F1 becomes the H level when the D input signal is at the H level when the V pulse rises, that is, when the CK input falls. The Q output of the flip-flop F1 is inverted by the inverter G1 and the APC filter voltage lock circuit 9
Is supplied to the base of the transistor Q17.

The APC filter voltage lock circuit 9 is constructed as follows. That is, the output terminal of the inverter G1 is connected to the positive side of the biasing DC voltage source V4 via the resistor R9, and is connected to the base of the transistor Q17, and the emitter of the transistor Q17 is connected to the reference potential point GND via the resistor R8. The common emitter of the two transistors Q16 and Q19 is connected to the collector of the transistor Q17. Two transistors Q16, Q
Among the transistors 19, the base and collector of the transistor Q16 are commonly connected, the base is connected to the APC filter voltage terminal P2 via the resistor R7, and the DC voltage source V3 is connected to the base of the transistor Q19. The emitter and collector of the transistor Q15 are connected in series between the DC power supply line VCC and the collector of the transistor Q16, and the emitter and collector of the transistor Q18 are connected in series between the DC power supply line VCC and the collector of the transistor Q19. Connect to
The bases of the transistors Q15 and Q18 are commonly connected, and the base and collector of the transistor Q18 are commonly connected. Furthermore, the DC power supply line VCC and the transistor Q1
A switching transistor Q20 for turning on and off the operation of the APC filter voltage lock circuit is connected in series between the common emitter of 6 and Q19, and a negative polarity burst from the terminal 8 is connected to the base of the transistor Q20. A gate pulse is supplied. That is, while the burst gate pulse is being input to the transistor Q20, the transistor Q20 is off and the APC filter voltage lock circuit is in an operating state (on). During the period other than the burst gate pulse period, the transistor Q20 is on and the APC filter voltage lock circuit is on. The filter voltage lock circuit becomes inactive (off).

Next, the operation of this embodiment will be described with reference to the discrimination circuit 10,
The logic processing circuit 11 and the APC filter voltage lock circuit 9 will be mainly described.

First, in the logic processing circuit 11, the output of the latch circuit L1 is reset to the L level at the falling edge of the V pulse from the terminal 12 and becomes the L level, and in one vertical period, the V pulse is at the H level period (vertical pattern period). If the output of the determination circuit 10 becomes H level even once, the latch output holds the H level until the next V pulse is input. This latch output is input to the D input terminal of the D-type flip-flop F1, and when the inverted pulse of the next V pulse is input to the CK input terminal (actually, when the inverted pulse falls), the next one vertical period. At, the H level of the D input is continuously output from the Q output terminal. Then, the Q output of the flip-flop F1 maintains its H level state until the next inverted pulse of the V pulse is input to the clock input terminal CK (actually, until the inverted pulse falls). This H level is inverted by the inverter G1 and becomes L level, and is supplied to the base of the transistor Q17. Therefore, the transistor Q17 is turned off and the APC filter voltage lock circuit 9 is deactivated (off).

Therefore, if the discriminating circuit 10 discriminates that there is a burst signal even once in one vertical period, the logic processing circuit 11 processes the discriminating signal to control the APC filter voltage lock circuit 11, and the next one vertical period. During the period, the APC filter voltage lock circuit 11 is turned off, and the control voltage of the VCO 6 (that is, the APC filter voltage V2 of the terminal P2) is AP.
F0 of the APC filter 4 by the phase detection operation of the C circuit 5
Set to the center voltage. In other words, if the burst signal temporarily disappears during one vertical period (V
Even if the burst signal and the burst gate signal are out of phase due to skew during TR special playback)
The PC filter voltage lock circuit 11 does not operate A
The PC filter voltage can be maintained at the f0 center voltage.

Only when the decision circuit 10 decides that there is no burst signal for one vertical period, the logic processing circuit 11 controls the APC filter voltage lock circuit 11 to control the APC filter voltage lock for the next one vertical period. The circuit 9 is turned on to lock the control voltage of the VCO 6 (that is, the APC filter voltage V2) to the APC lock voltage V3.

As described above, the APC filter voltage lock circuit 9 does not operate even if the burst signal disappears temporarily or the phase of the burst signal and the burst gate pulse deviates due to a skew or the like, and the oscillation frequency of the VCO 6 is centered. It is held as a value and can prevent the hue change on the screen.

[0038]

As described above, according to the present invention, when the burst signal disappears temporarily or when the video output of the VTR is demodulated, the APC filter voltage is temporarily locked due to the influence of skew or the like. Hue changes due to the operation of the circuit can be minimized.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a voltage controlled oscillator circuit in a television receiver according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a voltage controlled oscillator circuit used in a color synchronizing circuit of a conventional color television receiver.

FIG. 3 is a circuit diagram showing a specific circuit example of a conventional voltage controlled oscillator circuit.

FIG. 4 is a diagram showing ideal oscillation frequency control characteristics in a voltage controlled oscillator circuit.

FIG. 5 is a diagram showing an actual oscillation frequency control characteristic in a conventional voltage controlled oscillator circuit.

[Explanation of symbols]

1 ... Carrier color signal input terminal 2 ... Burst gate gate circuit 3 ... Phase detection circuit 4 ... Filter circuit 5 ... APC circuit (phase control means) 6 ... VCO (oscillator) 8 ... Burst gate pulse input terminal 9 ... APC filter voltage lock Circuit (control voltage fixing means) 10 ... Burst presence / absence determining circuit (determination means) 11 ... Logic processing circuit (means for controlling operation of control voltage fixing means) 12 ... V pulse input terminal L1 ... Latch circuit F1 ... D flip-flop G1, G4, G6 ... Inverter (inverting circuit)

Claims (2)

[Claims] 1. An oscillator whose oscillation frequency can be controlled by a control voltage, detects a phase difference between the output of this oscillator and a burst signal extracted from a carrier color signal, and integrates this detection signal to the oscillator. Phase control means supplied as a control voltage, control voltage fixing means capable of fixing the control voltage to a certain value, determination means for determining the presence or absence of a burst signal included in the carrier color signal, and this determination means When the output signal is input and it is determined that there is no burst signal in one vertical period, the control voltage fixing means is operated for the next one vertical period, and it is determined that there is a burst signal even once in one vertical period. A voltage controlled oscillator circuit in a color television receiver, comprising: a means for controlling the control voltage fixing means so as not to operate during the next vertical period. 2. The discriminating circuit outputs a high level discriminating signal when there is a burst signal, and outputs a low level discriminating signal when there is no burst signal. The control means is reset by a first inverting circuit that inverts the discrimination signal from the discrimination circuit and a pulse obtained by delaying the vertical synchronizing pulse for a predetermined time, and inputs and latches the signal from the first inverting circuit. Latch circuit, a second inverting circuit for inverting the vertical synchronizing pulse, and a D-type flip-flop for obtaining a Q output by using the pulse from the second inverting circuit as CK input and the signal from the latch circuit as D input. And a third inverting circuit that inverts the output of the D-type flip-flop and supplies it as a control signal to the control voltage fixing means, wherein the control voltage fixing means is When the output of the third inverting circuit is a high-level signal operates, the voltage controlled oscillation circuit in a color television receiver, characterized in that when a low level signal is made inoperative.