JPH08195655A - Hopper type voltage comparator - Google Patents

Abstract

PURPOSE: To prevent an inverter from malfunctioning by suppressing the propagation of voltage variation to the input terminal of an inverter owing to mixing of noise of a power source system at the time of input switching for voltage comparison. CONSTITUTION: This chopper type voltage comparator is provided with a capacity 3 which has its input terminal connected to a 1st input selection switch 5 and a 2nd input selection switch 6 for selecting an input and is charged or discharged by the difference between the voltage at the input terminal and output terminal, and plural feedback switches 2-1 to 2-3 which are connected between the input terminal and output terminal of the inverter 1, connected in series with the output terminal of the capacity 3, and are equal in continuity resistance value; and only the feedback switch 2-3 which maximize the feedback resistance value of the inverter 1 is turned ON at the time of the input switching.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chopper type voltage comparator used for analog-digital conversion or the like in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing a conventional chopper type voltage comparator. In FIG.
Is a feedback transistor as a feedback switch connected between the input and output ends of the inverter 1.

Further, 3 is a charge holding capacitor connected to the input side of the inverter 1, 4 is a control clock applied to the gate of the feedback transistor 2, 5 and 6 receive the control clock 4, and are set to the level thereof. Accordingly, when one is turned on, the other is turned off, that is, the first input selection switch and the second input selection switch.

Further, 7 is connected to the first input selection switch 5, a first input terminal to which the first input is supplied, 8 is connected to the second input selection switch 6, and the second input is connected. At the supplied second input terminal, the output terminals of these input selection switches 5 and 6 are both connected to the input terminal which is the first terminal of the charge storage capacitor 3.

Further, 9 is an input terminal of the inverter 1 connected to the output terminal which is the second terminal of the charge storage capacitor 3, 10 is an output terminal of the inverter 1, and 11 is a first signal obtained by inverting the control clock 4 described above. It is an inverter that is input between the input selection switch 5 and the second input selection switch 6.

Next, the operation will be described. First, when the control clock 4 is at a high level, the first input selection switch 5 is in a conductive state, while the second input selection switch 6 is in a cutoff state. A voltage level which is a first input applied to the first input terminal 7 is applied.

On the other hand, at the same time, the feedback transistor 2 is rendered conductive in response to the control clock 4 and the input terminal 9 and the output terminal 10 of the inverter 1 are in the initial state of the same intermediate level.

The level of the input terminal 9 at this time is also applied to the output terminal of the charge holding capacitor 3, so that
The charge of the voltage difference between the voltages at these input terminals and output terminals is held, and the balance of this system is maintained.

Next, when the control clock 4 is at a low level, the first input selection switch 5 is cut off,
On the other hand, the second input selection switch 6 becomes conductive. Therefore, the voltage level applied to the second input terminal 8 is applied to the input terminal of the charge storage capacitor 3.

On the other hand, at the same time, the feedback transistor 2
Is in a cutoff state, the inverter 1 is in a state of detecting a voltage difference, and the connection of the input / output terminal of the inverter 1 is released. Then, the voltage difference between the voltage applied to the first input terminal 7 and the voltage applied to the second input terminal 8 is reflected on the output terminal of the charge storage capacitor 3, that is, the input terminal 9 of the inverter 1 by capacitive coupling. The inverter 1 detects this voltage change, and the detection result appears at the output terminal 10.

Specifically, the voltage at the first input terminal 7 is the second
When the voltage is lower than the voltage of the input terminal 8 of the charge holding capacitor 3, the charge holding capacitor 3 is charged by inputting a charge having a voltage difference obtained by subtracting the voltage of the first input terminal 7 from the voltage of the second input terminal 8. It

Therefore, at the output end of one of the charge holding capacitors 3, the charge corresponding to the charge charged at the input end by capacitive coupling with the input end of the charge holding capacitor 3, in other words, the second
The potential rises by the difference obtained by subtracting the voltage of the first input terminal 7 from the voltage of the input terminal 8 of. Then, the inverter 1 detects the increase in the potential of the input terminal 9 and outputs a low level to the output terminal 10.

On the contrary, when the voltage of the first input terminal 7 is higher than the voltage of the second input terminal 8, from the input terminal of the charge storage capacitor 3 to the voltage of the first input terminal 7 to the second input terminal. The charge of the voltage difference obtained by subtracting the voltage of 8 is discharged, and the potential at the output end of the charge storage capacitor 3 decreases according to this voltage difference. Then, the inverter 1 detects the decrease in the potential of the input terminal 9 and outputs a high level to the output terminal 10.

[0014]

Since the conventional chopper type voltage comparator is constructed as described above, noise or the like is mixed in the power supply system of the inverter 1 immediately before the inverter 1 changes from the initial state to the detection state. As a result, when the power supply voltage changes, a change corresponding to the noise level is made through the feedback transistor 2 so that the input terminal 9 and the output terminal 10 of the inverter 1 are at the intermediate level of the same potential under the changed power supply voltage. May appear at the input 9 of the inverter 1.

In this case, since the feedback transistor 2 is completely cut off, the potential of the input terminal 9 of the inverter 1 is fixed while being changed by noise, the inverter 1 is in the voltage difference detection state, and the power supply system Even after the noise disappears, the inverter 1 detects a voltage change due to the noise, and there is a problem that the output terminal 10 outputs an incorrect comparison result.

On the other hand, as a method for solving such a malfunction, a layout or a circuit in which switching noise is unlikely to be mixed in the power supply system is taken as a countermeasure, the sensitivity to noise is lowered by lowering the detection gain of the inverter 1, and the feedback transistor 2 is used. Methods such as suppressing the feedback of noise by increasing the resistance value are adopted.

However, even with such a method, if the integration and speed of the semiconductor integrated circuit are increased, the layout and circuit countermeasures will be limited, and the accuracy will be sacrificed when the detection gain of the inverter 1 is lowered. Therefore, when the resistance of the feedback transistor 2 is increased, it takes time to set the inverter 1 to the initial state, and there is a problem that the comparison speed is reduced as it is. It was

The present invention has been made to solve the above-mentioned problems, and makes it difficult to propagate a voltage change to the input terminal of the inverter due to the mixing of noise in the power supply system, thereby preventing malfunction of the inverter. The purpose is to obtain a chopper type voltage comparator.

Another object of the present invention is to obtain a chopper type voltage comparator capable of surely preventing malfunction of the inverter due to noise mixing in the power supply system by selecting the feedback switch having the maximum conduction resistance.

A further object of the present invention is to obtain a chopper type voltage comparator capable of reliably preventing malfunction of the inverter with a simple structure by maximizing the conduction resistance of the feedback switch.

[0021]

According to another aspect of the present invention, there is provided a chopper type voltage comparator which selects a first input or a second input according to a level of a control clock and outputs the selected first input. A switch and a second input selection switch, and an input terminal connected to the first input selection switch and the second input selection switch for holding a charge of a voltage difference between voltages at the input terminal and the output terminal A capacitor and a plurality of feedback switches having the same conduction resistance value, which are connected between the input terminal and the output terminal of the inverter connected in series to the output terminal of the charge holding capacitor, are provided, and the inverter is provided in the clock generation circuit. During initialization, all of the feedback switches are turned on, while at the time of switching between the first input and the second input, the feedback switch that maximizes the feedback resistance value of the inverter. Chinomi is obtained so as to turn on the.

In a chopper type voltage comparator according to a second aspect of the present invention, an input end is connected to the first input selection switch and the second input selection switch, and the voltage difference of the voltage at the input end and the output end is calculated. A charge holding capacitor for holding charges is provided, and a plurality of feedback switches having a conduction resistance value from a minimum to a maximum are connected between an input terminal and an output terminal of an inverter connected in series to the output terminal of the charge holding capacitor. In the clock generation circuit, when the inverter is initialized, the feedback switch having the smallest conduction resistance value is turned on, while the first switch is turned on.
At the time of switching between the input and the second input, only the feedback switch that maximizes the feedback resistance value of the inverter is turned on.

In the chopper type voltage comparator according to the invention of claim 3, the input ends are connected to the first input selection switch and the second input selection switch, and the voltage difference of the voltage at the input end and the output end is calculated. A charge holding capacitor for holding charges is provided, a feedback switch is connected between an input terminal and an output terminal of an inverter connected in series to the output terminal of the charge holding capacitor, and the control signal generation circuit is connected to the first input and When the second input is switched, a control signal for controlling the conduction resistance of the feedback switch to the maximum value is output.

[0024]

In the chopper type voltage comparator according to the invention of claim 1, when the resistance of the feedback switch is lowered to speed up the initialization of the inverter, the feedback switch includes a plurality of feedback switches having the same resistance value. The feedback resistance of the inverter is divided into switches and the number of conductive switches among these feedback switches is controlled to be the minimum by the time the first input and the second input for voltage comparison are switched. Maximize the value.

In the chopper type voltage comparator according to the invention of claim 2, the feedback switch is divided into a plurality of feedback switches having different resistance values, and the feedback switch having the largest conduction resistance among these feedback switches. The switch is controlled to conduct when the first input and the second input for voltage comparison switch.

In the chopper type voltage comparator according to the third aspect of the present invention, the feedback switch is a switch having a characteristic that the conduction resistance is variable, and the first input and the second voltage comparison are performed.
The control clock generation circuit controls the feedback switch so that the conduction resistance is maximized when the input is switched.

[0027]

【Example】

Example 1. Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a chopper type voltage comparator according to an embodiment of the present invention.
-3 is a feedback transistor (feedback switch) connected in parallel with each other having the same conduction resistance, 4-1 to 4-3 are control clocks of these feedback transistors 2-1 to 2-3, and 12 is a control. Feedback transistor 2 from clock 4
It is a clock generation circuit that generates control clocks 4-1 to 4-3 for 1-2.

1 is an inverter, 3 is an inverter 1
Charge holding capacitors 5 and 6 connected to the input side of the first input selection switch and the second input selection switch 5 and 6 are turned off when one is turned on in response to the control clock 4.

Further, 7 is a first input terminal connected to the first input selection switch 5, 8 is a second input terminal connected to the second input selection switch 6, and each of these input selection switches. The output terminals 5 and 6 are both the first terminals of the charge holding capacitor 3.
It is connected to the input terminal which is the terminal of.

Further, 9 is the input terminal of the inverter 1 connected to the output terminal, which is the second terminal of the charge storage capacitor 3, 10 is the output terminal of the inverter 1, and 11 is the first signal obtained by inverting the control clock 4 described above. It is an inverter that is input between the input selection switch 5 and the second input selection switch 6.

Next, the operation will be described with reference to the timing chart of FIG. 2 showing the signals of the respective parts of the circuit of FIG. First, the clock generation circuit 12 receives the control clock 4 and receives the control clock 4 having different on times as shown in FIG.
-1 to 4-3 are separately generated.

Therefore, during the period in which the inverter 1 is initialized by the control clock 4 being at the high level, the control clocks 4-1 to 4-3 are all at the high level and the feedback transistors 2-1 to 2-2-. 3 becomes conductive.

When the control clock 4-1 becomes low level after a certain period of time, the feedback transistor 2-1 is used.
Is cut off, and the feedback resistance value of this circuit increases to 1.5 times the value when all the feedback transistors 2-1 to 2-3 are in the conductive state.

Then, after a lapse of a predetermined period with a further delay, the control clock 4-2 becomes low level, the feedback transistor 2-2 is turned off at this time, and the feedback resistance value of this circuit further rises from the above. In comparison, when all the feedback transistors 2-1 to 2-3 are in the conductive state, the number is three times as large.

According to this embodiment, the detection gain of the inverter 1 is increased by increasing (maximizing) the feedback resistance when the first input and the second input at which malfunction due to noise is most likely to occur are switched. Inverter 1 without lowering
It is possible to suppress the voltage change due to the noise from being transmitted to the input side of the inverter 1 without delaying the initialization of the.

Example 2. FIG. 3 is a block diagram showing a chopper type voltage comparator according to another embodiment of the present invention. In the figure, 2-4 to 2-6 are feedback transistors (feedback switches), and the conduction resistance value of the feedback transistor 2-6 is the maximum.

Further, 4-4 to 4-6 are control clocks for the feedback transistors 2-4 to 2-6, and 13 is a control clock 4 to control clocks 4-4 to 4-4 as shown in FIG.
6 is a clock generation circuit for generating 6. The other circuit parts that are the same as those shown in FIG. 1 are designated by the same reference numerals, and the duplicated description thereof will be omitted.

Next, the operation will be described with reference to the timing chart of FIG. 4 showing the signals of the respective parts of this circuit. First, the clock generation circuit 13 receives the control clock 4 and outputs the control clock 4 having different on times as shown in FIG.
-4 to 4-6 are generated.

Further, in the period in which the control clock 4 becomes high level and the inverter 1 is initialized, first, when the control clock 4-4 becomes high level, the transistor 2-4 having the minimum conduction resistance becomes conductive.

Next, the control clock 4-4 becomes low level and the control clock 4-5 becomes high level, so that the feedback transistor 2-4 is turned off and the feedback transistor 2-5 is turned on. The feedback resistance value of this inverter 1 becomes high.

Subsequently, the control clock 4-5 becomes low level and the control clock 4-6 becomes high level, whereby the feedback transistor 2-5 is turned off and the feedback transistor 2-having the maximum conduction resistance value. By making 6 conductive, the feedback resistance value of this circuit becomes maximum.

By switching to the feedback transistor 2-6 having the maximum conduction resistance in this way, the noise output at the moment when the first input and the second input for voltage comparison are switched is fed back. By delaying, the comparison result due to this noise can be prevented from being output from the inverter 1.

Example 3. FIG. 5 is a block diagram showing a chopper type voltage comparator according to another embodiment of the present invention. In the figure, 2-7 is a feedback transistor (feedback switch), 4-7 is a control signal for controlling this feedback transistor 2-7, and 14 is the control signal 4-7 generated from the control clock 4. Is a control signal generation circuit for.
The other circuit parts that are the same as those shown in FIG. 1 are designated by the same reference numerals, and the duplicate description thereof will be omitted.

Next, the operation will be described. First, the control signal generation circuit 14 receives the control clock 4 and outputs the control signal 4-7 at a level at which the feedback transistor 2-7 becomes conductive while the control clock 4 is at a high level. In this case, immediately after the control clock 4 is asserted, the control signal at the maximum level of the gate signal level at which the feedback transistor 2-7 becomes conductive is given to the gate of the feedback transistor 2-7.

Immediately before the control clock 4 is negated, the feedback transistor 2-7 generates the minimum level control signal 4-7 which does not turn off. By doing so, the feedback resistance of this circuit can be maximized, and an erroneous comparison result based on noise generated at the moment when the first input and the second input are switched is output to the inverter 1
It is possible to prevent the output from.

It is well known that the feedback transistor 2-7 used as the feedback switch has a conduction resistance that changes depending on the voltage applied to its gate, and therefore its detailed description is omitted here.

[0047]

As described above, according to the invention of claim 1, the first input selection switch and the second input selection switch for selecting and outputting the first input or the second input according to the level of the control clock. An input selection switch, an input terminal connected to the first input selection switch and the second input selection switch, and a charge holding capacity for holding a charge of a voltage difference between voltages at the input terminal and the output terminal; A plurality of feedback switches having the same conduction resistance value, which are connected between the input terminal and the output terminal of the inverter connected in series to the output terminal of the charge storage capacitor, are provided, and the clock generation circuit is provided with , Turning on all of the feedback switches, while switching between the first input and the second input,
Since only the feedback switch that maximizes the feedback resistance value of the inverter is turned on, at the moment when the first input and the second input for voltage comparison are switched, the feedback switch among the plurality of feedback switches is fed back. An effect is obtained in which an arbitrary one having the maximum resistance is cut off to make it difficult to propagate a voltage change to the inverter input terminal due to the noise mixture of the power supply system and prevent the malfunction of the inverter.

According to the invention of claim 2, the input terminal is connected to the first input selection switch and the second input selection switch, and the charge for holding the charge of the voltage difference between the voltage at the input terminal and the output terminal is held. A holding capacitor is provided, and a plurality of feedback switches having conduction resistance values from a minimum to a maximum are connected between an input terminal and an output terminal of an inverter connected in series to an output terminal of the charge holding capacitor, and a clock generation circuit, At the time of initialization of the inverter, the feedback switch having the minimum conduction resistance value is turned on, while at the time of switching between the first input and the second input, the feedback resistance that maximizes the feedback resistance value of the inverter. Since only the switch is turned on, the one having the largest conduction resistance among the plurality of feedback switches is switched and selected at the moment when the first input and the second input are switched. , The effect of which the malfunction of the inverter based on the noise interference power supply system just before switched its turn can be reliably prevented is obtained.

According to the third aspect of the present invention, the input terminal is connected to the first input selection switch and the second input selection switch, and the charge for holding the electric charge of the voltage difference between the voltage at the input terminal and the output terminal is held. A holding capacitor is provided, a feedback switch is connected between an input terminal and an output terminal of an inverter connected in series to the output terminal of the charge holding capacitor, and the control signal generation circuit is connected to the first input and the second input. Since the control signal for controlling the conduction resistance of the feedback switch to the maximum value is output at the time of switching, the conduction resistance of the feedback switch becomes maximum at the moment when the first input and the second input switch. By controlling the feedback switch so that the malfunction of the inverter can be reliably prevented with a simple configuration, there is an effect.

[Brief description of drawings]

FIG. 1 is a block diagram showing a chopper type voltage comparator according to an embodiment of the present invention.

FIG. 2 is a timing chart showing signals of various parts of the circuit of FIG.

FIG. 3 is a block diagram showing a chopper type voltage comparator according to another embodiment of the present invention.

FIG. 4 is a timing chart showing signals of various parts of the circuit of FIG.

FIG. 5 is a block diagram showing a chopper type voltage comparator according to another embodiment of the present invention.

FIG. 6 is a block diagram showing a conventional chopper type voltage comparator.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 inverter, 2-1 to 2-7 feedback transistor (feedback switch), 3 charge holding capacity, 5 1st input selection switch, 6 2nd input selection switch, 12,
13 clock generation circuit, 14 control signal generation circuit.

Claims (3)

[Claims] 1. A first input selection switch and a second input selection switch for selecting and outputting the first input or the second input according to the level of a control clock, and the first input selection switch and An input terminal is connected to the second input selection switch, and a charge holding capacitor that holds a charge of a voltage difference between voltages at the input terminal and the output terminal and an input of an inverter connected in series to the output terminal of the charge holding capacitor And a plurality of feedback switches connected between the output terminal and the output terminal and having the same conduction resistance value, and when the inverter is initialized, all of the feedback switches are turned on, while the first input and the second input switches are turned on. And a clock generation circuit for a control clock that turns on only a feedback switch that maximizes the feedback resistance value of the inverter when the input of the chopper type voltage comparator is switched. 2. A first input selection switch and a second input selection switch for selecting and outputting the first input or the second input according to the level of a control clock, and the first input selection switch and An input terminal is connected to the second input selection switch, and a charge holding capacitor that holds a charge of a voltage difference between voltages at the input terminal and the output terminal and an input of an inverter connected in series to the output terminal of the charge holding capacitor A plurality of feedback switches having a minimum to maximum conduction resistance value connected between the terminal and the output terminal, and at the time of initialization of the inverter, the feedback switch having the minimum conduction resistance value is turned on, while the above A clock generation circuit for a control clock that turns on only the feedback switch that maximizes the feedback resistance value of the inverter when switching between the first input and the second input. Top-type voltage comparator. 3. A first input selection switch and a second input selection switch for selecting and outputting the first input or the second input according to the level of a control clock, and the first input selection switch and An input terminal is connected to the second input selection switch, and a charge holding capacitor that holds a charge of a voltage difference between voltages at the input terminal and the output terminal and an input of an inverter connected in series to the output terminal of the charge holding capacitor A feedback switch connected between the output terminal and the output terminal, and a control signal generation that outputs a control signal for controlling the conduction resistance of the feedback switch to the maximum value when the first input and the second input are switched. A chopper type voltage comparator equipped with a circuit.