JP4047466B2 - Capacitance sensor circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a capacitance sensor circuit.
[0002]
[Prior art]
  Conventionally, a capacitance sensor circuit for detecting a capacitance difference between two detection electrodes has been disclosed in Japanese Utility Model Application Publication No. 63-36246. As shown in FIG. 10, this circuit includes a pulse signal generation circuit, a variable resistor, a first variable delay circuit, a second variable delay circuit, and phase discriminating means, and the detection electrode has a first variable delay. The circuit and the reference electrode are connected to the second variable delay circuit.
[0003]
  The pulse signal output from the pulse signal generation circuit is branched to the first variable delay circuit and the second variable delay circuit via a variable resistor. Both variable delay circuits have a capacitance between the detection electrode and the ground (hereinafter referred to as “detection electrode capacitance”) when an object to be detected is present in the detection region, and a capacitance between the reference electrode and the ground. (Hereinafter referred to as “reference electrode capacitance”), the input pulse signal is delayed, and each pulse signal is output to the phase discriminating means as the comparing means.
[0004]
  The phase discriminating means compares the phases of the input pulse signals, and outputs a detection signal if the phase shift is equal to or greater than a predetermined threshold value. It should be noted that the capacitance between the detection electrode and ground (hereinafter referred to as “detection electrode basic capacitance”) and the capacitance between the reference electrode and ground (hereinafter referred to as “reference”) when no detection object is present in the detection region. The difference from “electrode basic capacity” was that the variable resistance was adjusted manually.
[0005]
[Problems to be solved by the invention]
  In the capacitance sensor circuit described above, when either the detection electrode basic capacitance or the reference electrode basic capacitance fluctuates due to noise or the like, the phase difference of the delayed pulse signal due to the difference between the two basic capacitances is predetermined. If it is equal to or greater than the threshold value, a detection signal is output even when there is no object to be detected in the detection area. That is, it malfunctions.
[0006]
  In order to prevent the malfunction due to the difference between the detection electrode basic capacitance and the reference electrode basic capacitance, it can be avoided by setting the threshold value large. However, if the threshold value is set to be large, when a detection object having a predetermined charge amount is detected, the detection object cannot be detected unless the detection object approaches or contacts the detection electrode. That is, there is a problem that the detection sensitivity has to be lowered.
[0007]
  In addition, when the object approaches and stops within the area of the detection electrode, the charge amount of the detection electrode remains in an increased state, so that another object is newly detected. There was a problem that even if it entered the area, it could not be detected.
[0008]
  The present invention solves the problems of the capacitance sensor circuit described above, and does not cause malfunction even if the balance between the detection electrode basic capacitance and the reference electrode basic capacitance is lost, and also provides stable sensitivity and high detection sensitivity. It is an object to provide a capacitance sensor circuit that can be maintained.
[0009]
[Means for Solving the Problems]
  The capacitance sensor circuit according to claim 1, wherein the pulse signal generation circuit generates a pulse signal, and the pulse signal is converted into a clock signal, a first data signal, and a first data signal based on a change in capacitance of at least two detection electrodes. A comparator for forming two data signals, a time between the timing t2 of the first data signal and the timing t1 of the clock signal, and a time between the timing t1 of the clock signal and the timing t3 of the second data signal. Automatic balance adjustment means for comparing the clock signal and the first data signal, and determining means for comparing and determining the clock signal and the second data signal,The comparison means is connected to a first detection electrode and forms the clock signal, the second comparator is connected to a second detection electrode and forms the first data signal, and the first comparator A delay circuit for delaying a data signal to form the second data signalThat's it.
[0010]
  The capacitance sensor circuit according to the present invention forms a clock signal, a first data signal, and a second data signal based on a change in capacitance of the two detection electrodes, and controls the time between the timings, The detection sensitivity of the two detection electrodes can be maintained at a predetermined sensitivity.
[0011]
  The capacitance sensor circuit according to claim 2, wherein the automatic balancing means includes a time between the timing t2 of the first data signal and the timing t1 of the clock signal, and between the timing t1 of the clock signal and the timing t3 of the second data signal. The time is controlled evenly.
[0012]
  The capacitance sensor circuit according to the present invention can maintain the detection sensitivity of the two detection electrodes at a substantially equal sensitivity. In addition, noise that enters the detection electrode from the outside affects the two detection electrodes substantially evenly, so that the influence of this noise can be efficiently eliminated.
[0013]
  The specific configuration of the comparison means according to claim 1 is as follows:A first comparator connected to the first detection electrode and forming the clock signal; a second comparator connected to the second detection electrode and forming the first data signal; and delaying the first data signal Delay circuit for forming a second data signalAnd is added as a specific requirement of the present invention.
[0014]
  Claim 3In the described capacitance sensor circuit, the automatic balance adjusting means variably controls the comparison voltage of the second comparator.
[0015]
  Since the capacitance sensor circuit according to the present invention controls only the second comparator by the automatic balance adjusting means, it is not necessary to control the first comparator. Therefore, the circuit configuration can be simplified, the control can be facilitated, and the operation reliability of the circuit can be improved.
[0016]
  Claim 4The described capacitance sensor circuit is such that the automatic balance adjusting means is a D / A conversion circuit operated by a CPU.
[0017]
  Since the capacitance sensor circuit according to the present invention uses a D / A conversion circuit operated by a CPU, automatic balance adjustment can be precisely performed.
[0018]
  Claim 5In the capacitance sensor circuit described above, as a result of the judgment unit comparing the clock signal and the first data signal and comparing the clock signal and the second data signal, one of them is in an invalid detection state for a predetermined time or more. If it is determined, the automatic balance adjusting means is activated.
[0019]
  Claim 6In the described capacitance sensor circuit, the determination unit compares the clock signal and the first data signal, and as a result of comparing the clock signal and the second data signal, it is determined that one of them is in the valid detection state. In some cases, a detection signal is output.
[0020]
  Claim 7In the described capacitance sensor circuit, after the judgment means outputs the detection signal, the clock signal and the first data signal are compared, and as a result of comparing the clock signal and the second data signal, either one is predetermined. If it is determined that the state is in the valid detection state for more than the time, the automatic balance adjusting means is activated.
[0021]
  The capacitance sensor circuit according to the present invention allows another object to enter the detection area by operating the automatic balance adjusting means even when the object approaches and stops in the detection electrode area. Can be detected.
[0022]
  Claim 8In the capacitance sensor circuit described above, the judging means includes a first flip-flop circuit that compares the clock signal and the first data signal, a second flip-flop circuit that compares the clock signal and the second data signal, and a first flip-flop. And a CPU for judging output signals of the flip-flop circuit and the second flip-flop circuit.
[0023]
  Claim 9In the described capacitance sensor circuit, the delay circuit performs automatic sensitivity adjustment by variably controlling the delay time of the second data signal.
[0024]
  Claim 10In the described capacitance sensor circuit, when the judging means compares the clock signal with the first data signal and also compares the clock signal with the second data signal, it is judged that both are in the invalid detection state. In this method, the delay circuit is activated to lower the detection sensitivity.
[0025]
  Claim 11In the described capacitance sensor circuit, the delay circuit is composed of an integration circuit having a plurality of time constants selected by the CPU.
[0026]
  Claim 12In the described capacitance sensor circuit, the determination unit operates the automatic balance adjustment unit immediately after the operation of the capacitance sensor circuit.
[0027]
  Claim 13In the described capacitance sensor circuit, the judging means operates the delay circuit immediately after the capacitance sensor circuit is activated, and sets the detection sensitivity to the highest state.
[0028]
DETAILED DESCRIPTION OF THE INVENTION
  A capacitance sensor circuit according to the present invention will be described with reference to FIG. This circuit is formed by connecting a surge protection circuit 10, a comparison circuit 20, a waveform shaping circuit 30, a flip-flop circuit 40, and a CPU 80 in series from the input terminals 1 and 2, and further, the waveform shaping circuit 30. Is connected to a delay circuit 50, and the comparison circuit 20 is connected to a D / A conversion circuit 60.
[0029]
  Further, the circuit includes a stabilized power supply circuit 120, a reset circuit 130, an LED display circuit 140, and a CPU clock 150. The reset circuit 130 stops the operation of the CPU 80 and maintains the reset state until the supply voltage to the CPU 80 reaches a predetermined operable voltage after the power is turned on. It is a circuit for lighting LED141, 142, 143, 144 for monitoring the detection state of this.
[0030]
  A first detection electrode 6 is connected to the input terminal 1, and the first detection electrode is disposed to face the ground electrode 8. Further, the second detection electrode 7 is connected to the input terminal 2 and is disposed to face the ground electrode 9. In the present embodiment, the basic capacitance between the first detection electrode 6 and the ground electrode 8 and the basic capacitance between the second detection electrode 7 and the ground electrode 9 are adjusted to be the same. It is not necessarily the same.
[0031]
  The input terminals 1 and 2 are followed by a transformer 5, which constitutes a low-pass filter for noise removal. Further, a surge protection circuit 10 following the transformer 5 is provided to remove surge noise. Note that the transformer 5 and the surge protection circuit 10 are not necessarily required, and other circuits for noise removal can be used as appropriate.
[0032]
  The port 81 of the CPU 80 that supplies the 1/2 DUTY 249 Hz pulse signal P1 is branched and connected to the resistors 11 and 12 of the surge protection circuit 10 via the amplification resistors 3 and 4 respectively. The frequency of the pulse signal P1 is not limited to the above frequency.
[0033]
  The pulse signal P1 is converted into a first integrated waveform signal P2 by an integration circuit configured by the amplification resistor 3 and a capacitor formed between the first detection electrode 6 and the ground electrode 8. The inclination of the rising edge is determined by the time constant of the amplification resistor 3 and the capacitor formed between the first detection electrode 6 and the ground electrode 8. In addition, the pulse signal P1 is converted into the second integrated waveform signal P3 by an integrating circuit constituted by the amplification resistor 4 and a capacitor formed between the second detection electrode 7 and the ground electrode 9.
[0034]
  The comparison circuit 20 forms a first comparator 22 that forms a first delayed pulse signal P4 obtained by delaying the first integrated waveform signal P2, and a second delayed pulse signal P5 that produces a second delayed waveform signal P3. 2 comparator 23 is provided. The first integrated waveform signal P <b> 2 is input to the positive pole 221 of the first comparator 22, and a DC voltage fixed to 1.25 V by the resistor 24 is supplied to the negative pole 222. The capacitors 25 and 27 are smoothing decoupling capacitors, and the resistor 26 is a voltage dividing resistor.
[0035]
  On the other hand, the second integrated waveform signal P3 is input to the positive pole 231 of the second comparator 23, and a variably controlled DC voltage from a D / A conversion circuit 60 described later is supplied to the negative pole 232. Since both the comparators 22 and 23 are open collectors, a DC voltage is supplied to the output terminals 223 and 233 via the pull-up resistors 28 and 29.
[0036]
  The waveform shaping circuit 30 includes a first knot circuit 31, a second knot circuit 32, and a third knot circuit 33. The first knot circuit 31 inverts the phase of the first delay pulse signal P4 and shapes the waveform to the clock signal P6. The second knot circuit 32 inverts the phase of the second delay pulse signal P5 and Waveform shaping to 1 data signal P7.
[0037]
  The third knot circuit 33 forms a second delayed pulse signal P5 branched immediately after the output terminal 233 of the second comparator 23 by delaying it in four stages by a delay circuit 50 to be described later, inverts the phase, 2 Waveform shaping to data signal P8.
[0038]
  The flip-flop circuit 40 includes a first flip-flop circuit 41 and a second flip-flop circuit 42 which are delay flip-flop circuits. The first data signal P7 is input to the data input terminal 411 of the first flip-flop circuit, and the clock signal P6 is input to the clock input terminal 412. The first flip-flop circuit 41 inverts the signal level of the first data signal P7 at the timing of the rising edge of the clock signal P6 and outputs the first FF output signal P9 from the output terminal 413 to the port 82 of the CPU 80.
[0039]
  The second data signal P8 is input to the data input terminal 421 of the second flip-flop circuit 42, and the clock signal P6 is input to the clock input terminal 422. The second flip-flop circuit 42 outputs the second data signal P8 from the output terminal 423 to the port 83 of the CPU 80 as the second FF output signal without inverting the signal level of the second data signal P8 at the rising edge timing of the clock signal P6.
[0040]
  The delay circuit 50 includes a resistor 51, capacitors 52, 53 and 54, and MOS transistors 55 and 56. The gates of the MOS transistors 55 and 56 are connected to the ports 84 and 85 of the CPU 80, respectively, and are ON / OFF controlled.
[0041]
  The delay circuit 50 controls the time constant of the integrating circuit in the delay circuit 50 in four stages by ON / OFF control of the MOS transistors 55 and 56. Accordingly, the delay time of the branched second delay pulse signal is controlled in four stages. That is, when both MOS transistors 55 and 56 are OFF controlled, the resistor 51 and the capacitor 52 constitute an integrating circuit.
[0042]
  Further, when only the MOS transistor 55 is ON-controlled, the resistor 51 and the capacitors 52 and 53 are ON. When only the MOS transistor 56 is ON-controlled, the resistor 51 and the capacitors 52 and 54 are ON-controlled, and both the MOS transistors 55 and 56 are ON-controlled. An integrating circuit is configured by the resistor 51 and the capacitors 52, 53, and 54.
[0043]
  The D / A conversion circuit 60 is composed of resistors 62 to 69 connected to the ports 86 to 93 of the CPU 80, and converts 8-bit digital binary data signals from each port into a DC voltage. Then, a DC voltage of 1.0 to 1.5 V is variably controlled in 256 steps and supplied to the negative pole 232 of the second comparator 23. In this embodiment, 8-bit digital binary data is used. However, the circuit according to the present invention is not limited to the number of bits.
[0044]
  Next, the operation of the circuit of this embodiment will be described with reference to timing charts shown in FIGS. First, a state immediately after the power supply of this circuit is turned on will be described with reference to FIG.
[0045]
  When the power supply of this circuit is turned on, the pulse signal P1 output from the port 81 of the CPU 80 is branched and converted into the first integrated waveform signal P2 and the second integrated waveform signal P3 by the integration circuits. The
[0046]
  The first integrated waveform signal P2 is converted into a first delayed pulse signal P4 having a falling edge at a timing t1 when the threshold value of the 1.25V DC voltage supplied to the first comparator 22 is exceeded. On the other hand, the second integrated waveform signal P3 is converted into a second delayed pulse signal P5 having a falling edge at a timing t2 when the threshold value of the variable DC voltage supplied to the second comparator 23 is exceeded.
[0047]
  In the timing chart shown in FIG. 2, since the variable DC voltage supplied to the negative pole 232 of the second comparator 23 is the minimum value of 1.0 V, the timing t1 of the first delay pulse signal P4 is the second delay. It is ahead of the timing t2 of the pulse signal P5.
[0048]
  The first delayed pulse signal P4 is input to the first knot circuit 31, is output as the clock signal P6, and is supplied to the clock input terminals 412 and 422 of the first flip-flop circuit 41 and the second flip-flop circuit 42.
[0049]
  The branched second delayed pulse signal P5 is input to the second knot circuit 32 and input to the first flip-flop circuit 41 as the first data signal. Further, the other branched second delayed pulse signal P5 is delayed by a predetermined time by the delay circuit 50, and is then input to the third knot circuit 33, to the second flip-flop circuit 42 as the second data signal P8. Entered. Therefore, the timing t3 of the rising edge of the second data signal P8 is controlled to be further delayed than the timing t2.
[0050]
  Since the first data signal P7 is at the LOW level at the timing t1 of the rising edge of the clock signal P6, the first FF output signal P9 to be inverted is a HIGH level signal. On the other hand, since the second data signal P8 is at the LOW level, the second FF output signal P10 output as it is is a LOW level signal.
[0051]
  Next, the CPU 80 increases the variable DC voltage supplied to the negative pole 232 of the second comparator 23 from the minimum value of 1.0 V until the first FF output signal becomes the LOW level. This variable DC voltage is obtained by converting the 8-bit digital binary code signal output from the ports 86 to 93 of the CPU 80 by the D / A conversion circuit 60, and has 256 levels of voltage values. . Accordingly, the 8-bit digital binary code signal is incremented by +1 to increase the variable DC voltage. Note that it is not always necessary to add one by one, and first data and second data to be described later can be obtained by roughly adding or subtracting at a predetermined interval.
[0052]
  When the variable DC voltage is raised and the first FF output signal changes from HIGH level to LOW level at a constant voltage value, the CPU 80 uses the 8-bit digital binary code signal at the constant voltage value as the first data. Stored in the internal memory.
[0053]
  Further, as shown in FIG. 3, the CPU 80 increases the variable DC voltage supplied to the negative pole 232 of the second comparator 23 until the second FF output signal changes from the LOW level to the HIGH level. In FIG. 3, this voltage is temporarily displayed as 1.4V. Then, an 8-bit digital binary code signal at a voltage of 1.4 V is stored in the memory inside the CPU 80 as second data.
[0054]
  The CPU 80 calculates a balance voltage value by adding a constant voltage value of the first data to the intermediate voltage value of the first data and the second data as the measurement result. Then, an 8-bit digital binary code signal corresponding to the balance voltage value is output to the D / A conversion circuit 60.
[0055]
  If the balance voltage value is 1.3 V, the timing chart is as shown in FIG. That is, the time between timing t2 and timing t1 is equal to the time between timing t1 and timing t3. This state is reached, and the circuit becomes in a detectable state. When any of the ports 82 and 83 is kept at the LOW level, the CPU 80 determines that no object is present in any detection area of both electrodes.
[0056]
  Next, a case where an object approaches or contacts only within the detection region of the first detection electrode 6 and the amount of charge of the first detection electrode 6 increases will be described with reference to FIG.
[0057]
  In the first integrated waveform signal P2, since the capacitance between the first detection electrode 6 and the ground electrode 8 increases, the slope of the falling edge of the first integrated waveform signal P2 becomes smaller. Accordingly, the timing t1 of the first integrated waveform signal P2 is delayed from the timing t3 of the rising edge of the second data signal P8.
[0058]
  For this reason, at the rising edge t1 of the clock signal P6, the second data signal P8 is at the HIGH level, so the second FF output signal P10 changes from the LOW level to the HIGH level. On the other hand, since the first data signal P7 remains at the HIGH level, the first FF output signal P9 maintains the LOW level.
[0059]
  The CPU 80 that has monitored the signal levels of the ports 82 and 83, when the signal level of each port becomes the LOW level and the HIGH level, on the condition that the state continues for 0.2 seconds or more. A detection signal is output from the port 94.
[0060]
  Note that, when the timing t1 is delayed from the timing t3, the balance object shown in FIG. 4 is adjusted in a state where a stationary object having a predetermined charge is present in the detection region of the detection electrode 7, Thereafter, this also occurs when the object is separated from or separated from the detection region of the detection electrode 7. Therefore, the first detection signal when the signal level of the ports 82 and 83 becomes the LOW level and the HIGH level is output even when the object is separated from the detection region of the detection electrode 7 or separated. Is done.
[0061]
  Next, a case where an object approaches or contacts only within the detection region of the second detection electrode 7 and the amount of charge of the second detection electrode 7 increases will be described with reference to FIG.
[0062]
  In the second integrated waveform signal P3, since the capacitance between the second detection electrode 7 and the ground electrode 9 increases, the slope of the falling edge of the second integrated waveform signal P3 becomes smaller. Accordingly, the timing t2 of the second integrated waveform signal P3 is delayed from the timing t1 of the falling edge of the first integrated waveform signal P2.
[0063]
  Therefore, at the rising edge t1 of the clock signal P6, the first data signal P7 is at the LOW level, so the first FF output signal P9 changes from the LOW level to the HIGH level. Meanwhile, the second data signal P8Remains at the LOW level, the second FF output signal P10 maintains the LOW level.
[0064]
  The CPU 80 that has monitored the signal levels of the ports 82 and 83, when the signal level of each port becomes the HIGH level and the LOW level, on the condition that the state continues for 0.2 seconds or more. A detection signal is output from the port 94.
[0065]
  When the timing t2 is delayed from the timing t1, the balance object shown in FIG. 4 is adjusted in a state where a stationary object having a predetermined charge is present in the detection region of the detection electrode 6. Thereafter, this also occurs when the object is separated from or separated from the detection region of the detection electrode 6. Therefore, the second detection signal when the signal level of the ports 82 and 83 becomes the HIGH level and the LOW level is also output when the object is separated from the detection region of the detection electrode 6 or separated. Is done.
[0066]
  FIG. 8 is a timing chart showing in more detail the pulse signal P1 and the second FF output signal of the timing chart when an object approaches or contacts only within the detection region of the first detection electrode 6 shown in FIG. ing.
[0067]
  When an object approaches the detection area of the first detection electrode 6, as described above, the second FF output signal changes from a stable LOW level (non-detection signal) to a stable HIGH level (effective detection signal). Actually, as shown in FIG. 8, an invalid detection signal that alternately repeats the LOW level or the HIGH level is output between the non-detection signal and the valid detection signal for a short time.
[0068]
  This invalid detection signal is generated when the timing t1 and the timing t3 of the rising edge of the second data signal substantially coincide with each other, and the valid detection signal is formed when the timing t1 is completely delayed from the timing t3.
[0069]
  This invalid detection signal is also generated when the temperature, humidity, or the like around the detection electrode changes with the passage of time after the automatic balance adjustment. That is, the charge amount of one detection electrode gradually increases or decreases than the charge amount of the other detection electrode, so that the time between the timing t2 and the timing t1, The time between t1 and timing t3 is different, and an invalid detection signal is formed.
[0070]
  However, since the change in the charge amount of the detection electrode occurs with changes in temperature or the like, it gradually changes over time. Accordingly, the duration of the invalid detection signal caused by a change in temperature or the like is extremely longer than the change in the amount of charge caused by the approach or contact of an object in the detection region. As will be described later, when the time during which the invalidity detection signal is output is longer than a predetermined time (2 seconds), the CPU 80 executes the automatic balance adjustment.
[0071]
  Next, automatic sensitivity adjustment will be described. When external noise enters through the detection electrode or when noise enters the circuit from the power supply unit or the like, fluctuations (jitter) occur at timings t1, t2, and t3, and the first FF output signal P9 and the second FF output signal. Any of P10 becomes the above-mentioned invalidity detection signal and causes chattering.
[0072]
  This chattering is caused by relatively weak noise when the time between the timing t2 and the timing t1 and the time between the timing t1 and the timing t3 are short, that is, when the detection sensitivity is high.
[0073]
  Automatic sensitivity adjustment eliminates the influence of noise by adjusting the time between each timing. FIG. 7 shows a timing chart in a state where the one-step detection sensitivity is lowered by the delay circuit 50 from the most sensitive state shown in FIG. 7 is the time between the timing t2 and the timing t1 in FIG. 7 and the time between the timing t1 and the timing t3 in FIG. 7 than the time between the timing t2 and the timing t3 in FIG. It is getting longer.
[0074]
  Specifically, when both the first FF output signal P9 and the second FF output signal P10 are the above-described invalid detection signals, the CPU 80 determines that accurate detection is impossible due to noise, Perform automatic sensitivity adjustment. That is, by controlling the delay circuit 50, the time between the timing t2 and the timing t1 and the time between the timing t1 and the timing t3 are increased stepwise (four steps), and chattering no longer occurs. Stop automatic sensitivity adjustment. By this automatic sensitivity adjustment, a decrease in detection sensitivity can be minimized.
[0075]
  Next, a flowchart of the CPU 80 of the present embodiment will be described for each step with reference to FIG. By turning on the power of this circuit (S1) and not outputting direct current from the ports 84 and 85 to the delay circuit 50 that performs automatic sensitivity adjustment, the detection sensitivity is set to the highest state (S2).
[0076]
  The CPU 80 outputs an 8-bit digital binary data signal from each of the ports 86 to 93, and executes the automatic balance adjustment (S3). After completion of the automatic balance adjustment, it is determined whether the first FF output signal P9 of the port 82 is HIGH level and / or whether the second FF output signal P10 of the port 83 is HIGH level.
[0077]
  If it is determined that the HIGH level signal is a valid detection signal (S6), it is determined whether the duration of the valid detection signal is 0.2 seconds or more (S7). If the duration of the valid detection signal is 0.2 seconds or longer, the first detection signal or the second detection signal is output from the port 94 for 1 second (S7). If it is less than 0.2 seconds, the process returns to S4.
[0078]
  When the duration of the valid detection signal is further continued and becomes 10 seconds or more, automatic balance adjustment is executed (S9). For example, when the object is stationary for 10 seconds or longer in the detection region of any of the detection electrodes, the influence of the increase in the charge amount of the detection electrode can be eliminated by performing automatic balance adjustment again. Therefore, the balance of capacitance between the detection electrode and other detection electrodes is restored. Therefore, after the automatic balance adjustment is executed, the process returns to S4, and even when another object enters the detection area in the state where the stationary object exists, the other object can be detected.
[0079]
  If it is determined in S5 that the HIGH level signal is an invalid detection signal, it is then determined whether the invalid detection signal is generated in either of the ports 82 and 83 (S10). When invalid detection signals are generated in both ports 82 and 83, automatic sensitivity adjustment is executed, the sensitivity level of the four levels is lowered by one level (S11), and the process returns to S4.
[0080]
  When an invalidity detection signal is generated in one of the ports 82 and 83, it is determined whether the duration of the invalidity detection signal is 2 seconds or more (S12). If it is 2 seconds or longer, automatic balance adjustment is executed (S13), and then the process returns to S4. If it is less than 2 seconds, it is determined that it is not necessary to execute the automatic balance adjustment, and the process returns to S4 without executing the automatic balance adjustment.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a capacitance sensor circuit according to an embodiment of the present invention.
FIG. 2 is a timing chart showing the operation of the capacitance sensor circuit of FIG. 1, showing a state immediately after the operation of the circuit.
FIG. 3 is a timing chart showing the operation of the capacitance sensor circuit of FIG. 1, showing an operating state during automatic balance adjustment;
4 is a timing chart showing the operation of the capacitance sensor circuit of FIG. 1, and shows a state in which automatic balance adjustment is completed. FIG.
5 is a timing chart showing the operation of the capacitance sensor circuit of FIG. 1, showing a state in which the charge amount of the first detection electrode is increased.
6 is a timing chart showing the operation of the capacitance sensor circuit of FIG. 1, showing a state in which the charge amount of the second detection electrode is increased.
7 is a timing chart showing the operation of the capacitance sensor circuit of FIG. 1, and shows a state in which detection sensitivity is lowered by automatic sensitivity adjustment.
8 is a timing chart showing the operation of the capacitance sensor circuit of FIG. 1, showing an invalid detection signal and a valid detection signal of the first FF output signal.
9 is a flowchart showing the operation of a CPU 80 of the capacitance sensor circuit of FIG.
FIG. 10 is a block diagram of a conventional capacitance sensor circuit.
[Explanation of symbols]
1, 2 input terminals
3, 4 Amplification resistor
5 transformer
6 First detection electrode
7 Second sensing electrode
8, 9 Ground electrode
10 Surge protection circuit
11, 12 resistance
13, 14 ESD
20 Comparison circuit
22 First comparator
23 Second comparator
30 Waveform shaping circuit
31 First knot circuit
32 Second knot circuit
33 Third knot circuit
40 Flip-flop circuit
41 First flip-flop circuit
42 Second flip-flop circuit
50 Automatic sensitivity adjustment circuit
60 D / A converter circuit
80 CPU
120 Stabilized power supply circuit
130 Reset circuit
140 LED display circuit
150 CPU clock

Claims (13)

A pulse signal generation circuit for generating a pulse signal;
Comparing means for forming a clock signal, a first data signal and a second data signal based on a change in capacitance of at least two detection electrodes, the pulse signal;
Automatic balance adjustment means for controlling the time between the timing t2 of the first data signal and the timing t1 of the clock signal and the time between the timing t1 of the clock signal and the timing t3 of the second data signal;
Determining means for comparing the clock signal with the first data signal and comparing the clock signal with the second data signal;
The comparison means is connected to a first detection electrode and forms the clock signal, the second comparator is connected to a second detection electrode and forms the first data signal, and the first comparator A capacitance sensor circuit comprising a delay circuit that delays a data signal to form the second data signal .   The automatic balancing means controls the time between the timing t2 of the first data signal and the timing t1 of the clock signal and the time between the timing t1 of the clock signal and the timing t3 of the second data signal equally. Item 4. The capacitance sensor circuit according to Item 1. The automatic balance adjustment means, the electrostatic capacitance sensor circuit of claim 1 wherein the variable control of the comparison voltage of the second comparator. The capacitance sensor circuit according to claim 1 , wherein the automatic balance adjusting unit is a D / A conversion circuit operated by a CPU.   The determination means compares the clock signal with the first data signal, and compares the clock signal with the second data signal, and determines that one of them is in an invalid detection state for a predetermined time or more. 2. The capacitance sensor circuit according to claim 1, wherein the automatic balance adjusting means is operated.   The determination means compares the clock signal and the first data signal, and, as a result of comparing the clock signal and the second data signal, determines that one of them is in a valid detection state, The capacitance sensor circuit according to claim 1, which outputs a detection signal.   The determination means outputs a detection signal, compares the clock signal with the first data signal, and compares the clock signal with the second data signal. 2. The capacitance sensor circuit according to claim 1, wherein when it is determined that the state is in a state, the automatic balance adjusting means is operated.   The determination means includes a first flip-flop circuit that compares the clock signal with the first data signal, a second flip-flop circuit that compares the clock signal with the second data signal, the first flip-flop circuit, 2. The capacitance sensor circuit according to claim 1, further comprising a CPU for determining an output signal of the second flip-flop circuit.   The capacitance sensor circuit according to claim 1, wherein the delay circuit performs automatic sensitivity adjustment by variably controlling a delay time of the second data signal. The determination means compares the clock signal with the first data signal, and compares the clock signal with the second data signal, and determines that both are in an invalid detection state. capacitive sensor circuit of claim 1 wherein lowering the detection sensitivity by operating the delay circuit.   2. The capacitance sensor circuit according to claim 1, wherein the delay circuit comprises an integration circuit having a plurality of time constants selected by a CPU.   The capacitance sensor circuit according to claim 1, wherein the determination unit operates the automatic balance adjustment unit immediately after the capacitance sensor circuit is operated.   2. The capacitance sensor circuit according to claim 1, wherein immediately after the capacitance sensor circuit is activated, the determination unit activates the delay circuit and sets the detection sensitivity to the highest state.

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