JPH08195477A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH08195477A
JPH08195477A JP7003669A JP366995A JPH08195477A JP H08195477 A JPH08195477 A JP H08195477A JP 7003669 A JP7003669 A JP 7003669A JP 366995 A JP366995 A JP 366995A JP H08195477 A JPH08195477 A JP H08195477A
Authority
JP
Japan
Prior art keywords
electrode
insulating film
region
surge voltage
diode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7003669A
Other languages
Japanese (ja)
Inventor
Makoto Yamato
誠 大和
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP7003669A priority Critical patent/JPH08195477A/en
Publication of JPH08195477A publication Critical patent/JPH08195477A/en
Pending legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)
  • Electronic Switches (AREA)

Abstract

PURPOSE: To prevent insulation breakage from occurring when a high surge voltage is applied to the electrode on a thin insulating film by arranging the semiconductor device such that the diode made right under it is biased reversely to the region right under the wiring of a semiconductor substrate when surge voltage is applied to the electrode. CONSTITUTION: An n layer 4 which has a dimension larger than the dimension of the electrode 3 on an insulating film 2 in any direction is made on the surface layer in the region where a pad electrode 3 on the surface is made and there is a fear of positive surge voltage adding, of the p-type silicon substrate 1 of an integrated circuit. Especially, a diode 11, which has a region pn junction including the region opposed to the electrode 3, is made within the silicon substrate 1 right under the insulating film 2. And, when surge voltage is applied to the electrode 3, this diode 11 is reversely biased. Hereby, the strength of the internal electric field of the insulating film 2 drops, and insulation breakage can be prevented from occurring in the insulating film 2.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体基板上に絶縁膜
を介して電極が設けられる半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which electrodes are provided on a semiconductor substrate via an insulating film.

【0002】[0002]

【従来の技術】半導体集積回路においては、集積された
素子と接続される電極が半導体基板上に絶縁膜を介して
設けられる。図3はそのようなAl配線と外部回路との
接続に用いられるAlパッド部を示し、シリコン基板1
の上に酸化膜などの絶縁膜2を介して設けられる配線の
一部にパッド電極3が形成されている。
2. Description of the Related Art In a semiconductor integrated circuit, an electrode connected to an integrated element is provided on a semiconductor substrate via an insulating film. FIG. 3 shows an Al pad portion used for connecting such an Al wiring and an external circuit.
A pad electrode 3 is formed on a part of the wiring provided on the above via an insulating film 2 such as an oxide film.

【0003】[0003]

【発明が解決しようとする課題】集積回路の微細化に伴
い、表面上の絶縁膜2の膜厚は薄いことが要求される。
このため、絶縁膜の耐圧が低下し、電極3に高いサージ
電圧が印加されたとき、絶縁破壊が起こることがある。
この破壊を防止するために配線の下の絶縁膜を局部的に
厚くすることが考えられるが、そのためにはプロセスの
追加が必要となる。
With the miniaturization of integrated circuits, the insulating film 2 on the surface is required to be thin.
For this reason, the breakdown voltage of the insulating film is lowered, and when a high surge voltage is applied to the electrode 3, dielectric breakdown may occur.
In order to prevent this destruction, it is conceivable to locally thicken the insulating film under the wiring, but this requires an additional process.

【0004】本発明の目的は、上述の問題を解決し、薄
い絶縁膜上の電極に高いサージ電圧が印加されたときに
絶縁破壊の起こるのが防止される半導体装置を提供する
ことにある。
An object of the present invention is to solve the above problems and to provide a semiconductor device in which dielectric breakdown is prevented from occurring when a high surge voltage is applied to an electrode on a thin insulating film.

【0005】[0005]

【課題を解決するための手段】上記の目的を達成するた
めに本発明は、半導体基板上に絶縁膜を介して設けられ
た電極を有する半導体装置において、絶縁膜の直下の半
導体基板内に電極に対向する領域を包含する領域のPN
接合を有するダイオードが形成され、前記電極にサージ
電圧が印加されたときにこのダイオードが逆バイアスさ
れるものとする。PN接合が第一導電形の半導体基板と
この基板の表面層に形成された第二導電形の領域との間
に存在するか、あるいは第一導電形の半導体基板とこの
基板の表面層に形成された第二導電形の領域との間およ
びこの第二導電形の領域とこの領域の表面層に形成され
た第一導電形の領域との間の双方に存在することが有効
である。
In order to achieve the above object, the present invention provides a semiconductor device having an electrode provided on a semiconductor substrate via an insulating film, in which the electrode is provided in the semiconductor substrate immediately below the insulating film. Of the area including the area facing the
It is assumed that a diode having a junction is formed and that the diode is reverse biased when a surge voltage is applied to the electrode. A PN junction exists between the semiconductor substrate of the first conductivity type and the region of the second conductivity type formed on the surface layer of the substrate, or is formed on the semiconductor substrate of the first conductivity type and the surface layer of the substrate. Between the second conductivity type region and the second conductivity type region and between the second conductivity type region and the first conductivity type region formed in the surface layer of this region.

【0006】[0006]

【作用】半導体基板上に絶縁膜を介して設けられた電極
にサージ電圧が印加されたとき、その直下に形成された
ダイオードが逆バイアスされることにより、絶縁膜の内
部の電界強度が低下し、絶縁膜の絶縁破壊が起こること
が防止される。このダイオードのPN接合が第一導電形
基板とその表面層に形成された第二導電形の領域との間
にのみ存在するときは、電極に印加されるサージ電圧の
極性が限定されるが、さらにその第二導電形の領域の表
面層に第一導電形の領域が形成されてPNPあるいはN
PN構造によって逆直列接続される二つのダイオードが
存在するときは、サージ電圧にいずれの極性の電圧が印
加されても絶縁膜が保護される。
When the surge voltage is applied to the electrode provided on the semiconductor substrate via the insulating film, the diode formed immediately below is reverse-biased, so that the electric field strength inside the insulating film is lowered. The dielectric breakdown of the insulating film is prevented. When the PN junction of this diode exists only between the substrate of the first conductivity type and the region of the second conductivity type formed in the surface layer thereof, the polarity of the surge voltage applied to the electrodes is limited, Further, a region of the first conductivity type is formed on the surface layer of the region of the second conductivity type to form PNP or N
When there are two diodes connected in anti-series by the PN structure, the insulating film is protected regardless of the polarity of the surge voltage.

【0007】[0007]

【実施例】以下、図3を含めて共通の部分に同一の符号
を付した図を引用して本発明の実施例について述べる。
図1に示した実施例では、集積回路のp形シリコン基板
1の正のサージ電圧の加わるおそれのある表面上のパッ
ド電極3の形成される領域の表面層に、いずれの方向で
も絶縁膜2の上の電極3の寸法より大きい寸法をもつn
層4が形成されている。このn層4は、集積回路の基板
1にn層の拡散工程が施されるときに同時に形成してお
くか、あるいはn形多結晶Si層堆積工程が施されると
きに同時に形成しておく。ただし、このn層は基板1内
の他層と絶縁されているか、あるいはフローティングさ
れていることが必要である。図に記入されているよう
に、n層4とP基板1とによって生ずるダイオード11
に対して、電極3に印加される正のサージ電圧は逆バイ
アスになる。ダイオードの逆耐圧により絶縁膜2の中の
電界強度は低下し、サージ電圧によって絶縁破壊が生ず
ることがない。基板1がn形で電極3に加わるサージ電
圧が負の場合には、電極の寸法より大きいp層を形成す
れば同じ効果を生ずる。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to the drawings including the same parts in FIG.
In the embodiment shown in FIG. 1, the insulating film 2 is formed in any direction on the surface layer of the region where the pad electrode 3 is formed on the surface of the p-type silicon substrate 1 of the integrated circuit where a positive surge voltage may be applied. With a size larger than the size of the electrode 3 on the
Layer 4 has been formed. The n layer 4 is formed at the same time when the substrate 1 of the integrated circuit is subjected to the diffusion process of the n layer, or at the same time when the n type polycrystalline Si layer deposition process is performed. . However, it is necessary that the n layer is insulated from other layers in the substrate 1 or is floating. As shown in the figure, the diode 11 produced by the n-layer 4 and the P-substrate 1
On the other hand, the positive surge voltage applied to the electrode 3 has a reverse bias. The reverse breakdown voltage of the diode lowers the electric field strength in the insulating film 2 and the surge voltage does not cause dielectric breakdown. When the substrate 1 is n-type and the surge voltage applied to the electrode 3 is negative, the same effect is produced by forming a p-layer larger than the size of the electrode.

【0008】これに対し図2には、基板の導電形あるい
は電極への印加電圧の極性の如何にかかわらず有効であ
る本発明の実施例を示す。この場合は、集積回路のp形
シリコン基板1の表面層にn層4が形成され、さらにそ
のn層4の表面層にp層5が形成されている。n層4、
p層5は、いずれも集積回路の製造のための工程中の、
拡散工程あるいは多結晶Si層堆積工程と同時に形成し
たものである。p層5の寸法は、いずれの方向でも絶縁
膜2上の電極3の寸法より大きく、n層4はp層5を囲
んでおり、そのp層5の下の深さは、電極3に加わるサ
ージ電圧の高さとp層の抵抗率から決められる。この構
造では、図に記入されているように逆直列接続の二つの
ダイオード11、12が生ずる。電極3に正のサージ電
圧が印加されたときにはダイオード11が逆方向、ダイ
オード12が順方向になり、負のサージ電圧が印加され
たときにはダイオード12が逆方向、ダイオード11が
順方向になる。従ってどのような極性のサージ電圧が加
わっても絶縁膜2の絶縁破壊は起こらない。集積回路の
基板がn形のときは、その表面層にp層、さらにその中
にn層を形成することにより、同様に逆直列接続の二つ
のダイオードを得ることができ、同様の効果を生ずる。
On the other hand, FIG. 2 shows an embodiment of the present invention which is effective regardless of the conductivity type of the substrate or the polarity of the voltage applied to the electrodes. In this case, the n layer 4 is formed on the surface layer of the p-type silicon substrate 1 of the integrated circuit, and the p layer 5 is further formed on the surface layer of the n layer 4. n layer 4,
Each of the p-layers 5 is in the process for manufacturing an integrated circuit,
It is formed at the same time as the diffusion step or the polycrystalline Si layer deposition step. The dimension of the p layer 5 is larger than the dimension of the electrode 3 on the insulating film 2 in any direction, the n layer 4 surrounds the p layer 5, and the depth under the p layer 5 is added to the electrode 3. It is determined from the height of the surge voltage and the resistivity of the p layer. In this structure, two diodes 11 and 12 are connected in anti-series as shown in the figure. When a positive surge voltage is applied to the electrode 3, the diode 11 is in the reverse direction and the diode 12 is in the forward direction, and when a negative surge voltage is applied, the diode 12 is in the reverse direction and the diode 11 is in the forward direction. Therefore, dielectric breakdown of the insulating film 2 does not occur even if a surge voltage of any polarity is applied. When the substrate of the integrated circuit is n-type, by forming the p-layer on the surface layer and the n-layer in the surface layer, two diodes in anti-series connection can be similarly obtained, and the same effect is produced. .

【0009】[0009]

【発明の効果】本発明によれば、半導体基板の配線直下
の領域に電極へサージ電圧が印加されたとき、その電圧
が逆バイアスとなるようなダイオードを形成することに
より、電極直下の絶縁膜の耐圧が50V以上向上するの
で、絶縁膜を薄くでき、特に微細化のため表面絶縁膜の
膜厚を薄くする集積回路装置のような半導体装置に対し
て極めて有効である。また、このダイオードは半導体装
置の製造工程中に工程を追加することなく形成できる利
点をもつ。
According to the present invention, when a surge voltage is applied to an electrode in a region immediately below a wiring of a semiconductor substrate, a diode is formed so that the voltage becomes a reverse bias, whereby an insulating film directly below the electrode is formed. Since the withstand voltage of 50 V is improved by 50 V or more, the insulating film can be made thin, and is particularly effective for a semiconductor device such as an integrated circuit device in which the surface insulating film is thinned for miniaturization. Further, this diode has an advantage that it can be formed without adding steps during the manufacturing process of the semiconductor device.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の半導体装置のパッド電極部
断面図
FIG. 1 is a sectional view of a pad electrode portion of a semiconductor device according to an embodiment of the present invention.

【図2】本発明の別の実施例の半導体装置のパッド電極
部断面図
FIG. 2 is a sectional view of a pad electrode portion of a semiconductor device according to another embodiment of the present invention.

【図3】従来の半導体装置のパッド電極部断面図FIG. 3 is a sectional view of a pad electrode portion of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 p形シリコン基板 2 絶縁膜 3 パッド電極 4 n層 5 p層 1 p-type silicon substrate 2 insulating film 3 pad electrode 4 n layer 5 p layer

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】半導体基板上に絶縁膜を介して設けられた
電極を有するものにおいて、絶縁膜の直下の半導体基板
内に電極に対向する領域を包含する領域のPN接合を有
するダイオードが形成され、前記電極にサージ電圧が印
加されたときにこのダイオードが逆バイアスされること
を特徴とする半導体装置。
1. A diode having an electrode provided on a semiconductor substrate via an insulating film, wherein a diode having a PN junction in a region including a region facing the electrode is formed in the semiconductor substrate immediately below the insulating film. A semiconductor device in which the diode is reverse-biased when a surge voltage is applied to the electrodes.
【請求項2】PN接合が第一導電形の半導体基板とこの
基板の表面層に形成された第二導電形の領域との間に存
在する請求項1記載の半導体装置。
2. The semiconductor device according to claim 1, wherein the PN junction exists between the semiconductor substrate of the first conductivity type and the region of the second conductivity type formed in the surface layer of the substrate.
【請求項3】PN接合が第一導電形の半導体基板とこの
基板の表面層に形成された第二導電形の領域との間およ
びこの第二導電形の領域とこの領域の表面層に形成され
た第一導電形の領域との間の双方に存在する請求項1記
載の半導体装置。
3. A PN junction is formed between a semiconductor substrate of the first conductivity type and a region of the second conductivity type formed in the surface layer of the substrate, and in the region of the second conductivity type and the surface layer of this region. 2. The semiconductor device according to claim 1, wherein the semiconductor device exists in both of the region of the first conductivity type and the region of the first conductivity type.
JP7003669A 1995-01-13 1995-01-13 Semiconductor device Pending JPH08195477A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7003669A JPH08195477A (en) 1995-01-13 1995-01-13 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7003669A JPH08195477A (en) 1995-01-13 1995-01-13 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH08195477A true JPH08195477A (en) 1996-07-30

Family

ID=11563846

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7003669A Pending JPH08195477A (en) 1995-01-13 1995-01-13 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH08195477A (en)

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