JPH08195397A - Semiconductor device with bump and manufacture thereof - Google Patents

Semiconductor device with bump and manufacture thereof

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Publication number
JPH08195397A
JPH08195397A JP609895A JP609895A JPH08195397A JP H08195397 A JPH08195397 A JP H08195397A JP 609895 A JP609895 A JP 609895A JP 609895 A JP609895 A JP 609895A JP H08195397 A JPH08195397 A JP H08195397A
Authority
JP
Japan
Prior art keywords
electrode
semiconductor device
bump
bumps
composite
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP609895A
Other languages
Japanese (ja)
Other versions
JP3261912B2 (en
Inventor
Akira Amano
彰 天野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
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Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP609895A priority Critical patent/JP3261912B2/en
Priority to SE9600180A priority patent/SE9600180L/en
Publication of JPH08195397A publication Critical patent/JPH08195397A/en
Application granted granted Critical
Publication of JP3261912B2 publication Critical patent/JP3261912B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
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    • H01L24/72—Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/13001—Core members of the bump connector
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    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
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  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
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  • Wire Bonding (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thyristors (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE: To manufacture a bump applicable to an electrode of large area in a simple process, by providing, on an electrode part, a protruding body which is made of a substance having a small elastic modulus and a composite bump which is made by covering the protruding body with a metal film having a large elastic modulus and a proximate elastic coefficient. CONSTITUTION: In an oxide film on a silicon substrate 2 having a base diffusion region 3 and an emitter diffusion region 4 formed therein, a base aperture 5 and an emitter aperture 6 are opened. An Al-Si alloy is deposited thereon and photo-etching is carried out to form an Al electrode 7. Then, on the surface of the Al electrode 7 for forming a bump thereon, polyimide resin is accurately ejected and dropped from a nozzle and heat treatment is carried out to form a partly spherical protruding body 18. Subsequently, another Al-Si alloy is deposited and a second Al electrode 17 is photo-etched to form a composite bump 20. Finally, a nitride film 11 is deposited and patterned to protect a flat part of the second Al electrode 17.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、いわゆるバンプ電極等
突起状の電極を有するバンプ付き半導体装置およびその
製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bumped semiconductor device having a bump-like electrode such as a so-called bump electrode and a method for manufacturing the same.

【０００２】[0002]

【従来の技術】半導体装置の多数の電極の高信頼性の接
続のため、突起状のいわゆるバンプ電極を有する半導体
装置が量産されている。従来のバンプ付き半導体装置の
一例として、ｎ型基板を用いたｎｐｎトランジスタに半
田バンプを形成した例の平面図を図１３（ａ）に示す。
半導体チップ１にフォトエッチング技術を用いたパター
ン形成、酸化、不純物拡散等の工程により、トランジス
タの構造が作り込まれているものとする。３はベース拡
散領域、４はエミッタ拡散領域であり、その上の酸化膜
に電極接続のために設けられたベース開口部５、エミッ
タ開口部６が破線で示されている。２１はコレクタの電
極接続のための開口部である。そして、これらの開口部
上にＡｌ−Ｓｉ合金を被着、パターン形成したＡｌ電極
７が設けられ、チップ１上の周辺部に設けられたパッド
に接続されている。各パッド上には他の基板等に接続す
るため、球の一部を切り取ったような部分球状のベース
バンプ１３、エミッタバンプ１４、コレクタバンプ２２
が形成されている。バンプとしては直径０．２ｍｍ（面
積は約０．０３ｍｍ2 ）、高さ２０μｍ程度の小さいバ
ンプが標準的である。コレクタ開口部２１およびコレク
タバンプ２２が二つ設けられているのは、構造的、熱的
なバランスを考慮したためであり、場合によっては一つ
でもよい。2. Description of the Related Art Semiconductor devices having a so-called bump-shaped bump are mass-produced for highly reliable connection of a large number of electrodes of the semiconductor device. As an example of a conventional semiconductor device with bumps, a plan view of an example in which solder bumps are formed on an npn transistor using an n-type substrate is shown in FIG.
It is assumed that the structure of the transistor is built in the semiconductor chip 1 by steps such as pattern formation using a photoetching technique, oxidation, and impurity diffusion. Reference numeral 3 is a base diffusion region, 4 is an emitter diffusion region, and a base opening 5 and an emitter opening 6 provided for electrode connection in an oxide film thereon are shown by broken lines. Reference numeral 21 is an opening for connecting the collector electrode. Then, an Al-Si alloy coated and patterned Al electrode 7 is provided on these openings and is connected to a pad provided on the peripheral portion of the chip 1. In order to connect to another substrate or the like on each pad, a partial spherical base bump 13, an emitter bump 14, and a collector bump 22 are formed by cutting a part of a sphere.
Are formed. As the bump, a small bump having a diameter of 0.2 mm (area is about 0.03 mm 2 ) and a height of about 20 μm is standard. The reason why two collector openings 21 and two collector bumps 22 are provided is to consider the structural and thermal balance, and in some cases only one may be provided.

【０００３】図１３（ｂ）は、図１３（ａ）の半導体チ
ップ１のＡ−Ａ線における断面図である。ｎ型半導基板
２の表面層にｐ型のベース拡散領域３と、その表面層に
ｎ型のエミッタ拡散領域４が形成されている。半導体基
板２の表面上は、酸化膜８が覆っており、その酸化膜８
に開けられたベース開口部５、エミッタ開口部６を通じ
てＡｌ電極７が接触している。Ａｌ電極７の上に、窒化
膜からなる表面保護膜１１が覆っておりその保護膜１１
に開けられたベースバンプ用開口部１５、エミッタバン
プ用開口部１６に下地金属膜９を介して半田のベースバ
ンプ１３、エミッタバンプ１４が形成されている。FIG. 13B is a sectional view taken along line AA of the semiconductor chip 1 of FIG. A p-type base diffusion region 3 is formed on the surface layer of the n-type semiconductor substrate 2, and an n-type emitter diffusion region 4 is formed on the surface layer. The oxide film 8 covers the surface of the semiconductor substrate 2, and the oxide film 8
The Al electrode 7 is in contact with the base opening 5 and the emitter opening 6 which are opened. The Al electrode 7 is covered with a surface protective film 11 made of a nitride film.
Solder base bumps 13 and emitter bumps 14 are formed in the base bump opening 15 and the emitter bump opening 16 opened through the base metal film 9.

【０００４】図１４（ａ）〜（ｄ）は図１３のトランジ
スタの製造方法を説明するための工程順の断面図であ
る。この図に基づき、製造工程を説明する。ｎ型基板２
にフォトエッチング技術を用いたパターン形成、酸化、
不純物拡散等の工程により、トランジスタの接合構造が
作り込まれるまでの工程は良く知られているので省略す
る。そのような半導体基板上の酸化膜８に、フォトエッ
チング技術により、ベース開口部５、エミッタ開口部６
をあける、次に、Ａｌ−Ｓｉ合金膜を全面にスパッタリ
ング法により堆積し、所定の形状にパターン形成し、Ａ
ｌ電極７を設ける。その上全面をＣＶＤ法により耐水、
耐イオン透過性などのシール性の優れた窒化シリコン膜
からなる表面保護膜１１で覆い、その表面保護膜１１
に、フォトエッチング技術によりベースバンプ用開口部
１５、エミッタバンプ用開口部１６を設ける〔図１４
（ａ）〕。14A to 14D are cross-sectional views in the order of steps for explaining a method of manufacturing the transistor of FIG. The manufacturing process will be described with reference to this drawing. n-type substrate 2
Pattern formation using photo-etching technology, oxidation,
Since the steps until the junction structure of the transistor is formed by the steps such as impurity diffusion are well known, the description thereof will be omitted. A base opening 5 and an emitter opening 6 are formed on the oxide film 8 on the semiconductor substrate by a photoetching technique.
Then, an Al-Si alloy film is deposited on the entire surface by a sputtering method to form a pattern in a predetermined shape.
The l electrode 7 is provided. Besides, the entire surface is water resistant by the CVD method,
The surface protection film 11 is covered with a surface protection film 11 made of a silicon nitride film having excellent sealing property such as resistance to ion permeation,
The base bump opening 15 and the emitter bump opening 16 are provided by photoetching technique in FIG.
(A)].

【０００５】次に、バンプ下地金属９をスパッタリング
法により全面に形成する〔同図（ｂ）〕。バンプ下地金
属９としては、Ａｌ電極７と密着性のよい、Ｃｒのコン
タクト層、柔らかく延性のあるＣｕのスペーサ層、半田
中のＳｎの拡散を防止するＮｉのバリア層の三層を連続
的にスパッタリング法で被着した。或いは蒸着法によっ
て被着しても良い。コンタクト層としては、上記のＣｒ
の他に、Ｔｉ、Ｔｉ−Ｗ、Ｗ等を、また、スペーサ層と
しては、上記Ｃｕの他にＰｄ、Ａｕ、Ａｇ等を用いるこ
ともある。半田でバンプ電極を作る時には、Ｓｎバリア
層としてＮｉのスパッタ層を加えて三層とするが、金を
バンプ電極とするときには、Ｎｉのバリア層は不要であ
る。Next, a bump base metal 9 is formed on the entire surface by a sputtering method [FIG. As the bump base metal 9, three layers of a Cr contact layer, which has good adhesion to the Al electrode 7, a soft and ductile Cu spacer layer, and a Ni barrier layer which prevents Sn from diffusing in the solder, are continuously formed. It was deposited by the sputtering method. Alternatively, it may be deposited by a vapor deposition method. As the contact layer, the above-mentioned Cr
In addition, Ti, Ti-W, W and the like may be used, and as the spacer layer, Pd, Au, Ag and the like may be used in addition to the above Cu. When a bump electrode is made of solder, a Ni sputter layer is added as an Sn barrier layer to form three layers, but when gold is used as the bump electrode, the Ni barrier layer is unnecessary.

【０００６】その後、フォトレジスト１０を塗布しバン
プ電極形成用にパターニングし、それをマスクにして下
地金属９上に電解メッキでバンプ金属１２を形成する
〔同図（ｃ）〕。この時、同様にパターニングしたフォ
トレジスト１０をマスクにした蒸着法を行い、フォトレ
ジスト１０およびその上の金属膜を除去するリフトオフ
法を使用することもできる。After that, a photoresist 10 is applied and patterned for forming bump electrodes, and the bump metal 12 is formed on the base metal 9 by electroplating using the same as a mask [FIG. 2 (c)]. At this time, it is also possible to use a lift-off method of performing the vapor deposition method using the patterned photoresist 10 as a mask and removing the photoresist 10 and the metal film thereon.

【０００７】最後に、フォトレジスト１０を除去し、必
要に応じてフォトエッチング処理によりバンプ下地金属
９の不要部分をエッチング除去して、各々の電極を電気
的に分離し、フラックス処理を施し、トンネル炉で加熱
溶融するウェットバックと称する処理を施して、冷却時
に表面張力できれいな部分球状にベースバンプ１３およ
びエミッタバンプ１４の形状を整える〔同図（ｄ）〕。Finally, the photoresist 10 is removed, and an unnecessary portion of the bump underlying metal 9 is removed by photo-etching if necessary, each electrode is electrically separated, flux processing is performed, and tunneling is performed. A process called wet back, which heats and melts in a furnace, is performed, and the shapes of the base bumps 13 and the emitter bumps 14 are adjusted to a clean partial spherical shape by surface tension during cooling [(d) of the same figure].

【０００８】[0008]

【発明が解決しようとする課題】従来のバンプ付き半導
体装置においては、溶融接続を前提としているため、通
常、直径０．２ｍｍ（面積は約０．０３ｍｍ2 ）程度の
小さいバンプが標準的で、数ｍｍ×数ｍｍの大きな面積
上への形成は困難であった。また図１４（ａ）ないし
（ｄ）に示したように、各金属層がそれぞれ重要な役割
を担うため、多層構造として形成され、しかもその上に
電解メッキにより厚い金属層を形成した後、トンネル炉
で溶融して整形するなど、製造方法が非常に複雑で、工
数も多くかかる。Since the conventional semiconductor device with bumps is premised on fusion connection, a small bump having a diameter of about 0.2 mm (area is about 0.03 mm 2 ) is usually standard. It was difficult to form on a large area of several mm × several mm. In addition, as shown in FIGS. 14A to 14D, since each metal layer plays an important role, it is formed as a multi-layer structure, and a thick metal layer is formed on the metal layer by electrolytic plating. The manufacturing method is very complicated, such as melting and shaping in a furnace, and it takes a lot of man-hours.

【０００９】以上の問題に鑑み、本発明の目的は、大面
積の電極にも適用でき、簡単な工程で製造ができるバン
プを有する半導体装置を提供することにある。In view of the above problems, an object of the present invention is to provide a semiconductor device having bumps which can be applied to a large area electrode and can be manufactured by a simple process.

【００１０】[0010]

【課題を解決するための手段】上記の課題を解決するた
めに本発明の半導体装置は、弾性率の小さい物質からな
る凸状体と、弾性率が大きく、膨張係数の近い金属膜で
その凸状体を覆つた複合バンプを電極部に有するものと
する。一つの電極内に多数の複合バンプを設けることも
できる。In order to solve the above-mentioned problems, the semiconductor device of the present invention has a convex body made of a substance having a small elastic modulus and a convex metal film having a large elastic modulus and a close expansion coefficient. It is assumed that the electrode portion has a composite bump covering the strip. It is also possible to provide multiple composite bumps within one electrode.

【００１１】特に、凸状体がポリイミド樹脂であるもの
がよく、また、それを覆う金属膜がＡｌ−Ｓｉ合金であ
るものがよい。凸状体を覆う金属膜を半田付けできる多
層の金属膜とすることもできる。また、半導体チップの
裏面に半田付けできる多層の金属膜を設けてもよく、或
いは、半導体チップの両面に複合バンプを設けてもよ
い。In particular, the convex body is preferably made of polyimide resin, and the metal film covering the convex body is preferably made of Al--Si alloy. The metal film covering the convex body may be a multi-layered metal film that can be soldered. Further, a solderable multilayer metal film may be provided on the back surface of the semiconductor chip, or composite bumps may be provided on both surfaces of the semiconductor chip.

【００１２】更に、複合バンプ上に電極板を圧接した半
導体装置とすることができる。上記の半導体装置の製造
方法としては、定量吐出器により、半導体上にポリイミ
ド樹脂を吐出し、凸状体を形成するものとする。Further, a semiconductor device can be obtained in which an electrode plate is pressed onto the composite bump. As a method for manufacturing the above semiconductor device, a polyimide resin is discharged onto the semiconductor by a constant-volume dispenser to form a convex body.

【００１３】[0013]

【作用】上記の手段を講じ、弾性率の小さい物質からな
る凸状体と、弾性率が大きく、膨張係数の近い金属膜で
その凸状体を覆つた複合バンプを電極部に設けた半導体
装置とすることによって、加圧に強く（加圧しても塑性
変形しにくい芯をもつ）熱応力に対しても強く、適度に
変形能があり、溶融接続を前提としないので大面積に適
する大きなバンプを持つ半導体装置とすることができ
る。A semiconductor device having the electrode means provided with a convex body made of a substance having a small elastic modulus and a composite bump in which the convex body is covered with a metal film having a large elastic modulus and a close expansion coefficient in the electrode section by taking the above-mentioned means. With this, it is strong against pressure (has a core that is not easily plastically deformed even when pressure is applied), it is also moderately deformable, and it does not require fusion splicing, so it is a large bump suitable for a large area. Can be used as a semiconductor device.

【００１４】一つの電極内に多数の複合バンプを設けれ
ば、一層大電流容量の半導体装置に適する構成となる。
特に、凸状体がポリイミド樹脂で、また、それを覆う金
属膜がＡｌ−Ｓｉ合金であれば、湿式の電解メッキ等を
行うことなく、普通のウェハプロセスの範囲内でバンプ
が形成できる。Providing a large number of composite bumps in one electrode provides a structure suitable for a semiconductor device having a larger current capacity.
In particular, if the convex body is a polyimide resin and the metal film covering the convex body is an Al-Si alloy, bumps can be formed within a normal wafer process without performing wet electrolytic plating or the like.

【００１５】更に、凸状体を覆う金属膜を半田付けでき
る多層の金属膜とすれば、従来のバンプと同様の接続が
可能であり、応用範囲が広げられる。また、半導体チッ
プの裏面に半田付けできる多層の金属膜を設けてもよ
く、或いは、半導体チップの両面に複合バンプを設けれ
ば接続を容易にする。更に、複合バンプ上に電極板を圧
接すれば、圧接型半導体装置に適用できる。Furthermore, if the metal film covering the convex body is a multi-layered metal film which can be soldered, the same connection as the conventional bump can be made, and the range of application can be expanded. In addition, a solderable multilayer metal film may be provided on the back surface of the semiconductor chip, or composite bumps may be provided on both surfaces of the semiconductor chip to facilitate connection. Furthermore, if an electrode plate is pressed onto the composite bump, it can be applied to a pressure-contact type semiconductor device.

【００１６】上記の半導体装置の製造方法としては、定
量吐出器により、半導体上にポリイミド樹脂を吐出し、
凸状体を形成すれば、精度良く均一なバンプが容易に形
成できる。As a method of manufacturing the above semiconductor device, polyimide resin is discharged onto the semiconductor by a constant-volume dispenser,
By forming the convex body, it is possible to easily form uniform and accurate bumps.

【００１７】[0017]

【実施例】以下に図面を参照しながら本発明の実施例に
ついて説明する。図１は、本発明の第一の実施例のトラ
ンジスタの断面図である。半導体チップ１には、フォト
エッチング技術を用いたパターン形成、酸化、不純物拡
散等の工程により、ｐ型のベース拡散領域３と、ｎ型の
エミッタ拡散領域４等のトランジスタの構造が作り込ま
れている。半導体基板２の表面上は、酸化膜８が覆って
おり、その酸化膜８にベース開口部５、エミッタ開口部
６が開けられている。ベース開口部５、エミッタ開口部
６を通じてそれぞれベース拡散領域３、エミッタ拡散領
域４と接触しているＡｌ電極７が、酸化膜８の上にチッ
プ１の周辺近くまで延びていて、その上にポリイミド樹
脂からなる球の一部をなすような部分球状の凸状体１８
がある。部分球状の凸状体１８の上を覆う第二Ａｌ電極
１７は一部でＡｌ電極７と接続している。従って、ポリ
イミド樹脂からなる部分球状の凸状体１８を第二Ａｌ電
極１７で覆った複合バンプ２０ができている。更にＡｌ
電極７の平らな部分を、窒化膜等からなる表面保護膜１
１で覆っている。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of a transistor according to the first embodiment of the present invention. In the semiconductor chip 1, a transistor structure such as a p-type base diffusion region 3 and an n-type emitter diffusion region 4 is formed by a process such as pattern formation using a photoetching technique, oxidation, and impurity diffusion. There is. An oxide film 8 covers the surface of the semiconductor substrate 2, and a base opening 5 and an emitter opening 6 are opened in the oxide film 8. An Al electrode 7, which is in contact with the base diffusion region 3 and the emitter diffusion region 4 through the base opening 5 and the emitter opening 6, respectively, extends on the oxide film 8 to near the periphery of the chip 1, and the polyimide is formed thereon. Partially spherical convex body 18 forming part of a sphere made of resin
There is. The second Al electrode 17 covering the partial spherical convex body 18 is partially connected to the Al electrode 7. Therefore, the composite bump 20 in which the partially spherical convex body 18 made of polyimide resin is covered with the second Al electrode 17 is formed. Further Al
The flat portion of the electrode 7 is covered with a surface protection film 1 made of a nitride film or the like.
Covered with 1.

【００１８】図３（ａ）ないし（ｅ）は、図１の第一の
実施例のトランジスタの製造工程順の断面図である。ｐ
型のベース拡散領域３およびｎ型のエミッタ拡散領域４
を形成したｎ形シリコン基板２上の酸化膜８にフォトエ
ッチング技術により、ベース開口部５およびエミッタ開
口部６をあける〔同図（ａ）〕。Ａｌ−Ｓｉ合金をスパ
ッタリング法により被着し、フォトエツチングしてＡｌ
電極７を形成する〔同図（ｂ）〕。次に、バンプを形成
しようとするＡｌ電極７の表面に、ポリイミド樹脂を内
径２００μｍのノズルより数μｃｃ正確に吐出、滴下
し、熱処理して、精度良く部分球状の凸状体１８を形成
する〔同図（ｃ）〕。このポリイミド樹脂としては、例
えば信越化学（株）製のＫＪＲ−６５１を用いた。吐出
装置はノードソン（株）製のアキュラジェッターシステ
ムＳシリーズを、ノズルは同社の２７Ｇを用いた。この
ポリイミド樹脂を最高温度２５０℃で熱処理すると、表
面張力により直径４００〜８００μｍ±１０％、高さ５
〜２０μｍ±１０％、と均一性の優れた部分球状の凸状
体１８が形成される。次に、再びＡｌ−Ｓｉ合金をスパ
ッタリング法により被着し、第二Ａｌ電極１７をフォト
エツチングでパターン形成して、複合バンプ２０を形成
する〔同図（ｄ）〕。第二Ａｌ電極１７は、必要に応じ
その膜厚を定めればよく、３〜１０μｍが適当である。
最後に、プラズマＣＶＤ法により窒化膜の保護膜１１を
堆積しパターン形成して、第二Ａｌ電極１７の平坦な部
分を保護する〔同図（ｅ）〕。FIGS. 3A to 3E are sectional views in the order of manufacturing steps of the transistor of the first embodiment shown in FIG. p
-Type base diffusion region 3 and n-type emitter diffusion region 4
A base opening 5 and an emitter opening 6 are formed in the oxide film 8 formed on the n-type silicon substrate 2 by a photoetching technique [FIG. An Al-Si alloy is deposited by a sputtering method and photoetched to form an Al.
The electrode 7 is formed [(b) in the figure]. Next, a polyimide resin is accurately discharged and dropped by several μcc from a nozzle having an inner diameter of 200 μm onto the surface of the Al electrode 7 on which bumps are to be formed, and heat treatment is performed to form a partially spherical convex body 18 with high accuracy [ The same figure (c)]. As this polyimide resin, for example, KJR-651 manufactured by Shin-Etsu Chemical Co., Ltd. was used. The discharge device used was Acura Jetter System S series manufactured by Nordson Co., Ltd., and the nozzle used was 27G of the same company. When this polyimide resin is heat-treated at a maximum temperature of 250 ° C., the surface tension causes a diameter of 400 to 800 μm ± 10% and a height of 5
˜20 μm ± 10%, a partially spherical convex body 18 having excellent uniformity is formed. Next, an Al-Si alloy is deposited again by the sputtering method, and the second Al electrode 17 is patterned by photoetching to form the composite bump 20 [(d) in the figure]. The thickness of the second Al electrode 17 may be determined as necessary, and 3 to 10 μm is suitable.
Finally, a protective film 11 of a nitride film is deposited and patterned by the plasma CVD method to protect the flat portion of the second Al electrode 17 [(e) in the figure].

【００１９】そもそも、バンプに求められる特性として
最も重要なことは、形状が均一であること、電気的
な接続が良好なことであり、精度良く、凸状のふくらみ
を形成でき、かつ適当に変形して良く接触するのであれ
ば、芯が絶縁性でもよく、それを芯にして、その上に金
属膜を重ねることにより、バンプとすることができる。
ここで、芯となり得る条件は、（１）覆い被せる金属よ
り、弾性率（例えばヤング率のような）が小さいこと、
（２）熱膨張係数が覆い被せる金属とほぼ等しいこと、
（一桁以内）（３）ガラス転移点が低いこと、（２５０
℃程度が望ましい）（４）破壊強度がシリコンの１００
ＭＰａとほぼ等しいこと、等である。In the first place, the most important characteristics required for bumps are that they have a uniform shape and that they have good electrical connection, and that they can form a convex bulge with high accuracy and are appropriately deformed. As long as they make good contact with each other, the core may have an insulating property, and a bump can be formed by using the core as a core and stacking a metal film thereon.
Here, the condition that can be the core is that (1) the elastic modulus (such as Young's modulus) is smaller than that of the metal to be covered,
(2) The coefficient of thermal expansion is almost equal to that of the metal to be covered,
(Within one digit) (3) Low glass transition point, (250
(° C is desirable) (4) Breaking strength of silicon is 100
Approximately equal to MPa, and so on.

【００２０】上記の方法で形成したポリイミド樹脂から
なる部分球状の凸状体１８は、（１）ヤング率が２３５
０ＭＰａで、芯を覆うＡｌ電極１７のヤング率７．４×
１０ 4 ＭＰａより小さく、（２）熱膨張係数が５．０×
１０-5／℃で、Ａｌ電極１７の熱膨張係数２．９×１０
-5／℃とほぼ等しく、（３）Ｔｇ（ガラス転移温度）は
２６０℃で軟化させ易く、（４）引っ張り強度は１３７
ＭＰａでありバンプの芯として適している。Ａｌ電極１
７は、硬さ（ブリネル硬度）１７Ｈｂ、伸び６０％の特
性を有するので、応力に対して適当に変形し、良く接触
する。From the polyimide resin formed by the above method
The partially spherical convex body 18 has (1) Young's modulus of 235
Young's modulus of the Al electrode 17 covering the core at 0 MPa 7.4 ×
10 FourLess than MPa, (2) coefficient of thermal expansion 5.0 ×
10-Five/ ° C., thermal expansion coefficient of Al electrode 17 is 2.9 × 10
-FiveIs almost equal to / ° C, and (3) Tg (glass transition temperature) is
Easy to soften at 260 ℃, (4) Tensile strength is 137
It is MPa and is suitable as the core of the bump. Al electrode 1
No. 7 has a hardness (Brinell hardness) of 17 Hb and an elongation of 60%.
Since it has a property, it deforms appropriately against stress and makes good contact.
I do.

【００２１】上記の製造方法をとれば、従来のように半
田或いは金の電解メッキをする必要がなく、製造工程が
簡単であり、しかも多数のバンプを均一に形成した半導
体装置を得ることができる。図２は、本発明の第二の実
施例のトランジスタの断面図である。ｎ型半導基板２上
の酸化膜８にベース開口部５、エミッタ開口部６があけ
られていて、Ａｌ電極７がそれらの開口部を通じてそれ
ぞれベース拡散領域３エミッタ拡散領域４と接触してい
るのは、図１の第一の実施例と同じである。この例で
は、チップ１の周辺に近い酸化膜８の上にポリイミド樹
脂からなる部分球状の凸状体１８が設けられている。ベ
ース開口部５、エミッタ開口部６を通じてそれぞれベー
ス拡散領域３エミッタ拡散領域４と接触しているＡｌ電
極７が部分球状の凸状体１８の上まで延びている。従っ
て、ポリイミド樹脂からなる部分球状の凸状体１８をＡ
ｌ電極７で覆った複合バンプ２０が形成されている。Ａ
ｌ電極７の平らな部分は、窒化膜等からなる表面保護膜
１１で覆われている。According to the above-mentioned manufacturing method, there is no need to perform electrolytic plating of solder or gold as in the conventional case, the manufacturing process is simple, and a semiconductor device having a large number of bumps uniformly formed can be obtained. . FIG. 2 is a sectional view of a transistor according to the second embodiment of the present invention. A base opening 5 and an emitter opening 6 are formed in the oxide film 8 on the n-type semiconductor substrate 2, and an Al electrode 7 is in contact with the base diffusion region 3 and the emitter diffusion region 4 through these openings. Is the same as in the first embodiment of FIG. In this example, a partially spherical convex body 18 made of a polyimide resin is provided on the oxide film 8 near the periphery of the chip 1. The Al electrode 7 which is in contact with the base diffusion region 3 and the emitter diffusion region 4 through the base opening 5 and the emitter opening 6, respectively, extends to above the partially spherical convex body 18. Therefore, the partially spherical convex body 18 made of polyimide resin is
A composite bump 20 covered with the 1-electrode 7 is formed. A
The flat part of the l-electrode 7 is covered with a surface protection film 11 made of a nitride film or the like.

【００２２】図１の第一の実施例では、Ａｌ電極７と第
二Ａｌ電極１７との重なる部分が広いので、図２の第二
の実施例より一層信頼性の高い半導体装置とすることが
できる。一方図２の第二の実施例の半導体装置は、図１
の第一の実施例に比べて第二Ａｌ電極１７の分だけ工程
が短くでき、製造が容易である。図４は、本発明の第三
の実施例のトランジスタの断面図であり、図１の第一の
実施例の変形例である。すなわち一つの電極部に、ポリ
イミド樹脂からなる部分球状の凸状体１８を第二Ａｌ電
極１７で覆った複合バンプ２０を多数並列になるように
形成した構造で、電極面積の広い、電流容量の大きい素
子に適する。In the first embodiment of FIG. 1, since the overlapping portion of the Al electrode 7 and the second Al electrode 17 is wide, it is possible to obtain a semiconductor device having higher reliability than the second embodiment of FIG. it can. On the other hand, the semiconductor device of the second embodiment shown in FIG.
Compared with the first embodiment, the process can be shortened by the amount of the second Al electrode 17, and the manufacturing is easy. FIG. 4 is a cross-sectional view of the transistor of the third embodiment of the present invention, which is a modification of the first embodiment of FIG. That is, in one electrode part, a structure in which a large number of composite bumps 20 in which a partial spherical convex body 18 made of a polyimide resin is covered with a second Al electrode 17 is formed in parallel is provided, and the electrode area is wide and the current capacity Suitable for large devices.

【００２３】図５は、本発明の第四の実施例のトランジ
スタの断面図であり、図１の第一の実施例の半導体装置
のフリップチップタイプとしての組立例である。プリン
ト基板２６の電極パッド３７の上に半導体チップ１の複
合バンプ２０を載せ、上方から少し押しながら、接着剤
３８で接着し且つ回路の接続を行う。接着剤３８が導電
性のものであれば接続は、一層信頼性の高いものとな
る。図２の第二の実施例、図４の第三の実施例のトラン
ジスタも同様に組み立てられる。FIG. 5 is a sectional view of a transistor of a fourth embodiment of the present invention, which is an example of assembling the semiconductor device of the first embodiment of FIG. 1 as a flip chip type. The composite bump 20 of the semiconductor chip 1 is placed on the electrode pad 37 of the printed board 26, and while being slightly pressed from above, the composite bump 20 is adhered with the adhesive 38 and the circuit is connected. If the adhesive 38 is conductive, the connection will be even more reliable. The transistors of the second embodiment of FIG. 2 and the third embodiment of FIG. 4 are assembled in the same manner.

【００２４】図６は、本発明の第五の実施例のトランジ
スタの断面図であり、図１の第一の実施例の変形例であ
る。すなわち、第一の実施例の半導体装置の第二Ａｌ電
極１７の上に更に、メタルマスクによる選択蒸着によ
り、下層からＴｉ／Ｃｕ／Ｎｉの多層膜３９を被着した
複合バンプ２０を形成している。このような多層膜を形
成すれば、半田付け可能な半導体装置になる。例えば、
フリップチップタイプとして、プリント基板の電極パッ
ドの上に半田箔を置いて置き、半導体チップ１の複合バ
ンプ２０を載せ、トンネル炉を通せば、従来の半田バン
プと全く同様に回路の接続ができる。最上層にＡｕ層を
被着し、Ａｕ−Ｓｎ系の半田付けをすることもできる。FIG. 6 is a sectional view of a transistor of the fifth embodiment of the present invention, which is a modification of the first embodiment of FIG. That is, a composite bump 20 having a Ti / Cu / Ni multilayer film 39 deposited from below is further formed on the second Al electrode 17 of the semiconductor device of the first embodiment by selective vapor deposition using a metal mask. There is. When such a multilayer film is formed, a solderable semiconductor device is obtained. For example,
As a flip-chip type, if a solder foil is placed on the electrode pad of the printed board, the composite bump 20 of the semiconductor chip 1 is placed thereon, and a tunnel furnace is passed through, the circuit connection can be performed in the same manner as the conventional solder bump. It is also possible to deposit an Au layer on the uppermost layer and perform Au—Sn soldering.

【００２５】図７は、本発明の第六の実施例のトランジ
スタの断面図であり、図１の第一の実施例の変形例であ
る。すなわち、上面側に凸状体１８と第二Ａｌ電極から
なる複合バンプ２０をもつ第一の実施例の半導体装置の
裏面に下層より、Ｔｉ／Ｎｉ／Ａｕの多層膜の裏面電極
１９を烝着している。このような多層膜を形成すれば、
裏面が半田付け可能な半導体装置になる。FIG. 7 is a sectional view of a transistor of a sixth embodiment of the present invention, which is a modification of the first embodiment of FIG. That is, the back surface electrode 19 of the Ti / Ni / Au multilayer film is adhered from the lower layer to the back surface of the semiconductor device of the first embodiment having the convex body 18 and the composite bump 20 including the second Al electrode on the upper surface side. are doing. If such a multilayer film is formed,
The back side becomes a solderable semiconductor device.

【００２６】図８は、本発明の第七の実施例の半導体装
置の断面図であり、この例の半導体装置は、図７の第六
の実施例のように裏面電極を持つダイオードで、その半
導体装置の組立例である。セラミクスからなる環状の絶
縁壁２７の両端に放熱版を兼ねるカソード電極２８とア
ノード電極２５が気密に接着されたケース２３内に、上
述の如きバンプ電極を形成した半導体チップ１が封入さ
れている。FIG. 8 is a sectional view of a semiconductor device according to a seventh embodiment of the present invention. The semiconductor device of this example is a diode having a back electrode as in the sixth embodiment of FIG. It is an example of assembling a semiconductor device. The semiconductor chip 1 on which the bump electrodes as described above are formed is enclosed in a case 23 in which a cathode electrode 28 and an anode electrode 25, which also serve as heat dissipation plates, are airtightly adhered to both ends of an annular insulating wall 27 made of ceramics.

【００２７】すなわち、絶縁壁２７と気密に接着された
カソード電極２８に、半導体チップ１を半田２４で接着
する。次に、複合バンプ２０が放熱板を兼ねるアノード
電極２５に接するように数十ＭＰａの加圧力で加圧し、
その状態で絶縁壁２７とアノード電極２５との間をヘリ
ウムアーク溶接で融着する。その後、絶縁壁２７に設け
られた脱気口２９より内部の空気を抜いて真空にし、窒
素或いはヘリウムガス等の不活性ガスと置換し、脱気口
２９を封止して、図８の半導体装置が完成する。４１は
封止部である。That is, the semiconductor chip 1 is bonded by the solder 24 to the cathode electrode 28 that is hermetically bonded to the insulating wall 27. Next, a pressure of several tens of MPa is applied so that the composite bumps 20 come into contact with the anode electrode 25 that also serves as a heat sink,
In this state, the insulating wall 27 and the anode electrode 25 are fused by helium arc welding. After that, the air inside is evacuated from the deaeration port 29 provided in the insulating wall 27 to make a vacuum, and it is replaced with an inert gas such as nitrogen or helium gas, and the deaeration port 29 is sealed, and the semiconductor of FIG. The device is completed. 41 is a sealing part.

【００２８】図８の半導体装置の加圧力は、せいぜい数
十ＭＰａ（通常２０ＭＰａ）程度である。このとき、複
合バンプ２０とアノード電極２５とが圧接されると、ま
ず複合バンプ２０の第二Ａｌ電極１７が、少し変形して
第一の衝撃を緩和し、さらなる力に対しては、ヤング率
の小さい芯である部分球状の凸状体１８が変形して、圧
力を吸収する。この時、第二Ａｌ電極１７も厚さが薄く
柔らかいこと、伸びのよいことから、凸状体１８の変形
に追随して変形する。しかし、ヤング率は大きいので、
アノード電極との接触は確保される。さらに、熱応力に
対しては、シリコンの熱膨張係数が、２．４×１０-6／
℃と、上記のバンプ形成物質より一桁小さいが、第二Ａ
ｌ電極１７と凸状体１８とは、ほぼ同じ熱膨張係数なの
で、シリコンと約一桁違ってもサーマルストレスによる
異常は生じ難い。このように、複合バンプ２０を形成し
た半導体装置を、従来のバンプ付きの半導体装置では難
しかった加圧接触により使用することができる。The pressure applied to the semiconductor device shown in FIG. 8 is at most about several tens MPa (normally 20 MPa). At this time, when the composite bump 20 and the anode electrode 25 are brought into pressure contact with each other, first, the second Al electrode 17 of the composite bump 20 is slightly deformed to alleviate the first impact, and for further force, Young's modulus is increased. The partially spherical convex body 18 which is a small core deforms to absorb the pressure. At this time, since the second Al electrode 17 is also thin and soft and has good elongation, it deforms following the deformation of the convex body 18. However, since Young's modulus is large,
Contact with the anode electrode is ensured. Furthermore, with respect to thermal stress, the coefficient of thermal expansion of silicon is 2.4 × 10 −6 /
C, which is an order of magnitude smaller than the above bump forming material,
Since the l-electrode 17 and the convex body 18 have substantially the same coefficient of thermal expansion, an abnormality due to thermal stress is unlikely to occur even if they differ from silicon by an order of magnitude. In this way, the semiconductor device having the composite bumps 20 can be used by pressure contact, which is difficult with the conventional semiconductor device with bumps.

【００２９】図９は、本発明の第八の実施例のダイオー
ドの断面図であり、図８の第七の実施例の変形である。
すなわち、絶縁壁２７にアノード電極２５とカソード電
極２８が接着されたケース２３内に、複合バンプ２０を
有するチップ１が封入されているのは同じであるが、チ
ップ１は電極板３０に半田２４で接着されており、複合
バンプ２０の上には電極板３１が、バネ３２で押さえら
れている。このようにすれば、バネの強度によって、加
圧力が制御できる特長がある。FIG. 9 is a sectional view of the diode of the eighth embodiment of the present invention, which is a modification of the seventh embodiment of FIG.
That is, the chip 1 having the composite bump 20 is encapsulated in the case 23 in which the anode electrode 25 and the cathode electrode 28 are adhered to the insulating wall 27, but the chip 1 is soldered to the electrode plate 30 by the solder 24. The electrode plate 31 is pressed onto the composite bump 20 by the spring 32. With this configuration, the pressing force can be controlled by the strength of the spring.

【００３０】図１０は、本発明の第九の実施例のダイオ
ードの断面図であり、両面に複合バンプ２０を設けた例
を示す。すなわち、ダイオードチップ１の一方の面上の
酸化膜８に明けられたアノード開口部３３を介してアノ
ード領域３４に接するＡｌ電極７の上にポリイミド樹脂
からなる部分球状の凸状体１８を形成し、その凸状体１
８を覆う第二Ａｌ電極が形成され、複合バンプ２０が設
けられている。ダイオードチップ１の他方の面にもＡｌ
−Ｓｉ合金からなるＡｌ電極３５が被着され、その上に
同様に凸状体１８と第二Ａｌ電極３９からなる複合バン
プ４０が設けられている。カソード側は、面積が広いの
で多数の複合バンプ４０が形成されている。FIG. 10 is a sectional view of a diode according to the ninth embodiment of the present invention, showing an example in which composite bumps 20 are provided on both sides. That is, a partial spherical convex body 18 made of a polyimide resin is formed on the Al electrode 7 in contact with the anode region 34 through the anode opening 33 exposed in the oxide film 8 on one surface of the diode chip 1. , Its convex body 1
A second Al electrode covering 8 is formed, and a composite bump 20 is provided. Al on the other side of the diode chip 1
An Al electrode 35 made of a —Si alloy is deposited, and a composite bump 40 made of the convex body 18 and the second Al electrode 39 is also provided thereon. Since the cathode side has a large area, a large number of composite bumps 40 are formed.

【００３１】図１１は、本発明の第十の実施例の半導体
装置の断面図であり、この例の半導体装置は、図１０の
実施例のように両面に複合バンプ２０および４０をもつ
ダイオードで、その組立例である。セラミクスからなる
環状の絶縁壁２７の両端に放熱版を兼ねるカソード電極
２８とアノード電極２５が気密に接着されたケース２３
内に、上述の如きバンプ電極を形成した半導体チップ１
が封入されている。この例では、アノード電極２５と複
合バンプ２０だけでなく、カソード電極２５と複合バン
プ４０とも圧接されていて、半田付けされていない点が
図８の第七の実施例と違っている。半田付けがないの
で、熱サイクル疲労に対して強く、高信頼性の構造であ
る。組立方法は、第七の実施例と同様なので省略する。FIG. 11 is a sectional view of a semiconductor device according to a tenth embodiment of the present invention. This semiconductor device is a diode having composite bumps 20 and 40 on both surfaces as in the embodiment of FIG. , Is an example of its assembly. A case 23 in which a cathode electrode 28 and an anode electrode 25, which also serve as heat dissipation plates, are airtightly adhered to both ends of an annular insulating wall 27 made of ceramics.
A semiconductor chip 1 having the above-mentioned bump electrodes formed therein
Is enclosed. This example is different from the seventh embodiment in FIG. 8 in that not only the anode electrode 25 and the composite bump 20 but also the cathode electrode 25 and the composite bump 40 are pressed and not soldered. Since there is no soldering, it has a structure with high reliability against heat cycle fatigue. Since the assembling method is the same as that of the seventh embodiment, it will be omitted.

【００３２】なお、カソード電極２８に複合バンプ４０
を形成して、半導体チップ１をケース２３内に封入した
図１２のような形もとることができる。図８、９、１１
および１２はダイオードについて圧接構造の例を示した
が、ダイオードに限られたものではなく、特にＭＯＳＦ
ＥＴ（金属−酸化膜−半導体型電界効果素子）、絶縁ゲ
ートバイポーラトランジスタや絶縁ゲートサイリスタの
ようにゲート電力が小さい場合は、ゲート端子をワイヤ
ボンディング等で取り出すなどして、上記の圧接構造を
適用することができる。The composite bump 40 is formed on the cathode electrode 28.
Can be formed, and the semiconductor chip 1 can be formed in a case 23 as shown in FIG. 8, 9, 11
Although 12 and 12 show an example of a pressure contact structure for a diode, the structure is not limited to a diode, and a MOSF in particular is used.
When the gate power is low, such as ET (metal-oxide film-semiconductor field effect device), insulated gate bipolar transistor and insulated gate thyristor, the above pressure contact structure is applied by taking out the gate terminal by wire bonding or the like. can do.

【００３３】[0033]

【発明の効果】以上述べたように本発明は、以下の効果
を奏する。弾性率の小さい物質からなる凸状体と、弾性
率が大きく、膨張係数の近い金属膜でその凸状体を覆つ
た複合バンプを電極部に設けた半導体装置とすることに
よって、簡単な工程で、大面積に適する大きなバンプを
持つ半導体装置とすることができ、半導体装置の信頼性
向上および価格低減に資する。As described above, the present invention has the following effects. By using a semiconductor device in which a convex body made of a substance having a small elastic modulus and a composite bump in which the convex body is covered with a metal film having a large elastic modulus and a close expansion coefficient are provided in the electrode portion, a simple process can be performed. A semiconductor device having large bumps suitable for a large area can be provided, which contributes to improvement in reliability and cost reduction of the semiconductor device.

【００３４】一つの電極内に多数の複合バンプを設ける
ことにより、一層大電流容量の半導体装置の信頼性向上
および価格低減に資する。また、従来の溶融接合型のバ
ンプではできなかった、加圧接触構造のバンプ付き半導
体装置が可能になった。特に、凸状体をポリイミド樹脂
とし、定量吐出器により、半導体上にポリイミド樹脂を
吐出し、凸状体を形成すれば、精度良く均一なバンプが
容易に形成できる。また、それを覆う金属膜がＡｌ−Ｓ
ｉ合金であれば、湿式の電解メッキ等を行うことなく、
普通のウェハプロセスの範囲内でバンプが形成できるの
で、設備の軽減ができ、また工数の低減が可能である。Providing a large number of composite bumps in one electrode contributes to improvement in reliability and cost reduction of a semiconductor device having a larger current capacity. In addition, a semiconductor device with bumps having a pressure contact structure, which has not been possible with the conventional fusion-bonded bumps, has become possible. In particular, if the convex body is made of polyimide resin, and the polyimide resin is discharged onto the semiconductor by a constant-volume dispenser to form the convex body, uniform bumps can be easily formed with high accuracy. Also, the metal film covering it is Al-S
If it is an i alloy, without performing wet electrolytic plating,
Since bumps can be formed within the range of a normal wafer process, equipment can be reduced and man-hours can be reduced.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の第一の実施例の半導体装置の断面図FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

【図２】本発明の第二の実施例の半導体装置の断面図FIG. 2 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

【図３】（ａ）ないし（ｅ）は図５の半導体装置の製造
方法を説明するための製造工程順の断面図3A to 3E are cross-sectional views in the order of manufacturing steps for explaining the method for manufacturing the semiconductor device in FIG.

【図４】本発明の第三の実施例の半導体装置の断面図FIG. 4 is a sectional view of a semiconductor device according to a third embodiment of the present invention.

【図５】本発明の第四の実施例の半導体装置の断面図FIG. 5 is a sectional view of a semiconductor device according to a fourth embodiment of the present invention.

【図６】本発明の第五の実施例の半導体装置の断面図FIG. 6 is a sectional view of a semiconductor device according to a fifth embodiment of the present invention.

【図７】本発明の第六の実施例の半導体装置の断面図FIG. 7 is a sectional view of a semiconductor device according to a sixth embodiment of the present invention.

【図８】本発明の第七の実施例の半導体装置の断面図FIG. 8 is a sectional view of a semiconductor device according to a seventh embodiment of the present invention.

【図９】本発明の第八の実施例の半導体装置の断面図FIG. 9 is a sectional view of a semiconductor device according to an eighth embodiment of the present invention.

【図１０】本発明の第九の実施例の半導体装置の断面図FIG. 10 is a sectional view of a semiconductor device according to a ninth embodiment of the present invention.

【図１１】本発明の第十の実施例の半導体装置の断面図FIG. 11 is a sectional view of a semiconductor device according to a tenth embodiment of the present invention.

【図１２】本発明の第十一の実施例の半導体装置の断面
図FIG. 12 is a sectional view of a semiconductor device according to an eleventh embodiment of the present invention.

【図１３】（ａ）は従来の半導体装置の例の平面図、
（ｂ）は（ａ）の半導体装置のＡ−Ａ線における断面図FIG. 13A is a plan view of an example of a conventional semiconductor device,
(B) is sectional drawing in the AA line of the semiconductor device of (a).

【図１４】（ａ）ないし（ｄ）は図１３の半導体装置の
製造方法を説明するための製造工程順の断面図14A to 14D are cross-sectional views in the order of manufacturing steps for explaining the method for manufacturing the semiconductor device in FIG.

【符号の説明】[Explanation of symbols]

１ 半導体チップ ２ シリコン基板 ３ ベース拡散領域 ４ エミッタ拡散領域 ５ ベース開口部 ６ エミッタ開口部 ７ Ａｌ電極 ８ 酸化膜 ９ 下地金属膜 １０ フォトレジスト １１ 保護膜 １２ バンプ金属 １３ ベースバンプ １４ エミッタバンプ １５ ベースバンプ開口部 １６ エミッタバンプ開口部 １７ 第二Ａｌ電極 １８ 凸状体 １９ 裏面電極 ２０ 複合バンプ ２１ コレクタ開口部 ２２ コレクタバンプ ２３ ケース ２４ 半田 ２５ アノード電極 ２６ プリント基板 ２７ 絶縁壁 ２８ カソード電極 ２９ 脱気口 ３０ 電極板 ３１ 電極板 ３２ バネ ３３ アノード開口部 ３４ アノード領域 ３５ Ａｌ電極 ３６ 多層金属膜 ３７ 電極パッド ３８ 接着剤 ３９ 第二Ａｌ電極 ４０ 複合バンプ ４１ 封止部 1 Semiconductor Chip 2 Silicon Substrate 3 Base Diffusion Region 4 Emitter Diffusion Region 5 Base Opening 6 Emitter Opening 7 Al Electrode 8 Oxide Film 9 Base Metal Film 10 Photoresist 11 Protective Film 12 Bump Metal 13 Base Bump 14 Emitter Bump 15 Base Bump Opening 16 Emitter bump Opening 17 Second Al electrode 18 Convex body 19 Backside electrode 20 Composite bump 21 Collector opening 22 Collector bump 23 Case 24 Solder 25 Anode electrode 26 Printed board 27 Insulating wall 28 Cathode electrode 29 Degassing port 30 Electrode plate 31 Electrode plate 32 Spring 33 Anode opening 34 Anode region 35 Al electrode 36 Multi-layer metal film 37 Electrode pad 38 Adhesive 39 Second Al electrode 40 Composite bump 41 Sealing part

Claims (9)

【特許請求の範囲】[Claims] 【請求項１】半導体の一方の主面の電極部に、弾性率の
小さい物質からなる凸状体と、弾性率が大きく、膨張係
数の近い金属膜でその凸状体を覆つた複合バンプを有す
ることを特徴とするバンプ付き半導体装置。1. A semiconductor-made bump having a small elastic modulus and a composite bump formed by covering the convex with a metal film having a large elastic modulus and a close expansion coefficient are provided on an electrode portion on one main surface of a semiconductor. A semiconductor device with bumps, characterized by having. 【請求項２】凸状体がポリイミド樹脂であることを特徴
とする請求項１に記載のバンプ付き半導体装置。2. The bumped semiconductor device according to claim 1, wherein the convex body is a polyimide resin. 【請求項３】凸状体を覆う金属膜がＡｌ−Ｓｉ合金であ
ることを特徴とする請求項１または２に記載のバンプ付
き半導体装置。3. The semiconductor device with bumps according to claim 1, wherein the metal film covering the convex body is an Al—Si alloy. 【請求項４】凸状体を覆う金属膜が半田付けできる多層
の金属膜であることを特徴とする請求項１ないし３のい
ずれかに記載のバンプ付き半導体装置。4. The semiconductor device with bumps according to claim 1, wherein the metal film covering the convex body is a solderable multilayer metal film. 【請求項５】半導体の裏面に半田付けできる多層の金属
膜を有することを特徴とする請求項１ないし４のいずれ
かに記載のバンプ付き半導体装置。5. The bumped semiconductor device according to claim 1, further comprising a multi-layered metal film that can be soldered on the back surface of the semiconductor. 【請求項６】半導体の両面に複合バンプを有することを
特徴とする請求項１ないし４のいずれかに記載のバンプ
付き半導体装置。6. The semiconductor device with bumps according to claim 1, which has composite bumps on both sides of the semiconductor. 【請求項７】一つの電極内に多数の複合バンプを有する
ことを特徴とする請求項１ないし６のいずれかに記載の
バンプ付き半導体装置。7. The bumped semiconductor device according to claim 1, wherein a plurality of composite bumps are provided in one electrode. 【請求項８】複合バンプと圧接される電極板を有するこ
とを特徴とする請求項１ないし７のいずれかに記載のバ
ンプ付き半導体装置。8. The semiconductor device with bumps according to claim 1, further comprising an electrode plate that is pressed against the composite bump. 【請求項９】定量吐出器により、半導体上にポリイミド
樹脂を吐出し、凸状体を形成することを特徴とする請求
項２に記載のバンプ付き半導体装置の製造方法。9. The method for manufacturing a semiconductor device with bumps according to claim 2, wherein a polyimide resin is discharged onto the semiconductor by a constant-volume dispenser to form a convex body.
JP609895A 1995-01-19 1995-01-19 Semiconductor device with bump and method of manufacturing the same Expired - Fee Related JP3261912B2 (en)

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JP609895A JP3261912B2 (en) 1995-01-19 1995-01-19 Semiconductor device with bump and method of manufacturing the same
SE9600180A SE9600180L (en) 1995-01-19 1996-01-18 Semiconductor device with a composite bead for contacting and a method for manufacturing it

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Application Number Priority Date Filing Date Title
JP609895A JP3261912B2 (en) 1995-01-19 1995-01-19 Semiconductor device with bump and method of manufacturing the same

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JP3261912B2 JP3261912B2 (en) 2002-03-04

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Also Published As

Publication number Publication date
JP3261912B2 (en) 2002-03-04
SE9600180D0 (en) 1996-01-18
SE9600180L (en) 1996-07-20

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