JPH08186804A - Television receiver - Google Patents

Abstract

PURPOSE: To attain VT signal reproduction processing without luminance speckles by eliminating a DC offset component causing luminance speckles in the unit of lines in a video image after reproduction if the DC offset component is superimposed on a VT signal before VT signal reproduction processing in the VT signal reproduction processing being part of the EDTV 2 demodulation processing. CONSTITUTION: A pre-stage of a VT signal reproduction circuit is provided with a horizontal phase detection circuit 2 detecting a phase of a horizontal synchronizing signal, accumulating circuits 4-6 generating a gate pulse based on an output of the circuit 2 to detect a DC offset level of an input video signal at the prestage of the VT signal reproduction circuit, a divider 8 dividing accumulated video data being an output of the circuits 4-6 by number of samples, a timing generating circuit 9 updating the DC offset level obtained as an output of the divider in the unit of horizontal lines, a load/hold circuit and a subtractor 13 subtracting output data of the load/hold circuit from an input video signal at the pre-stage of the VT signal reproduction circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television receiver having a decoder capable of receiving EDTV2 broadcast and capable of non-interlaced scanning of 525 lines / field.

[0002]

2. Description of the Related Art In recent years, an EDTV2 broadcasting system has been developed, which is compatible with the current NTSC broadcasting system and transmits a wide image having an aspect ratio of 16: 9 with high image quality.

Hereinafter, referring to FIGS. 4 and 5, the EDTV 2 will be described.
The outline of the broadcasting system will be described. Figure 4 shows EDTV2
It is a schematic diagram for demonstrating the method of multiplexing the video signal of a broadcasting system. In FIG. 4, the numbers from 1 to 525 on the vertical axis at the left end are the numbers of scanning lines within one frame period, and the numbers on the horizontal axis at the top end are when one horizontal scanning period is sampled at four times the frequency of the color subcarrier. 910 from 0 to 909
This is the number of each pixel.

The video signal of the EDTV2 broadcasting system is currently 4:
When images are received by three receivers, black bands are displayed at the top and bottom, and a 16: 9 image is displayed in the center in a so-called letterbox format. Referring to FIG. 4, in the first field, a video signal is transmitted by a total of 180 main image units from scanning line numbers 53 to 232. In the current NTSC broadcasting, since the total 240 scanning lines of scanning line numbers 23 to 262 were carried, it corresponds to exactly 3/4 scanning lines. Signals based on black are transmitted to a total of 30 upper non-image areas of scanning line numbers 23 to 52 and a total of 30 lower non-image areas of scanning line numbers 233 to 262.

Video signals of the EDTV2 broadcasting system are transmitted at 16: 9.
When the image is received by the wide receiver of, if the main image portion is simply zoomed and displayed, the horizontal and vertical resolutions will be lower than in the current broadcast, so the reinforcement signal is multiplexed. First, a horizontal high frequency signal of 4.2 to 6 MHz (hereinafter referred to as HH signal) is modulated by the blow-out carrier and multiplexed on the main picture portion.
Also, the vertical reinforcement signal of the luminance signal is modulated by the color carrier wave and multiplexed in the upper and lower non-image portions. 3 in the horizontal direction
Divided (pixel numbers 7 to 258, 259 to 510, 5
Information corresponding to 180 main image areas is divided into a total of 60 scanning lines in the upper and lower non-image areas. The signals sent by the vertical reinforcement signal are a vertical time resolution reinforcement signal (hereinafter referred to as VT signal) and a vertical high frequency signal (hereinafter referred to as VH signal). The VT signal is a reinforcement signal when converting the 180 interlaced scanning signals of the main picture portion into 360 sequential scanning signals, and the VH signal is a progressive scanning converted 360 video signal to 480 zoom signals. It is a reinforcement signal when performing (3-4 scanning line number conversion).

Scanning line numbers 22 and 285 in FIG.
The identification signal of V2 is multiplexed. This will be described with reference to FIG. FIG. 5 shows a waveform diagram of the EDTV2 identification signal. In FIG. 5, 27-bit information from B1 to B27 is multiplexed in one horizontal scanning period as numbers are attached to the waveform diagram. Each bit is 7 of color subcarrier
It has a width of a period (= about 2 μsec). The table below the waveforms in FIG. 5 summarizes the information of each bit, and the major ones will be described. B3 and B4 are EDT when 40 IRE
It is V2 broadcast, and when it is 0IRE, it is NTSC broadcast.
In B6 to B23, color subcarriers are multiplexed with an amplitude of ± 20 IRE, and when the phase is 0 phase, 1 is defined, and when it is π phase (in phase with color burst), 0 is defined. B8, B
It is possible to identify whether or not the VT signal, the VH signal, and the HH signal are multiplexed by 9 and B10, respectively. In the EDTV2 identification signal, in addition to the above identification information, B25-2
7 is multiplexed with phase information of the blow-out carrier that modulates the HH signal, and is further divided into three division points (B
1 to 9, B10 to 18, and B19 to 27) are information indicating the positions of the three division points of the VT signal / VH signal multiplexed in the upper and lower non-picture areas.

As a document describing the circuit configuration showing the circuit configuration of the conventional EDTV2 receiver for receiving the EDTV2 signal as described above (Nikkei Electronics 1994.
1-31 no. 600 P. P. 142-149 "2
Part <transmission / reception circuit> separates and transmits high resolution components ”).

A conventional EDTV2 receiving circuit will be described below with reference to FIG. Figure 3 shows the conventional EDTV2
It is a block diagram of a receiving circuit. In FIG. 3, reference numeral 201 is a tuner circuit for receiving and selecting broadcasts, detecting video, and outputting a composite video signal, 202 is an A / D converter for converting the composite video signal output from the tuner circuit 201 into a digital signal, and 203 is A. The identification signal detection circuit connected to the output terminal of the D / D converter 202 detects the EDTV2 identification signal multiplexed in the 22nd and 285th horizontal scanning periods of the horizontal scanning period of 525 lines / frame of the NTSC signal. It is a circuit to do. A three-dimensional Y / C separation circuit 204 is connected to the output end of the A / D converter 202, and separates and extracts a luminance signal and a chrominance signal by motion adaptive processing. Reference numeral 205 denotes an HH reproduction circuit, which further modulates the color signal extracted by the three-dimensional Y / C separation circuit 204 by a field difference to obtain a modulated HH.
The signal and the color signal are separated, and the HH signal is reproduced by multiplying the blown-out carrier extracted by the identification signal detection circuit 203 and the modulated HH signal. Reference numeral 206 denotes an HH combiner for adding the 4.2 MHz or lower component of the luminance signal output from the three-dimensional Y / C separation circuit 204 and the 4.2 to 6 MHz band component of the HH signal output from the HH reproduction circuit 205. Two
Reference numeral 07 is a VT / VH demodulation circuit which demodulates a VT / VH signal which is modulated by a color carrier of 3.58 MHz and is multiplexed in the upper and lower non-picture portions, and 208 is a V demodulated by the VT / VH demodulation circuit 207.
VT /, which multiplexes the T / VH signal with the luminance signals of the upper and lower non-image areas
VH multiplex circuit, 209 outputs EDTV2 identification signals such as B8 and B9 detected by the identification signal detection circuit 203 to VT / VH
Similar to the multiplexing circuit 208, an identification signal multiplexing circuit that multiplexes the luminance signals of 22H and 285H, 210 is the HH reproducing circuit 20.
5 is a color demodulation circuit that demodulates the color signal extracted in 5 and time-division-multiplexes two color signals to output. Reference numeral 211 is a D / A converter that converts the digital signals of the luminance and the color output from the identification signal multiplex circuit 209 and the color demodulation circuit 210, and 212 is a clock that serves as a reference timing for the operation of the digital signal processing circuits 202 to 211. A burst lock clock generation circuit 213 for generating an analog luminance signal output from the D / A converter 211, an A / D converter for converting a color difference signal into a digital signal, and a reference numeral 214 for a clear vision receiver or the like. An A / D converter 213 is a motion adaptive scanning line interpolation circuit that creates a sequential scanning signal from interlaced scanning signals that are present.
The luminance signal and color difference signal output from the
6 luminance current line signal, 217 luminance interpolation line signal,
Four signals of a color difference current line signal 218 and a color difference interpolation line signal 219 are output.

Reference numeral 215 is a VT / VH separation circuit connected to the luminance signal output terminal of the A / D converter 213. The VT signal and VH are multiplexed in the upper and lower non-image area using the frame difference.
Separate the signals. Reference numeral 221 denotes a VT reproduction circuit connected to the output terminal of the VT / VH separation circuit 215, which outputs the VT signal to the ED.
Reproduction is performed using a symmetric short kernel filter (hereinafter referred to as SSKF) that is generally used in the TV2 broadcasting system. A VT synthesizer 222 adds the high frequency component of the luminance interpolation line signal 217 output from the motion adaptive scanning line interpolation circuit 214 and the low frequency component of the VT signal output from the VT reproduction circuit 221. 224 is V
The H reproduction circuit reproduces the VH signal from the signal separated and output by the VT / VH separation circuit 215.

Reference numeral 223 is a scanning line number conversion circuit composed of a field memory and a vertical filter.
The number of 0 scanning lines is multiplied by 4/3 to synthesize 480 scanning lines, and 225 luminance current line signals, 226 luminance interpolation line signals, 227 color difference current line signals, and 228 color difference interpolation line signals are combined. Outputs four kinds of signals. 229 and 230 are V
The H combiner adds the VH signal output from the VH reproduction circuit 224 to each of the luminance current line signal 225 and the luminance interpolation line signal 226 output from the scanning line number conversion circuit 223.

Reference numeral 231 denotes a double speed conversion circuit composed of a line memory, which sequentially generates a scanning luminance signal from the luminance current line signal output from the VH synthesizer 229 and the luminance interpolation line signal output from the VH synthesizer 230. , The color difference current line signal 227 output from the scanning line number conversion circuit 223
And the color difference interpolation line signal 228 are used to sequentially generate a scan color difference signal. Reference numeral 232 is a D / A converter connected to the output of the double speed conversion circuit 231 and outputs a luminance signal for sequential scanning and two color difference signals. A line lock clock generation circuit 233 generates a clock that serves as a reference timing for the operation of the digital signal processing circuits 213 to 232.

Reference numeral 234 is an RGB processing circuit for synthesizing RGB signals by matrix calculation from the signal output from the D / A converter 232, and 235 is a display for displaying the output of the RGB processing circuit 234. The aspect ratio of the screen is 16 :. It is 9.

The conventional EDTV 2 constructed as described above
The operation of the receiving circuit will be described below. First, the identification signal detection circuit 203 detects the identification signal multiplexed on the scanning line numbers 22 and 285 of the composite video signal from the tuner circuit 201, and B3 and B4 are 1, that is, the letterbox video is multiplexed. , And B2
When several conditions are satisfied, such as the confirmation sine wave being multiplexed in 5 to 27, this composite video signal is sent to EDTV2.
Certify that

The identification signal detection circuit 203 enables the HH reproduction circuit 205 to output the HH signal when the identification signal B10 is 1 (there is an HH signal), and the identification signal B8 is 1 (VT). When there is a signal), it is possible to output the VT signal from the VT reproducing circuit 221, and when the identification signal B9 is 1 (there is a VH signal), the VH reproducing circuit 224 can output the VH signal. And

When the identification signal detection circuit 203 determines that the composite video signal from the tuner circuit 201 is not the EDTV2 signal, the value of each output of the HH reproduction circuit 205, the VT reproduction circuit 221, and the VH reproduction circuit 224 is 0. Become. That is, the HH combiner 206, the VT / VH multiplexing circuit 2
08, identification signal multiplex circuit 209, VT synthesizer 222, V
The H-synthesizers 229 and 230 are in a state of passing the signals of the main line system, and have the configuration of the conventional clear vision receiver. However, if the scanning line number conversion circuit 223 is separately controlled, it can be operated as a zoom function without a vertical reinforcement signal.

[0016]

When the EDTV2 processing is roughly divided as shown in the above-mentioned conventional example, a processing system for demodulating a signal modulated by a color carrier of 3.58 MHz and performing the processing,
There are two processing systems that perform arithmetic processing such as addition and subtraction between horizontal lines. In order to improve the calculation accuracy, it is desirable that each system perform arithmetic processing with a clock synchronized with the burst signal and the horizontal synchronizing signal, and the two processing systems perform signal transfer in the form of analog signals. Further, in the VH reproducing circuit, since the VT signal is reproduced by using the SSKF, it is necessary that the DC level is zero when there is no VT signal.

However, when the A / D conversion is performed again in the above analog signal transfer, it is impossible to suppress the fluctuation of the clamp level to zero including the influence of noise, and the fluctuation of the clamp level causes a DC offset in the VT signal. There is a problem in that the DC offset level difference is reproduced as an uneven luminance between lines when superposed and reproduced by SSKF.

In view of the above-mentioned problems, the present invention provides an EDTV2 receiving circuit capable of accurately reproducing a VT signal without causing luminance unevenness between lines in a VT reproducing process during reception of an EDTV2 broadcast. Is.

[0019]

In order to achieve the above object, an EDTV2 receiving circuit included in a television receiver of the present invention is a vertical time augmented signal (VT signal) reproducing circuit which is a part of EDTV2 signal demodulation processing. A horizontal phase detection circuit for detecting the phase of the horizontal synchronizing signal for each line in the previous stage, and a DC for generating a gate pulse for sampling the input video signal in order to detect the DC offset level of the input video signal in the previous stage of the VT signal reproducing circuit. A level detection gate pulse generation circuit, a cumulative addition circuit whose sampling point is controlled by the DC level detection gate pulse generation circuit, and which accumulates the amplitude level of the video signal to detect the DC offset level in the input video signal, and the cumulative addition circuit. The horizontal scanning line which is obtained by dividing the cumulative video data obtained by A divider used to obtain the DC offset level of the video signal in the video signal, a correction data update timing generation circuit for generating the timing to update the DC offset level of the video signal obtained as the output of the divider, and the correction data. A load / hold circuit which is controlled by the update timing generation circuit and holds the DC offset level of the video signal, and a subtracter which subtracts the output data of the load / hold circuit from the input video signal in the preceding stage of the VT signal reproducing circuit. It is a thing.

[0020]

With the above structure, the present invention can eliminate the DC offset level that is superimposed when data is transferred between the processing system using the burst lock clock and the processing system using the line lock clock. By performing it in the preceding stage of the VT signal reproducing circuit in the processing system, it is possible to obtain an accurate V without causing luminance unevenness between lines due to the influence of the DC offset of the VT signal.
It becomes possible to perform the reproduction processing of the T signal.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An EDTV2 receiving circuit of a television receiver according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a VT reproduction correction circuit 120 according to an embodiment of the present invention. In FIG. 1, reference numeral 1 is a D flip-flop that latches an input video signal to the VT reproduction correction circuit, and 2 is a phase that is a reference of a horizontal phase of each line from the video signal output from the D flip-flop 1 such as a synchronizing signal. A horizontal phase detection circuit 3 for detecting a DC level detection circuit for generating a gate pulse at a sample point of a video signal used for calculating the level of a DC offset determined with respect to the reference phase obtained by the horizontal phase detection circuit 2. A gate pulse generation circuit 4, an adder for accumulating video signal samples in each line, and a reference numeral 5 for controlling the output of the DC level detection gate pulse generation circuit 3 to determine whether or not to accumulate video signals of a certain phase as sample points. Selector for selecting whether or not, 6 is a D flip-flop for latching the selection result of the selector 5, and 7 is a sample number of 1 line Register for storing, D flip-flop 6-8 is the result of cumulatively adding the level of the DC offset of one line
Is divided by the output of the register 7 in which the number of samples is stored to calculate the level of the DC offset in one line, and 9 is the correction data for generating the timing for updating the data of the DC offset obtained by the divider 8. The update timing generation circuit 10 is controlled by the output of the correction data update timing generation circuit 9, and a selector 11 for selecting whether to hold the current DC offset data or to update with the data from the output of the divider 8 is provided. D flip-flop for latching the output of the selector 10, 12 for D
A subtracter 13 that subtracts the output of the D flip-flop 11 from the output video signal of the flip-flop 1 to remove the DC offset from the video signal, and 13 is a D flip-flop that latches the output of the subtractor.

The operation of the VT reproduction correction circuit 120 according to the embodiment of the present invention configured as described above will be described below. First, in order to calculate the superimposed DC offset level from the input video signal, the horizontal phase detection circuit 2 finds a point serving as a phase reference in a horizontal line such as a synchronization signal. Next, based on the obtained phase reference, the DC level detection gate pulse generating circuit 3 and the accumulators of the circuits 4 to 6 sample a plurality of video signals at positions where the VT signal is not superimposed, such as a back porch, and accumulate them. Calculate the DC offset level. Further, the divider 8 accumulates D
The C offset level is divided by the number of samples to obtain the average value of the DC offset level of a certain line. Average D
After the C offset level is calculated, the average D is calculated line by line at the timing of the correction data update timing generation circuit 9.
By updating the C offset level and subtracting this average DC offset level from the input video signal in the entire period including the video period in which the VT signal is superimposed,
The DC offset component superimposed on the input video signal can be removed. This series of processing is performed in units of horizontal lines.

Next, the EDTV2 receiving circuit in one embodiment of the present invention including the VT reproduction correction circuit 120 will be described. FIG. 2 shows an EDTV 2 according to an embodiment of the present invention.
It is a block diagram of a receiving circuit. In FIG. 2, 101 is a tuner circuit that receives and selects broadcasts, detects video, and outputs a composite video signal, 102 is an A / D converter that converts the composite video signal output from the tuner circuit 101 into a digital signal, and 103 is A The identification signal detection circuit connected to the output terminal of the D / D converter 102 detects the EDTV2 identification signal multiplexed in the 22nd and 285th horizontal scanning periods of the horizontal scanning period of 525 lines / frame of the NTSC signal. It is a circuit to do. A three-dimensional Y / C separation circuit 104 is connected to the output terminal of the A / D converter 102 and separates and extracts a luminance signal and a chrominance signal by motion adaptive processing. Reference numeral 105 denotes an HH reproducing circuit, which further modulates the color signal extracted by the three-dimensional Y / C separation circuit 104 by field difference to obtain a modulated HH.
The signal and the color signal are separated, and the HH signal is reproduced by multiplying the blown-out carrier extracted by the identification signal detection circuit 103 and the modulated HH signal. Reference numeral 106 denotes an HH combiner for adding the 4.2 MHz or lower component of the luminance signal output from the three-dimensional Y / C separation circuit 104 and the 4.2 to 6 MHz band component of the HH signal output from the HH reproduction circuit 105. 1
Reference numeral 07 is a VT / VH demodulation circuit that demodulates a VT / VH signal that is modulated by a color carrier of 3.58 MHz and is multiplexed in the upper and lower non-picture portions, and 108 is V demodulated by the VT / VH demodulation circuit 107.
VT /, which multiplexes the T / VH signal with the luminance signals of the upper and lower non-image areas
VH multiplex circuit, 109 is VT / VH for EDTV2 identification signals such as B8 and B9 detected by the identification signal detection circuit 103.
Similar to the multiplexing circuit 108, an identification signal multiplexing circuit that multiplexes the luminance signals of 22H and 285H, and 110 is the HH reproducing circuit 10.
5 is a color demodulation circuit that demodulates the color signal extracted in 5 and time-division-multiplexes two color signals to output. Reference numeral 111 is a D / A converter for converting the digital signals of luminance and color output from the identification signal multiplex circuit 109 and the color demodulation circuit 110, and 112 is a clock serving as a reference timing for the operation of the digital signal processing circuits 102 to 111. Is a burst lock clock generation circuit for generating a signal, 113 is an analog luminance signal which is an output of the D / A converter 111, an A / D converter which converts a color difference signal into a digital signal, and 114 is a clear vision receiver or the like. The A / D converter 113 is a motion adaptive scanning line interpolation circuit that creates a sequential scanning signal from the interlaced scanning signal that is present.
The luminance signal and color difference signal output from the
6 luminance current line signal, 117 luminance interpolation line signal,
Four signals of the color difference current line signal 118 and the color difference interpolation line signal 119 are output.

Reference numeral 115 is a VT / VH separation circuit connected to the luminance signal output terminal of the A / D converter 113, which uses the frame difference to multiplex the VT signal and VH in the upper and lower non-image areas.
Separate the signals. Reference numeral 120 denotes the VT reproduction correction circuit described above, which is connected to the output terminal of the VT / VH separation circuit 115.
The DC offset component superimposed on the VT signal is removed.
Reference numeral 121 is a VT reproduction circuit connected to the output terminal of the VT reproduction correction circuit 120, and reproduces the VT signal using SSKF. A VT synthesizer 122 adds the high frequency component of the luminance interpolation line signal 117 output from the motion adaptive scanning line interpolation circuit 114 and the low frequency component of the VT signal output from the VT reproduction circuit 121. Reference numeral 124 is a VH reproducing circuit, and VT /
The VH signal is reproduced from the signal separated and output by the VH separation circuit 115.

Reference numeral 123 is a scanning line number conversion circuit composed of a field memory and a vertical filter.
The number of 0 scanning lines is multiplied by 4/3 to synthesize 480 scanning lines, and 125 luminance current line signals, 126 luminance interpolation line signals, 127 color difference current line signals, and 128 color difference interpolation line signals are combined. Outputs four kinds of signals. 129 and 130 are V
The H combiner adds the VH signal output from the VH reproduction circuit 124 to each of the luminance current line signal 125 and the luminance interpolation line signal 126 output from the scanning line number conversion circuit 123.

Reference numeral 131 denotes a double speed conversion circuit composed of a line memory, which sequentially generates a scanning luminance signal from the luminance current line signal output from the VH synthesizer 129 and the luminance interpolation line signal output from the VH synthesizer 130. , The color difference current line signal 127 output from the scanning line number conversion circuit 123
And a color difference interpolation line signal 128 are used to sequentially generate a scan color difference signal. Reference numeral 132 denotes a D / A converter connected to the output of the double speed conversion circuit 131, which outputs a luminance signal for progressive scanning and two color difference signals. Reference numeral 133 is a line lock clock generation circuit that generates a clock that serves as a reference timing for the operation of the digital signal processing circuits 113 to 132.

Reference numeral 134 is an RGB processing circuit for synthesizing RGB signals by matrix calculation from the signal output from the D / A converter 132, and 135 is a display for displaying the output of the RGB processing circuit 134. The aspect ratio of the screen is 16 :. It is 9.

The operation of the EDTV2 receiving circuit according to the embodiment of the present invention constructed as above will be described below. First, the identification signal detection circuit 103 detects the identification signal multiplexed on the scanning line numbers 22 and 285 of the composite video signal from the tuner circuit 101, and B3 and B4 are 1, that is, the letterbox image is multiplexed. Further, when some conditions are satisfied such that the sine wave for confirmation is multiplexed on B25 to B27, this composite video signal is identified as EDTV2.

Then, the identification signal detection circuit 103 enables the HH reproduction circuit 105 to output the HH signal when the identification signal B10 is 1 (there is an HH signal), and the identification signal B8 is 1 (VT). When the signal is present, it is possible to output the VT signal from the VT reproducing circuit 121. When the identification signal B9 is 1 (the VH signal is present), the VH reproducing circuit 124 can output the VH signal. And

When the identification signal detection circuit 103 determines that the composite video signal from the tuner circuit 101 is not the EDTV2 signal, the value of each output of the HH reproduction circuit 105, the VT reproduction circuit 121 and the VH reproduction circuit 124 is 0. Become. That is, the HH combiner 106, the VT / VH multiplexing circuit 1
08, identification signal multiplexing circuit 109, VT synthesizer 122, V
The H combiners 129 and 130 are in a state of passing signals of the main line system, and have the configuration of the conventional clear vision receiver. However, if the scanning line number conversion circuit 123 is separately controlled, it can be operated as a zoom function without a vertical reinforcement signal.

[0031]

As described above, according to the television receiver of the present invention, the horizontal synchronizing signal for each line is provided in the preceding stage of the vertical time enhancement signal (VT signal) reproducing circuit which is a part of the EDTV2 signal demodulating process. A horizontal phase detection circuit for detecting the phase of the input video signal, and a DC level detection gate pulse generation circuit for generating a gate pulse for sampling the input video signal in order to detect the DC offset level of the input video signal in the preceding stage of the VT signal reproduction circuit, A cumulative addition circuit for controlling the sampling point by the DC level detection gate pulse generation circuit to accumulate the amplitude level of the video signal for detecting the DC offset level in the input video signal, and cumulative video data obtained by the cumulative addition circuit. Video signal D on a horizontal scan line divided by the number of samples
A divider used to obtain the C offset level, a correction data update timing generation circuit for generating the timing for updating the DC offset level of the video signal obtained as the output of the divider, and the correction data update timing generation circuit. By providing a load / hold circuit that holds the DC offset level of the video signal that is controlled and a subtracter that subtracts the output data of the load / hold circuit from the input video signal in the preceding stage of the VT signal reproducing circuit, the VT D in the input video signal to the signal reproduction circuit
It becomes possible to remove the C offset level, and as a negative effect, it is possible to prevent the luminance unevenness that has been generated in the line unit at the time of reproducing the VT signal, the signal is reproduced accurately, and a high-definition image is displayed. It becomes possible to provide.

[Brief description of drawings]

FIG. 1 is a block diagram of a VT correction circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram of an EDTV2 receiving circuit according to an embodiment of the present invention.

FIG. 3 is a block diagram of a conventional EDTV2 receiving circuit.

FIG. 4 is a schematic diagram for explaining a method of multiplexing video signals of EDTV2 broadcasting system.

FIG. 5 is a waveform diagram of an EDTV2 identification signal.

[Explanation of symbols]

 1, 6, 11, 13 D Flip-Flop Circuit 2 Horizontal Phase Detection Circuit 3 DC Level Detection Gate Pulse Generation Circuit 4 Adder 5, 10 Selector 7 Constant 8 Divider 9 Correction Data Update Timing Generation Circuit 12 Subtractor 101 Tuner Circuit 102 , 113, 202, 213 A / D converter 103 Identification signal detection circuit 104 Three-dimensional Y / C separation circuit 105 HH reproduction circuit 106 HH combiner 107 VT / VH demodulation circuit 108 VT / VH multiplexing circuit 109 Identification signal multiplexing circuit 110 Color demodulation circuit 111, 132 D / A converter 112 Burst lock clock generation circuit 114 Motion adaptive scanning line interpolation circuit 115 VT / VH separation circuit 120 VT reproduction correction circuit 121 VT reproduction circuit 122 VT synthesizer 123 Scan line number conversion circuit 124 VH reproduction circuit 129, 13 VH combiner 131 double speed conversion circuit 133 line-locked clock generation circuit 134 RGB processing circuit 135 Display

Front page continuation (72) Inventor Hiroshi Nio 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Toshiaki Kitahara 1006, Kadoma, Kadoma City, Osaka Prefecture (72) Invention Yuuki Urakawa Address 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Kenichiro Hayashi, 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (1)

[Claims] 1. A horizontal phase detection circuit for detecting a phase of a horizontal synchronizing signal for each line in a front stage of a vertical time reinforcement signal (VT signal) reproduction circuit which is a part of EDTV2 signal demodulation processing, and a front stage of the VT signal reproduction circuit. A DC level detection gate pulse generation circuit for generating a gate pulse for sampling the input video signal to detect a DC offset level of the input video signal, and a sampling point controlled by the DC level detection gate pulse generation circuit in the input video signal. A cumulative addition circuit that accumulates the amplitude level of the video signal for detecting the DC offset level, and the cumulative video data obtained by the cumulative addition circuit is divided by the number of samples to obtain the DC offset level of the video signal in a certain horizontal scanning line. The divider used to obtain the above divider output A correction data update timing generation circuit that generates a timing for updating the DC offset level of the video signal, a load / hold circuit that holds the DC offset level of the video signal controlled by the correction data update timing generation circuit, and the load / load circuit. When the VT signal is reproduced, the output data of the hold circuit is subtracted from the input video signal in the preceding stage of the VT signal reproduction circuit, and a DC offset level in the input video signal to the VT signal reproduction circuit is removed. A television receiver characterized by preventing the occurrence of luminance unevenness on a line-by-line basis.