JPH07226925A - Television receiver - Google Patents

Abstract

PURPOSE:To reduce the hardware configuration by realizing the configuration receptible of a laterally long broadcast signal and an existing broadcast signal so as to reduce the number of memories in use. CONSTITUTION:A field double scan motion detection circuit 302 in the color signal processing system acts like a picture motion detection section in the case of processing a laterally long broadcast signal processing and acts like a field double scanning section in the case of processing an existing broadcast signal. Furthermore, a sequential scanning conversion field double scanning section 303 in the luminance signal processing system acts like a sequential scanning conversion section in the case of processing the laterally long broadcast signal and acts like a field double scanning section in the case of processing the existing broadcast signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television receiver.

[0002]

2. Description of the Related Art When a horizontally long screen having an aspect ratio of 16: 9 is photographed by a camera and displayed on a display having an aspect ratio of 4: 3, the circularity cannot be maintained and a circular object becomes a vertically long ellipse. That is, the compatibility between the landscape broadcast and the current receiver cannot be obtained as it is. To avoid this problem, the feed side compresses a horizontally long image 3/4 times in the vertical direction, and there is a non-image part at the top and bottom of the display (there are black bars at the top and bottom of the screen, A letterbox method of transmitting and receiving a signal has been proposed.

In the letterbox system, a signal having an aspect ratio of 16: 9 and N scanning lines (N is an integer) is compressed into M lines (M is an integer), and the compressed signals are displayed on the screen. It is located in the center. The signal lost by this compression processing is used as a compensation signal in the upper and lower non-picture parts (NM).
This is used for reproducing the original signals of N scanning lines.

FIG. 5 shows the number of scanning lines in the letterbox system, which is four.
A block diagram for encoding signals of 80 lines and a frame frequency of 1/60 [sec] is shown. In addition, FIG.
Shows a block diagram for decoding an input signal to obtain a progressive scanning signal with 480 scanning lines and a frame frequency of 1/60 [sec].

In FIG. 5, input terminals 101, 102, 1
The R, G, and B signals respectively input to 03 are matrix-converted by the matrix circuit 104, converted into Y, I, and Q signals and output. The control signal generator 129 generates various timing signals required by the system based on the horizontal synchronizing signal H and the vertical synchronizing signal V.

The I signal is a vertical low pass filter (VL).
PF) 117 is band-limited, and interlaced scanning converter 119
Then, the progressive scanning signal having the frame frequency of 1/60 [sec] is converted into the interlaced scanning signal having the frame frequency of 1/30 [sec]. The I signal thus converted into the interlaced scan is vertically compressed 3/4 times by the 4 → 3 converter 121, and the effective scanning line number 360 is converted from the signal of 480 effective scanning lines [lines / frame]. Converted to a [book / frame] signal. The output of the 4 → 3 converter 121 is input to the horizontal low-pass filter (H-LPF) 123, band-limited in the horizontal direction, and input to the multiplier 125. In the multiplier 125, the carrier (cos2πf) from the control signal generator 129 is transmitted.
Sct) is modulated with the I signal.

The Q signal is a V-LPF 118, an interlaced scanning converter 120, a 4 → 3 converter 122, and an H-LPF 124.
Processing similar to that for the I signal is performed, and the number of effective scanning lines is 360
[Book / frame], frame frequency 1/30 [sec]
Which is the interlaced scanning signal and is input to the multiplier 126.
The multiplier 126 modulates the carrier wave (sin2πfsct) from the control signal generator 129 with the Q signal. The modulated I signal and Q signal are added by the adder 127,
The C signal is input to the adder 115.

On the other hand, the Y signal output from the matrix circuit 104 is input to the motion detection circuit 141, the vertical low pass filter (V-LPF) 105, and the vertical high pass filter (V-HPF) 131. Motion detection circuit 14
In 1, the motion of the image is detected using the Y signal and the motion detection signal is output. This motion detection signal is sent to the 4 → 3 converter 14
2 is vertically compressed to 3/4 times, and then the interlaced scanning converter 143 converts the progressive scanning signal into an interlaced scanning signal. The number of effective scanning lines is 360 [lines / frame], the frame frequency is 1 / It is converted into a signal of 30 [sec].

The V-HPF 131 extracts the vertical high frequency component (VH signal) of the Y signal. The extracted VH signal is shifted to the vertical low frequency band by the vertical shift over furnace 132, and 4
→ 3 converter 133 compresses 3/4 times in the vertical direction, effective scanning line number 360 [lines / frame], frame frequency 1
It is converted into a progressive scanning signal of / 60 [sec]. This 4
The → 3 converted signal is input to the frame inverting circuit 134 and inverted every other frame. The interlaced scanning converter 135 converts the frame-inverted signal from a sequential scanning signal into an interlaced scanning signal, and the effective scanning line number is 360 [lines / line].
Frame] and a frame frequency of 1/30 [sec]. This signal is sent to the H-LPF 136 and the switch 14
4 is input to the adder 137 described later.

The V-LPF 105 band-limits the Y signal in the vertical direction. The band-limited signal is vertically compressed 3/4 times by the 4 → 3 converter 106, the number of effective scanning lines is 480 [lines / frame], and the frame frequency is 1/60 [s].
ec] sequential scanning signal, the effective scanning line number is 360 [lines /
Frame], and a progressive scanning signal having a frame frequency of 1/60 [sec]. The output of the 4 → 3 converter 106 is
It is input to the V-LPF 107 and the V-HPF 108.

In the V-LPF 107, the 4 → 3 converter 10
The output of 6 is band-limited in the vertical direction, and the band-limited Y signal is converted by the interlaced scan converter 109 from a sequential scanning signal to an interlaced scanning signal. The output of the interlaced scan converter 109 is input to the adder 115. The V-HPF 108 extracts the vertical high frequency components of the output of the 4 → 3 converter 106, and the extracted Y signal is converted by the interlaced scan converter 110 from a sequential scanning signal to an interlaced scanning signal. The output of the interlaced scanning converter 110 is band-limited in the horizontal direction by the H-LPF 111 and input to the adder 137.

The VH signal band-limited by the H-LPF 136 is input to the adder 137 via the switch 114, which is determined to be a still image based on the motion detection signal from the motion detecting means. Turn on only when
In the adder 137, the VH signal passed through the switch 114 and the Y signal in the vertical high range are added, and the addition result is input to the time compression rearrangement circuit 112. In the time compression rearrangement circuit 112, time compression in the horizontal direction and rearrangement processing for arranging the compressed signals on the scanning line are performed and processed so as to fit in the upper and lower non-image portions (120 [lines / frame]). It

In the adder 115, the Y signal converted into the interlaced scanning and the modulated color signal (C signal) are added to form a signal of the main screen portion of the 4: 3 screen. Adder 115
And the output of the time compression rearrangement circuit 112 are selectively output by the switch 116 according to the timing signal a output from the control signal generation unit 129, and this output becomes an encode output signal.

Next, a decoder for restoring the encoded output signal will be described. Considering an actual receiver, besides decoding the above signals, the aspect ratio is 4:
It is preferable that the three current broadcast signals can also be received. There are various methods of receiving and displaying the current broadcast signal in the decoder. However, as used in the first generation EDTV, the still image part is inter-field interpolated and the moving image part is inter-field interpolated and converted into a progressive scanning signal. For example, the horizontal and vertical deflection systems of the decoder can be used as they are. However, in this method, the image quality can be improved in the still image part, but in the moving image part, the aliasing component due to the interlaced scanning becomes progressively noticeable and deteriorates the image quality, and there is a difference in the image quality between the still image and the moving image. Since it is large, it has the drawback that the transitions look unnatural.

In order to improve such a drawback, there is a method called field double scan in which the field frequency is doubled and displayed in the interlaced scanning state. This method is a method used as a countermeasure against large screen flicker such as the PAL method, and scans as shown in FIG. In this method, the vertical deflection frequency must be doubled, but the horizontal deflection system may be the same as in the case of progressive scanning. Although the image quality is equivalent to that of a conventional interlaced scanning receiver, the system is very simple and requires less hardware because it does not require processing such as motion adaptive operation.

FIG. 6 is a block diagram of a system which is a premise of the present invention. The decoder restores the above-mentioned encoded signal.
It is an example of a television receiver that performs display processing by field double scanning.

The input terminal 201 has an analog digital (A
/ D) The converted television signal is input. The input signal is input to the Y / C separation circuit 202, the multiple signal processing circuit 221, the identification circuit 250, and the synchronization generation circuit 251. The multiple signal processing circuit 221 demodulates and rearranges the signals multiplexed in the upper and lower non-image parts when the horizontal broadcast is received, and converts 120 signals into 360 signals and time-compresses them. Time stretch the signal.
The output signal of the multiple signal processing circuit 221 is supplied to the LD / VH separation circuit 238. LD / VH separation circuit 238
Separates the LD signal and the VH signal.

The VH signal is converted from interlaced scanning into a progressive scanning signal by the progressive scanning converter 239, and 360/2: 1.
Signal becomes 360/1: 1. The signal converted into the progressive scan is input to the 3 → 4 conversion circuit 236, vertically expanded by 4/3 times, and the signal with the effective scanning line number of 360 [lines / frame] is converted into the effective scanning line number of 480 [lines]. / Frame] signal. The line-inversion circuit 237 line-inverts the scanning line number-converted signal, and frequency-shifts it from the vertical low band to the vertical high band. The line-inverted VH signal is input to the adder 214.

L separated by the LD / VH separation circuit 238
The D signal is level 0 every other line in the 0 insertion circuit 233.
Signal is inserted and the interlaced scanning signal of 180 [lines / field] is converted into a progressive scanning signal of 360 [lines / frame]. The 0-inserted signal is input to the vertical high-pass filter (V-HPF) 234, the signal of 0 level is interpolated, and the interpolated signal is input to the adder 235.

The Y / C separation circuit 202 separates the input video signal into a luminance signal Y and a color signal C. The color signal C is
The luminance signal Y input to the color demodulation circuit 241 is supplied to the motion detection circuit 203 and the horizontal low pass filter (H-LPF) 20.
4, the subtractor 207, and the time compression circuit 253.
The color demodulation circuit 214 performs color demodulation processing to obtain an I signal and a Q signal. The I and Q signals are H-LPF242
Band limitation in the horizontal direction by 3 to 4 conversion circuit 2
43 and the time compression circuit 255. In the 3 → 4 conversion circuit 243, a decompression process of 4/3 times is performed in the vertical direction, and the interlace scanning signal of 360 [lines / frame] is used to obtain 48.
Conversion to an interlace scanning signal of 0 [book / frame] is performed. The I / Q signal converted from the number of scanning lines is converted into the double speed conversion circuit 2
At 44, the double speed conversion is performed, and the interlaced scanning signal of 480 [lines / frame] is converted to a progressive scanning signal of 480 [lines / frame]. The double-speed converted I / Q signal is selected by the selecting means 2
It is input to 47. The time compression circuit 255 performs horizontal time compression so that the roundness becomes correct when the current broadcast signal is received, and the field double scan circuit 2
Output to 46. Field double scan circuit 246
, The field frequency is converted from about 60 Hz to 120 Hz, and its output is given to the selection means 247.

The selecting means 247 selects the output of the double speed conversion circuit 244 when the horizontal broadcast signal is received and the output of the field double scan circuit 246 when the current broadcast signal is received, according to the identification result of the identification circuit 250. select.
The output of the selection means 247 is input to the matrix circuit 245.

The discriminating circuit 250 discriminates whether the input signal is the horizontally long broadcast signal or the current broadcast signal, and supplies the discrimination result to the control ends of the synchronization generating circuit 251, the selecting means 247 and the selecting means 252.

The motion detection circuit 203 detects the image motion using the input Y signal. There are various methods for motion detection, but basically, a difference signal between one frame is generated, and when the magnitude of the absolute value is equal to or larger than a certain value, it is determined to be image motion. The generated motion detection signal is provided to the control unit of the progressive scan conversion circuit 208.

The Y signal input to the H-LPF 204 is
The band is limited in the horizontal direction, and its output is the 0 insertion circuit 205.
And to the subtractor 207. The subtractor 207 subtracts the Y signal band-limited by the H-LPF 204 from the original Y signal to extract a horizontal high frequency component. The extracted horizontal high frequency Y signal is input to the progressive scan conversion circuit 208.

FIG. 7 is a diagram for specifically explaining the progressive scan conversion circuit 208. The signal introduced to the input terminal 301 is supplied to the buffer memory 501, the field memory 502, and the interpolation filter 503. The interpolation filter 503 creates an interpolation component using the upper and lower scanning lines. This interpolation component becomes an interpolation component in a moving image. The field memory 502 outputs a signal obtained by delaying the input signal by one field. This signal becomes an interpolation component in the still image. Field memory 502 and interpolation filter 5
The output of 03 is input to the selector 504, and is selectively derived according to the motion detection signal from the motion detection circuit 203.
The output of the selector 504 is input to the double speed conversion circuit 505. The double speed conversion circuit 505 includes a buffer memory 501.
The output of is also input. The double speed conversion circuit 505 converts an input signal into a sequential scanning signal of the effective scanning line 360 [lines / frame] and outputs it. The output of the double speed conversion circuit 505 is
It is input to the adder 212 (FIG. 6) via the output terminal 315.

On the other hand, in the signal input to the 0 insertion circuit 205, the level 0 signal is inserted every other line, and the effective scanning line number is 360 [lines] from the interlaced scanning signal of the effective scanning line number 180 [lines / field]. / Frame] progressive scanning signal. The 0-inserted V-LPF 206 interpolates the signal at the 0 level and inputs it to the adder 235. The adder 235 adds the LD signal and reproduces components up to 360 LPH in the horizontal low range.

The output of the adder 235 is added to the horizontal high-frequency components sequentially converted by the adder 212, and expanded in the vertical direction by 4/3 times in the 3 → 4 conversion circuit 213 to obtain 360.
The [book / frame] signal is converted to a 480 [book / frame] signal. The scan line converted signal is added by the adder 2
At 14, the VH signal is added and the components up to 480 LPH are reproduced. The output of the adder 214 is a luminance signal component when the landscape broadcast is received, and is input to the selection unit 252.

The time compression circuit 253 performs time compression in the horizontal direction so that the roundness does not collapse when the current broadcast is received, and outputs it to the field double scan circuit 254. The field double scan circuit 254 performs the same processing as the field double scan circuit 246 and outputs it to the selection means 252. In the selecting means 252, the adder 214 is used according to the result of the discriminating circuit 250 in the case of the landscape broadcast.
The output of the field double scan circuit 254 is selected for the current broadcast. The output of the selection means 252 is input to the matrix circuit 245.

In the matrix circuit 245, the input Y
.Image processing circuit 24 by converting the I and Q signals into a matrix
Output to 8. The video processing circuit 248 performs inverting amplification and supplies the output to the cathode of the display device 249.

The sync generation circuit 251 generates horizontal and vertical sync signals and outputs horizontal and vertical deflection pulses to the display device 2.
It supplies to the deflection coil of 49. The synchronization generation circuit 251 generates a horizontal variation pulse and supplies it to the horizontal deflection coil of the display device 249. Further, according to the identification result of the identification circuit 250, 60 Hz for landscape broadcasting and 120 for current broadcasting.
The vertical deflection pulse of Hz is output to the display device 249 to the deflection coil.

[0031]

As described above, a television receiver capable of receiving both the horizontally long broadcast signal and the current broadcast signal is conceivable. In the receiver described above, even when the current broadcast signal is received, the fold-back of the moving part is not conspicuous and the switching part between the still image and the moving image does not look unnatural. However, the above configuration requires a large number of memories. The field double scan circuits 246 and 254 and the progressive scan converter 208 each have a capacity of about 1 field and a motion detection circuit 2 respectively.
03 requires a memory of about 1 frame,
The circuit configuration is extremely expensive.

Therefore, an object of the present invention is to provide a television receiver having a structure in which the number of memories used can be reduced as much as possible in order to realize a structure capable of receiving both a horizontally long broadcast signal and a current broadcast signal. And

[0033]

The first aspect of the present invention is the first aspect in which the aspect ratio is 4: 3 and the number of horizontal scanning lines is N (N is an integer).
Of the television signal is compressed into M scanning lines (M is an integer), the component lost by the compression is converted into a compensation signal, and the remaining scanning lines (NM) are multiplexed and jumped. Second television signal sent by scanning and the number of scanning lines N
The receiving means capable of selectively receiving both the book (N is an integer) and the third television signal sent by the interlaced scanning, the storage means, and the receiving means receive the second television signal. When received, the storage means is used to convert the second television signal into a sequential scan and to a signal having N scanning lines, and the compensation signal is reproduced to reproduce the N number of scanning lines. When the first signal processing circuit that synthesizes a signal to generate a first display signal and the receiving means receives the third television signal, the storage means is used to use the third television. And a second signal processing circuit for generating a second display signal by doubling the field frequency of the signal.

[0034]

By the above means, the number of storage means (memory) used can be reduced, and the cost and the hardware can be reduced.

[0035]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention. The same parts as those of the circuit shown in FIG. 6 are designated by the same reference numerals. The part different from the circuit of FIG. 6 will be described.

In this embodiment, a part of the memory of the motion detection circuit 203 (FIG. 6) is shared with the memory used in the field double scan circuit 246, and the memory of the progressive scan conversion circuit 208 (FIG. 6) is field doubled. It is shared with the scan circuit 254. That is, the field double scan / motion detection circuit 302 of FIG. 1 includes the field double scan circuit 246 and the motion detection circuit 20 of FIG.
It has the function of combining 3 and progressive scan conversion in FIG.
The field double scan circuit 303 has the functions of the sequential scan conversion circuit 208 and the field double scan circuit 254 in FIG.

The field double scan / motion detection circuit 302 is supplied with the output of the time compression circuit 255, the Y signal from the Y / C separation circuit 202, and the identification signal obtained by the identification circuit 250. The I signal and Q signal subjected to the field double scan by the field double scan / motion detection circuit 302 are input to the selection means 247.

In the progressive scan conversion / field double scan circuit 303, the horizontal high frequency component from the subtractor 207, the output of the time compression circuit 253, the field double scan / field double scan
The image motion detection signal from the motion detection circuit 302 and the identification signal obtained by the identification circuit 250 are supplied. When the horizontal broadcast signal is being received, the output of the progressive scan conversion / field double scan circuit 303 (luminance signal low frequency component) is supplied to the adder 212. When the current broadcast signal is being received, the field double scan output obtained from the progressive scan conversion / field double scan circuit 303 is supplied to the matrix circuit 245 via the selecting means 252.

That is, the above system is based on the identification circuit 250.
The operation mode is switched according to the identification signal obtained from. The identification signal is the synchronization generation circuit 251, the selection means 24.
7, selection means 252, field double scan / motion detection circuit 302, and progressive scan conversion / field double scan circuit 303.

FIG. 2 shows a specific example of the configuration of the field double scan / motion detection circuit 302 described above.
The I signal from the time compression circuit 255 is input to the input terminal 401.
The Q signal is input to the input terminal 402. The I signal and the Q signal are input to the parallel-serial conversion circuit 405, the I signal and the Q signal are time-axis-multiplexed, and are input to the selecting unit 404. The output of the selection means 404 is supplied to the memory 406. The output of the memory 406 is input to the memory 407 and the serial / parallel conversion circuit 410. On the other hand, Y /
The luminance (Y) signal from the C separation circuit 202 is input to the input terminal 4
03, the selection means 404 and the subtractor 413.
Is being supplied to. At the input terminal 408, the identification circuit 25
The identification signal from 0 is introduced, and the selection means 404,
It is supplied to the control terminal of the memory control circuit 409.

When the horizontal broadcast signal is being received, the selection means 404 is controlled by the identification signal, and the input terminal 40
The Y signal from No. 3 is selected, and the output signal from the parallel-serial conversion circuit 405 is selected when the current broadcast signal is being received. The memory control circuit 409 generates a control signal for the memory 406 in response to the identification signal. When the horizontal broadcast signal is received, the memory 406 controls the memory 406 to function as a 1-field delay line, and controls the current broadcast. When receiving the signal, the memory 406 controls so as to obtain the field double scan function.

In the serial-parallel conversion circuit 410, the time-axis multiplexed I signal and Q signal are separated and led to the output terminal 411 and the output terminal 412, respectively. The memory 407 operates as a 1-field delay line, the output of which is input to the subtractor 413 and is calculated with the signal from the input terminal 403. The subtraction result is a difference signal between one field, which is non-linearly processed by the non-linear circuit 414 and is output to the output terminal 415 as an image motion detection signal.

FIG. 3 shows a specific example of the structure of the progressive scan conversion / field double scan circuit 303. Figure 7
The same parts as those of the progressive scan conversion circuit shown in are denoted by the same reference numerals. The signal from the subtractor 207 is introduced into the input terminal 301, and the buffer memory 501 and the selection means 50 are introduced.
9 is supplied to the interpolation filter 503. Input terminal 507
A signal from the time compression circuit 253 is introduced into the input terminal and is supplied to the selection means 509.

The identification signal from the identification circuit 250 is introduced into the input terminal 508 and is supplied to the control terminal of the selection means 509 and the control terminal of the memory control circuit 511. The selection unit 509, when receiving the horizontal broadcast signal,
The signal from the terminal 301 is selected to select the frame memory 510.
Supply to. At this time, the frame memory 510 is controlled by the memory control circuit 511 so as to function as a 1-field delay line. Frame memory 51
The output of 0 and the interpolation output of the interpolation filter 503 are input to the selection unit 504, selectively derived according to the motion detection signal, and input to the double speed conversion circuit 505. In the double speed conversion circuit 505, the output from the selecting means 504 and the output from the buffer memory 501 are double speed converted and alternately selected and derived, and supplied to the adder 212 via the output terminal 315.

When the current broadcast signal is received, the selection means 509 selects the signal of the terminal 507 to which the output of the time compression circuit 523 is supplied and supplies it to the frame memory 510. At this time, the frame memory 510 is controlled by the memory control circuit 511 so as to have a field double scan function, and its output is supplied to the selecting means 252 via the output terminal 512.

As described above, in this device, the memory necessary for receiving and displaying the horizontally long broadcast signal and the memory necessary for processing and displaying the current broadcast signal by the field double scan are shared. It is configured. This reduces the hardware of the entire device. That is, in FIG. 2, the memory for field double scanning of color signals and the memory for motion detection are shared.
Further, in FIG. 3, the memory for the field double scan of the luminance signal and the memory for the progressive scan conversion are shared.

The present invention is not limited to the above embodiment, but a memory for motion detection and a memory for field double scan of luminance signal are shared, and a memory for progressive scan conversion and a field double scan of color signal are shared. The memory for use may be shared. Also, the memory for motion detection is 1
Since the memory has a capacity for frames, all the memory for field double scan of the luminance signal and the chrominance signal may be shared with the memory for motion detection.

[0048]

As described above, according to the present invention,
In order to realize a configuration capable of receiving both the horizontal broadcast signal and the current broadcast signal, the number of memories used can be reduced and the hardware configuration can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram specifically showing an example of the field double scan / motion detection circuit of FIG.

FIG. 3 is a diagram specifically showing an example of the progressive scan conversion / field double scan circuit of FIG. 1;

FIG. 4 is an explanatory diagram of field double scan.

FIG. 5 is a diagram showing an encoder for obtaining a letterbox type signal.

FIG. 6 is a diagram showing a decoder for letterbox type signals.

FIG. 7 is a diagram showing a progressive scan conversion circuit.

[Explanation of symbols]

202 ... Y / C separation circuit, 204 ... H-LPF (horizontal low-pass filter), 205 ... 0 insertion circuit, 206 ... V-
LPF (vertical low pass filter), 207 ... Subtractor, 2
12 ... Adder, 213 ... 3 → 4 converter, 214 ... Adder, 221 ... Multiple signal processing circuit, 233 ... 0 insertion circuit,
234 ... V-HPF (vertical high pass filter), 235
... adder, 236 ... 3 → 4 converter, 237 ... line inversion circuit, 238 ... LD / VH separation circuit, 239 ... progressive scan conversion circuit, 241 ... demodulation circuit, 242 ... H-LPF (horizontal low-pass filter) 243 ... 3 → 4 converter, 244
... Double speed conversion circuit, 245 ... Matrix circuit, 247 ...
Selection means, 248 ... video processing circuit, 249 ... display device,
250 ... Identification circuit, 251 ... Sync generation circuit, 252 ... Selection means, 253, 255 ... Time compression circuit, 302 ... Field double scan / motion detection circuit, 303 ... Sequential scan conversion / Field double scan circuit.

Claims (3)

[Claims] 1. A first television signal having a number N of scanning lines (N is an integer) having an aspect ratio of 4: 3 or longer is compressed into a number M of scanning lines (M is an integer), and is lost by the compression. The number of scanning lines remaining (NM)
The second television signal that is multiplexed on a book and is transmitted by interlaced scanning, the number of scanning lines N (N is an integer), and the third television signal that is transmitted by interlaced scanning are both selective. When the receiving means receives the second television signal, the storage means is used to convert the second television signal into sequential scanning, And a first signal processing circuit for converting the signal into a signal of N scanning lines and reproducing the compensation signal to synthesize the N signals to generate a first display signal; A second signal processing circuit which, when receiving the third television signal, doubles the field frequency of the third television signal using the storage means to generate a second display signal; Equipped with a television Receiver. 2. When the second television signal is received in the storage means, the high frequency component of the luminance signal is introduced, and when the third television signal is received. The television receiver according to claim 1, wherein a signal obtained by time-compressing the luminance signal is introduced. 3. The second storage means, and when the receiving means receives the second television signal, the second storage means is used to store image motion information of the second television signal. Then, when it is given to the first signal processing circuit and the receiving means receives the third television signal, the second storage means is used to relate the color signal of the third television signal. A third field frequency is converted and added to the second display signal.
2. The television receiver according to claim 1, further comprising a signal processing circuit according to claim 1.