JPH08186769A - Driving voltage pulse generation device for solid state image pickup device - Google Patents

Abstract

PURPOSE: To provide a driving voltage pulse generation device which has the large driving capability and generates a voltage pulse of a sufficiently high level that is applied to a drive control electrode which controls the signal charge shift of a CCD device. CONSTITUTION: The boosting modules m1 to m3 consist plural stages of charge pumps consisting of capacitors 25 to 27 and the transistors TR 22 to 24 whose gates and input terminals are connected to one of both ends of each of capacitors 25 to 27 respectively. Then the voltage pulses P4 to P6 are supplied in a period when the drive control voltage should be supplied to the electrode of a CCD device so that the TR 22 to 24 are alternately turned on and off. The capacitor Co placed at the output terminal of the boosting modules is boosted by the charge pumps. However, the capacitor Co is discharged out of the preceding supply period of the drive control voltage and a high driving voltage pulse is produced. Therefore, a boosted voltage pulse is obtained at the output terminal of the boosting module of the final stage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CC such as a solid-state image pickup device.
A drive voltage pulse generator for generating a drive voltage pulse applied to a charge transfer electrode in a D device, and in particular, C
The present invention relates to a drive voltage pulse generator that boosts a low power supply voltage externally supplied to a CD device to obtain a drive voltage pulse having a high voltage.

[0002]

2. Description of the Related Art An example of a drive voltage pulse generator used in a conventional solid-state image pickup device will be described. FIG.
1 schematically shows a solid-state image pickup device in which a drive voltage pulse generator is used, and a photodiode 10 for converting an optical image projected by an optical system (not shown) into a signal charge.
A large number of 0s are arranged in a line on a semiconductor substrate (not shown).
The signal charges generated in each of the photodiodes 100 are transferred to the shift gates 20 arranged along the diode row.
It is simultaneously transferred to the CCD register 300 via 0.
The CCD register 300 sequentially transfers the transferred signal charge group toward the output circuit 400. The output circuit 400 converts the signal charge into an image signal and outputs it.

In solid-state image pickup devices such as CCD image sensors, the power supply voltage is being reduced. However, it is necessary to apply a pulse voltage higher than the power supply voltage to the electrode group (not shown) that controls the charge transfer formed in the shift gate 200, the CCD register 300, and the like. Therefore, a device for boosting a low power supply voltage supplied from the outside to obtain a high control voltage is required.

For example, in the area of the shift gate 200, the electrodes of the shift gate and the electrodes of the CCD register for transferring charges are intricate, and the electrode of the shift gate 200 arranged above has a higher pulse voltage. Is required.

Therefore, inside the apparatus, as shown in FIG.
A pulse booster is provided. In the figure, an N-type MOS transistor 11 is connected between a node (connection point) No and a power supply VA. The capacitor 12 is connected between the terminal T1 and the node No. The N-type MOS transistor 13 is connected between the node No and the ground potential Vss. The node No is a node that can obtain a boosted voltage,
It serves as a voltage source for supplying the drive voltage Vo to the transfer control electrode for the signal charge (not shown).

In such a configuration, as shown in FIG.
Voltage pulses P1 to P3 from the gate voltage pulse generating circuit (not shown) as boosting pulses are respectively generated in the MOS transistor 1.
1, the terminal T1 and the MOS transistor 13 are sequentially supplied. First, the voltage pulse P1 changes to the MOS transistor 1
When applied to the gate of the transistor 1, the transistor 11 becomes conductive and the capacitor 12 is charged with the electric potential V1 of the power supply VA. As a result, the potential Vo of the node No is
Rises from the ground potential Vss to approximately V1.

The voltage pulse P1 disappears and the transistor 1
After 1 becomes non-conductive, the voltage pulse P2 is applied to the terminal T1. Depending on the amplitude V2 of the voltage pulse P2, the node N
The potential Vo of o rises to about (V1 + V2). When the voltage pulse P2 disappears, the potential of the node No becomes V1, and then the voltage pulse P3 changes to the MOS transistor 13
Applied to the gate of. By applying the voltage pulse P3,
The transistor 13 is turned on to discharge the charge stored in the capacitor and reset the node No to the ground potential Vss.

By such an operation, it is possible to obtain a voltage boosted to the node No, a drive voltage pulse having an amplitude of approximately (V1 + V2).

[0009]

However, in the conventional pulse booster, if the power source VA and the original power source of the pulse generating circuit for generating the pulses P1 to P3 are common, the boosted voltage Vo obtained at the node No is , About twice the potential V1 and the pulse amplitude V2. In this case, the voltage value may be insufficient. In addition, solid-state imaging device (CCD device)
Then, the capacitance of the electrode serving as a load is as large as several hundreds of pF. In this case, the capacitance of the capacitor 12 that holds the potential of the node No must be increased, but it may be difficult to provide a large-capacity booster inside a device such as a solid-state imaging device.

Therefore, according to the present invention, a solid-state image pickup device (C) which generates a sufficiently large boosted voltage and has a large driving capability is provided.
It is an object of the present invention to provide a drive voltage pulse generator for a CD device).

[0011]

To achieve the above object, a drive voltage pulse generator for a solid-state image pickup device according to the present invention includes a plurality of drive voltage pulse generators arranged to transfer signal charges in a predetermined direction in the solid-state image pickup device. In a drive voltage pulse generator for a solid-state imaging device that supplies a drive voltage pulse to a transfer electrode, the amplitude is at a first level during the period when the drive voltage pulse is to be output to the output terminal of the device, and during the other periods. A pulse voltage generator that generates a reset pulse that becomes a second level and a boosting pulse in which a plurality of voltage pulses are aligned while the reset pulse is at the first level, and a plurality of pulse voltage generators that are connected in series with each other. The charge pump circuit is configured to receive the boosting pulse and stepwise boost a predetermined voltage supplied to the input end to form the drive voltage pulse at the output end. And a reset unit for setting the output terminal to a predetermined reference potential while the reset pulse is at the second level. Further, the driving voltage pulse of the CCD device of the present invention is provided. The generator is a drive voltage pulse generator for a CCD device that supplies drive voltage pulses to a plurality of transfer electrodes arranged to transfer signal charges in a predetermined direction in a charge transfer path in the CCD device. A reset pulse whose amplitude is at a first level during the period in which the drive voltage pulse is to be output, and is at a second level during other periods, and a plurality of pulses while the reset pulse is at the first level. Of the boosting pulse, and a plurality of charge pump circuits connected in series with each other. Of a predetermined voltage supplied to an input terminal in response to the supply of the voltage, and a step-up unit that forms the drive voltage pulse at the output terminal, and the output while the reset pulse is at the second level. And a reset unit that sets the end to a predetermined reference potential.

[0012]

The booster is composed of the charge pumps connected in the required number corresponding to the required output voltage. During the period in which the drive voltage pulse is to be output to the electrode of the CCD device or the like, a plurality of voltage pulses for the boosting operation are supplied to the charge pump to boost the output voltage of the boosting unit. After the lapse of the above period, the output voltage is reset to a predetermined level to obtain a drive voltage pulse having a relatively high voltage.

[0013]

Embodiments of the present invention will be described below. FIG. 1 shows an embodiment of the present invention, which is roughly divided into a power supply unit 1, a boosting unit 2, a reset unit 3, and a pulse voltage generating unit 4. The power supply unit 1 is a (external) constant voltage source V
A and an N-type MOS transistor 21 which is diode-connected to the power supply VA via the terminal T2. The booster 2 is connected in series with a diode between the transistor 21 and the node No. The N-type MOS transistors 22 to 24 are connected at one end to the connection point (node) N1 of the transistors 21 and 22 and the gate of the transistor 22. , A capacitor 2 to which the voltage pulse P5 is applied to the other end
5, a capacitor 26 having one end connected to the connection point N2 of the transistors 22 and 23 and the gate of the transistor 23, and the voltage pulse P6 applied to the other end, and one end of the connection point N3 of the transistors 23 and 24 and the transistor 24. The capacitor 27 is connected to the gate and the voltage pulse P7 is applied to the other end. Capacitor 25
To 27 are formed in the same capacity, for example.

The booster unit 2 has a structure in which a plurality of booster modules m1 to m3 each including a pair of a capacitor and a transistor are connected in cascade, and the booster units 2 are provided in the number corresponding to a required output pulse voltage.

The reset section 3 is composed of an N-type MOS transistor 28 which connects between the node No and the ground potential Vss in response to the supply of the voltage pulse P8 to the gate. An equivalent capacitance Co due to a wiring capacitance exists at the node No and holds the potential of the node No for a short time. Node N
o is the output terminal of the drive voltage pulse generator, and is connected to the drive electrode of the shift gate 200 of the solid-state imaging device, for example.

The pulse voltage generator 4 generates voltage pulses P5 to P8 as shown in FIG. 2 according to a control sequence (not shown). That is, the voltage pulses P5, P6, and P are generated only while the voltage pulse P8, which is a reset pulse, is at a low level corresponding to the generation period of the drive voltage pulse.
Multiple 7 are generated respectively. The voltage pulses P5 and P7 are in-phase waveforms, and the voltage pulse P6 changes the amplitude complementarily to the voltage pulses P5 and P7. Voltage pulse P
5 to P7 are individually supplied to the gates of the transistors 22 to 24 via the capacitors 25 to 27, respectively. The potential V1 of the power supply VA and the amplitude V of each of the voltage pulses P5 to P7
2 to V4 are set to the same value in this embodiment,
It can be set arbitrarily.

In such a configuration, the voltage pulses P5 to P8 shown in FIG.
8, the capacitors 25 to 27 are supplied, and the odd-numbered transistors and the even-numbered transistors are alternately turned on.
First, the voltage pulse P8 is at the high level except the low level period T1 of the voltage pulse P8 corresponding to the generation period of the drive voltage pulse. In the period other than T1, the transistor 28 becomes conductive, the charge of the capacitor Co is discharged to the ground power supply, and the voltage Vo of the node No is pulled to the reference potential Vss. In the state where the voltage pulse P6 is high level and the voltage pulses P5 and P7 are low level immediately before the period T1, as shown by the solid line in FIG. 1, the charge current flows from the power supply VA toward the capacitor 25 through the transistor 21. Further, a charge current flows through the capacitors 26 and 27 through the transistor 23 by the voltage pulse P6.

During the period T1 of the voltage pulse P8, the voltage pulses P5 and P7 and the voltage pulse P6 are alternately generated.

When the voltage pulses P5 and P7 are at high level and the voltage pulse P6 is at low level within the period T1, as shown by the dotted line in FIG.
A charge current flows toward the transistor 6 through the transistor 22. In addition, a charge current flows from the capacitor 27 toward the capacitor Co through the transistor 24 to raise the potential of the node No.

When the supply of the voltage pulses P5 to P7 from the voltage generator 4 is repeated a plurality of times within the period T1, the above-described boosting operation is repeated and the potential Vo of the capacitor Co rises.

As a result, as shown in FIG.
Potential Vo increases gradually at the timing when the drive voltage pulse should be supplied to the transfer control electrode and the gate electrode (not shown), and a drive voltage pulse having a voltage higher than the original power supply voltage is obtained.

The boosted potential Vo is set after the T1 period has elapsed.
When the voltage pulse P8 becomes high level and the transistor 28 becomes conductive, it is reset to the ground potential. The boosted substantially pulsed voltage Vo is obtained at the output node No. Although the rise of this pulse voltage waveform is stepwise, there is no particular problem as the voltage applied to the charge transfer electrodes of the solid-state imaging device (or CCD device).

By increasing the number of stages of the module m of the booster 2 of the drive voltage pulse generator described above,
It is possible to generate higher desired voltages. Further, by increasing the number of supply pulses of the voltage pulses P5, P6, and P7 in series (increasing the frequency), it is possible to suppress the capacity of the booster unit (charge pump unit) to a small value. This is convenient when the device is provided on a semiconductor chip.

[0024]

As described above, according to the drive voltage pulse generator of the present invention, a high voltage can be easily obtained by increasing the number of stages of the charge pump of the booster. Further, although the electrode capacitance of the solid-state imaging device is as large as several hundreds of pF, the capacitance of the booster unit can be suppressed to a small value by increasing the number of times a series of voltage pulses are supplied, which is advantageous for on-chip implementation. Further, the present apparatus is suitable for boosting a pulse having a relatively long pulse period. Although a voltage pulse with a fast cycle is required, in the solid-state imaging device and other CCD devices, the control electrode pulse that needs to be boosted is often relatively slow, and a high-speed CCD transfer pulse or the like is used as the boost pulse. Since it can be diverted, the burden for driving the booster circuit is small.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a circuit configuration of a pulse booster of the present invention.

FIG. 2 is a waveform diagram showing a signal waveform in each part of the pulse booster circuit.

FIG. 3 is a block diagram showing a configuration example of a solid-state imaging device.

FIG. 4 is a circuit diagram showing a circuit configuration of a conventional pulse booster.

FIG. 5 is a waveform diagram showing signal waveforms of various parts in a conventional pulse booster circuit.

[Explanation of symbols]

 2 booster unit (charge pump unit) 3 reset unit 4 pulse voltage generation unit 21 to 24, 28 MOS transistor 25 to 27 capacitor

Claims (2)

[Claims] 1. A drive voltage pulse generator for a solid-state image pickup device, which supplies a drive voltage pulse to a plurality of transfer electrodes arranged to transfer a signal charge in a predetermined direction in the solid-state image pickup device, the output of the device. A reset pulse whose amplitude is at a first level during the period in which the drive voltage pulse is to be output to the end, and which is at a second level during the other period, and while the reset pulse is at the first level. A predetermined voltage supplied to an input terminal by being supplied with the boosting pulse, which is configured by a pulse voltage generating unit that generates a boosting pulse in which a plurality of voltage pulses are arranged, and a plurality of charge pump circuits connected in series with each other. A step-up unit that steps up the voltage stepwise to form the drive voltage pulse at the output end, and a predetermined reference potential at the output end while the reset pulse is at the second level. Driving voltage pulse generator of the solid-state imaging apparatus characterized by having a reset unit that sets. 2. A drive voltage pulse generator for a CCD device, which supplies a drive voltage pulse to a plurality of transfer electrodes arranged to transfer signal charges in a predetermined direction in a charge transfer path in the CCD device. Of the reset pulse and the reset pulse whose amplitude is at the first level during the period in which the driving voltage pulse is to be output to the output terminal A pulse voltage generator that generates a boosting pulse in which a plurality of voltage pulses are lined up during a period, and a plurality of charge pump circuits connected in series with each other. The boosting pulse is supplied to the input terminal. A boosting unit that boosts a predetermined voltage stepwise to form the drive voltage pulse at the output terminal, and the output terminal at a predetermined level while the reset pulse is at the second level. Driving voltage pulse generator of the CCD device characterized by having a reset unit that sets the quasi potential.