JPH08186488A - Digital circuit, pulse generator, and ccd element - Google Patents

Abstract

PURPOSE: To provide the digital circuit which obtains a stable output independently of the temperature, the element characteristic, and the change of the supply voltage by putting another circuit in a PLL loop. CONSTITUTION: A pulse generator 61 is provided with a PLL circuit 45 and a timing circuit 46 to which the output of this circuit 45 is inputted. The PLL circuit 45 is a 2-multiplier and has a phase comparator 42, a VCO 43, a 1/2 frequency division circuit 44, a low pass filter, etc., as components. The timing circuit 46 is provided with the delay circuit where plural inverters 62 are connected in series and gate circuits 64 and 65 which use the delay in inverters taken out from each array of inverters to perform the gate processing of signals different by phase relations. The output of the inverter array in the preceding stage of the timing circuit 46, namely, a delay wave CL3 from the inverter 62 in the second stage is inputted to the frequency division circuit 44, and the phase of an outputted frequency-divided wave CL5 and that of an external clock signal CL1 are compared with each other by the comparator 42, and the VCO 43 oscillates so that phases coincide with each other. Thus, the input of the PLL circuit 45 and the phase of the timing circuit 46 are kept fixed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital circuit consisting of a PLL circuit and other circuits connected thereto, a pulse generator in which the other circuit is constituted by a timing circuit, and a digital circuit or pulse generator. The present invention relates to a built-in CCD element (for example, CCD delay element, solid-state image sensor, etc.).

[0002]

2. Description of the Related Art Conventionally, a so-called digital circuit consisting of a PLL circuit and other circuits connected thereto has been widely used in various devices, for example, it is also used for generating timing pulses of CCD elements. .

In this PLL circuit and other circuits connected to it, such as a timing circuit, when the timing circuit generates various timing pulses using the delay of the gate, temperature, element characteristics, power supply voltage, etc. Change (variation) changes the delay amount of each gate and changes the phase relationship of each timing pulse with respect to the output of the PLL circuit.

A conventional PLL circuit, that is, as shown in FIG. 8, a phase comparator 2, a VCO (voltage control generator) 3, 1 /
The PLL circuit 1 including the n frequency dividing circuit 4 and a low-pass filter (not shown) as a constituent element supplies the output of the VCO 3 to the frequency dividing circuit 4 to obtain a 1 / n frequency division output, and this output is an input terminal. T ₁
The phase is compared with the external clock input from the phase comparator 2 and locked. Therefore, as a result, the phases of the external clock input, the output of the PLL circuit, the pulse in the PLL circuit, and the pulse in the other circuit 5 independently change due to the temperature or the like, and the influence of the pulse in the PLL circuit is affected. It will be out of 5, causing problems.

A PLL circuit / timing circuit, that is, a pulse generator for generating necessary clock pulses such as a CCD drive clock pulse of the CCD delay element and a sample and hold clock pulse will be specifically described. FIG.
An example of a pulse generator 8 including a conventional PLL circuit 1 and a timing circuit 7 which is another circuit is shown, and FIG. 10 is a timing chart thereof.

The PLL circuit 1 is a frequency doubler and has a phase comparator 2, a VCO 3, a 1/2 frequency divider circuit 4, and a low-pass filter as shown in the figure. On the other hand, the timing circuit 7 has a delay circuit in which a plurality of inverters 8 are connected in series, and the gate circuits 9 and 10 output signals having different phase relations utilizing the delay inside the inverters extracted from the respective inverter rows. Gated through to create the necessary clocks as needed. In this example, four inverters 8 are connected in series and the output signal of the second-stage inverter 8 and the output signal of the fourth-stage inverter 8 are supplied to the first gate circuit (OR circuit) 9. The first timing pulse P ₁ is output from the output terminal 18, and the input signal of the first-stage inverter 8 and the output signal of the second-stage inverter 8 are supplied to the second gate circuit (NAND circuit) 10. Output terminal 20
Therefore, the _second timing pulse P ₂ is output. That is, in this example, the timing pulse generated is of two series.

Therefore, the clock signal oscillated by the VCO 3 is input to the inverter train, and each of them is shown by (14) in the figure.
The first gate circuit 9 and the second gate from the locations (input end of the first-stage inverter), (15) (output end of the second-stage inverter) (16) (output end of the fourth-stage inverter) It is input to the circuit 10. In the pulse generator 8, when the external clock signal CL ₁ is input to the PLL circuit 1, ₂ is output to the output end of the VCO output 3 (hence the input end of the first stage inverter).
A multiplied wave CL ₂ is generated (see the timing chart in FIG. 10). Based on this doubled wave CL ₂ , delay waves CL ₃ and CL ₄ are generated by the inverter train in the timing circuit 7.
The output CL _{2 of the} VCO ₃ and the delayed waves CL ₃ and CL ₄ are used to generate the timing pulses P ₁ and P ₂ .

Since the pulse generator 8 uses the frequency-divided output CL ₅ obtained by dividing the output CL ₂ of the VCO ₃ in half for phase comparison of the PLL circuit 1, the delay amount t in the timing circuit 7 is t. Changes in ₁₁ and t ₁₂ are not considered at all. Therefore, when the phase relationship between the timing pulses P ₁ and P ₂ and the external clock signal CL ₁ does not match as shown by the symbol b in FIG. 10, and the delay amount of the inverter train changes due to temperature or the like. , The phase relationship will change.

In view of the above points, the present invention provides a so-called digital circuit, a pulse generator and a CCD device using these, which can always keep the phase of the input of the PLL circuit and the output of the other circuit constant. Is.

[0010]

A digital circuit 41 according to a first aspect of the present invention comprises a PLL circuit 45, and a PLL circuit 4 of this type.
5 and the other circuit 46 that receives the output of the fifth circuit 5 as an input, and the divider circuit input in the PLL circuit 45 is used as the output of the other circuit 46.

The pulse generator 61 according to the second invention is
It has a PLL circuit 45 and a timing circuit 46 which receives the output of the PLL circuit 45 as an input, and uses the frequency divider circuit input in the PLL circuit 45 as the timing circuit output.
The phase relationship between the 5 input CL ₁ and the timing circuit output CL ₃ is always constant.

The CCD element according to the third aspect of the present invention has a structure in which the digital circuit 41 of the first aspect of the invention or the pulse generator 61 of the second aspect of the invention is incorporated.

[0013]

According to the digital circuit 41 of the first aspect of the present invention, the frequency divider input in the PLL circuit 45 is used as the output of the other circuit 46 to change (variation) in temperature, element characteristics, power supply voltage and the like. Regardless, the effect of the pulse in the PLL circuit 45 does not affect the other circuit 46,
The input signal CL ₁ and the output signal CL ₃ of the other circuit 46 can always be kept constant in phase.

According to the pulse generator 61 according to the second aspect of the present invention, the frequency divider circuit input in the PLL circuit 45 is used as the timing circuit output, so that variations (variations) in temperature, element characteristics, power supply voltage, etc. However, the influence of the pulse in the PLL circuit 45 does not reach the timing circuit, and the PLL circuit 45
The phase relationship between the clock input CL ₁ and the output pulse CL ₃ of the timing circuit 46 can always be kept constant.

According to the CCD element of the third aspect of the present invention,
By incorporating the digital circuit 41 of the first invention or the pulse generator 61 of the second invention, the PLL circuit 4 can be operated regardless of changes (variations) in temperature, element characteristics, power supply voltage and the like.
5 external clock input CL ₁ and, for example, reset pulse P
_a, keeping the sample-and-hold pulse P _b, etc. of the phase of the clock pulses always constant, avoiding the influence of the variation can be always operate normally.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the basic configuration of a digital circuit 41 according to the present invention. The digital circuit 41 includes a phase comparator 42, a VCO 43, a 1 / n frequency dividing circuit 44, and a PLL circuit 45 having a low-pass filter as a constituent element.
The frequency dividing circuit 4 in the PLL circuit 45, which is composed of the other circuit 46.
4 is used as the output of the other circuit 46. That is, the feedback circuit in the PLL circuit 45 is connected to the other circuit 4
It will be done via 6. As a result, the phase relationship between the input signal supplied to the input terminal T ₂ of the PLL circuit 45 and the output signal of the other circuit 46, that is, the output signal of the terminal T ₃ is always kept constant.

Next, the present invention was applied to a CCD delay element.
An example of the case will be described in detail. Figure 2 shows a typical CCD delay element.
The structure of the child 51 is shown, and the input terminal T_FourInput signal from
Signal is input to the CCD register 53 by the input circuit 52.
After being adjusted to a suitable shape, it is input to the CCD register 53.
The number of stages of the CCD register 53, the PLL circuit 45 and others
Generated by the circuit, i.e. the timing generator 46
CCD drive clock pulse φ_XDepending on the driving frequency of
Delay for a fixed amount of time. Output from CCD register 53
The sampled signal is input to the output circuit 54, and the sample signal is output.
Pulse pulse φ_SHSample-held at the timing of
Later, it is amplified and output terminal T _FiveIs output from.

The PLL circuit 45 multiplies the external clock signal CL ₁ input from the input terminal T ₂ by n (n is an integer of 2 or more). The timing generator 46 outputs the external clock signal CL ₁ supplied from the PLL circuit 45.
CCD driving clock pulse φ _X
Generates necessary clock signals such as sample hold clock pulse φ _SH .

FIG. 3 shows a pulse generator 61 comprising a PLL circuit 45 according to the present invention and a timing circuit 46 which is another circuit.
FIG. 4 shows an example of the timing chart.
The PLL circuit 46 is, as described above, a frequency doubler and has a phase comparator 42, a VCO 43, a 1/2 frequency divider circuit 44, and a low-pass filter as shown in the figure. The timing circuit 46 has a delay circuit in which a plurality of inverters 62 are connected in series, and gate circuits 64 and 65 that gate signals having different phase relationships by using the delay inside the inverter 62 extracted from each inverter column. Consists of

In this example, four inverters 62 are connected in series as described above, and the output signal of the second-stage inverter 62 and the output signal of the fourth-stage inverter 62 are connected to the first gate circuit (OR circuit). ) 64 and supplies the input signal of the first-stage inverter 62 and the output signal of the second-stage inverter 62 to the second gate circuit (NAND circuit) 65, and outputs the respective gate circuits 64, 65. It has a two-series configuration in which timing pulses P ₁ and P ₂ (see the timing chart of FIG. 4) having different phase relationships are output from the terminals. 26
Indicates the input end of the first stage inverter, 27 indicates the output end of the second stage inverter, and 28 indicates the output end of the fourth stage inverter.

In this example, the output of the inverter row in the preceding stage of the timing circuit 46, that is, the delayed wave CL ₃ from the inverter 62 in the second stage is input to the 1/2 divider circuit 44 of the PLL circuit 45, and this 1/2 The divided frequency CL ₅ output from the frequency dividing circuit 44 and the external clock signal CL ₁ are compared in phase by the phase comparator 42, and the VCO 43 oscillates so that the phases match each other.

Since the PLL circuit 45 is locked in the timing chart of FIG. 4, the phases of the external clock signal CL ₁ and the divided frequency CL ₅ from the 1/2 frequency dividing circuit 44 match. Further, since the divided frequency CL ₅ is obtained by dividing the delayed wave CL ₃ by 1/2, the rising edges of the delayed wave CL ₃ and the divided frequency CL ₅ also coincide with each other.

FIG. 5 is a timing chart when the delay amount of the inverter array increases due to changes in temperature, power supply voltage, and element characteristics. The delay amounts of the delayed waves CL ₃ and CL ₄ with respect to the output CL _{2 of the} VCO 45 are larger than in the case of FIG. 4 described above (t ₅ , t ₆ <t ₇ , t ₈ ). However, in this embodiment, since the PLL circuit 45 is locked by using the delayed wave CL ₃ , the external clock signal CL ₁ and the delayed wave C
The phase relationship of L ₃ does not change.

On the other hand, since the delayed wave CL ₃ is also used to create the timing pulses P ₁ and P ₂ , the phase relationship between them is always constant, and as a result, the external clock signal CL of the PLL circuit 45 is obtained. ₁ and delayed wave C of timing circuit 46
The phase relationship with L ₃ can be kept constant regardless of the delay amount. Therefore, the phase relationship between the external clock signal CL ₁ and the timing pulses P ₁ and P ₂ is as shown by reference numeral a in FIG. It will be constant regardless of.

The timing charts of FIGS. 4 and 5 show the rising (or falling) of the external clock signal CL ₁ and the clock pulse P ₁ , in order to facilitate understanding of the present invention.
Although the falling edges of P ₂ are made to coincide with each other, for example, in the actual operation of the CCD element, the phase is set so that they do not coincide,
The phase relationship is always kept constant.

FIG. 6 and FIG. 7 show the circuit configuration after the output section of the CCD element and its timing chart when the present invention is applied to the CCD element. CC as shown in FIG.
The CCD output output from the D output unit 71 is sampled and held by a sample hold circuit (the figure shows only MOS transistors as a representative) 73 via a first amplifier 72, and further output via a second amplifier 74. It is taken out as a signal output from T ₇ . A reset pulse P _a supplied to a reset circuit for resetting the CCD output section 71 after the signal charges are read out, and a sample hold pulse P supplied to the sample hold circuit 73.
_b can be obtained by the pulse generator 61 shown in FIG.

As a result, as shown in the timing chart of FIG. 7, the phases of the reset pulse P _a and the sample hold pulse P _b do not match the phase of the frequency division CL ₅ , that is, the pulses P _a and P _b of ₄ Rise, fall, and split frequency C
The rising and falling edges of L ₅ do not coincide with each other, and the phase relationship between them does not change and is always kept constant. Therefore, even if there is a change in temperature, element characteristics, power supply voltage, etc., the phase relationship is constant, so a stable signal output can always be obtained.
In FIG. 7, τ _a indicates the sampling period.

According to the above-described embodiment, by inserting another circuit, such as the timing circuit 46, in the loop of the PLL circuit 45, the PLL circuit 45 can be locked so as to correct the delay generated in the timing circuit 46. it can. As a result, the phase relationship under the center condition is always maintained, and it is possible to manufacture a digital circuit and a pulse generator that are stable with respect to changes (variations) in temperature, element characteristics, and power supply voltage. Further, it can be applied to a CCD element to obtain a reliable signal output.

[0030]

According to the digital circuit including the PLL circuit and the other circuit connected thereto according to the present invention, by inserting the other circuit in the PLL loop, the input of the PLL circuit becomes the phase of the output of the other circuit. The relationship can always be kept constant, and a digital circuit that can obtain a stable output regardless of changes in temperature, element characteristics, and power supply voltage can be created.

According to the pulse generator including the PLL circuit and the timing circuit connected thereto according to the present invention, the PL
By inserting a timing circuit in the L loop, PL
It is possible to maintain a constant phase relationship between the input of the L circuit and the output of the timing circuit, and to make a pulse generator that can obtain a stable pulse signal regardless of changes in temperature, element characteristics, power supply voltage, etc. .

According to the CCD device of the present invention, by incorporating the above digital circuit or pulse generator, the required phase relationship is always kept constant with respect to changes in the power supply voltage, device characteristics, temperature and the like. It is possible to apply a clock pulse (for example, a reset pulse, a sample hold pulse) of, and to provide a highly reliable CCD element that does not disturb the signal output.

[Brief description of drawings]

FIG. 1 is a basic configuration diagram of a digital circuit including a PLL circuit and other circuits according to the present invention.

FIG. 2 is a circuit block diagram inside a CCD delay element according to an embodiment of the present invention.

FIG. 3 is a circuit diagram showing an example of a pulse generator according to the present invention.

FIG. 4 is a timing chart of the pulse generator of FIG.

FIG. 5 is a timing chart when the pulse generators of FIG. 3 have different delay amounts.

FIG. 6 is a configuration diagram of a main part showing an example of a CCD device of the present invention.

7 is a reset pulse P _a , a sample hold pulse P _b of the CCD device of FIG. 6 and a divided frequency CL _{5 of the} pulse generator.
3 is a timing chart showing the relationship with

FIG. 8 is a configuration diagram of a digital circuit including a conventional PLL circuit and other circuits.

FIG. 9 is a circuit diagram of a conventional pulse generator.

10 is a timing chart of the pulse generator of FIG.

[Explanation of symbols]

41 Digital circuit 2,42 Phase comparator 3,43 VCO 4,44 Frequency divider circuit 1,45 PLL circuit 5,46 Other circuit, timing circuit 52 Input circuit 53 CCD register 54 Output circuit 8,61 Pulse generator 62 Inverter 9 , 10, 64, 65 Gate circuit 71 CCD output section 72, 74 Amplifier 73 Sample and hold circuit (only MOS transistors are shown)

Claims (3)

[Claims] 1. A digital circuit, comprising: a PLL circuit; and another circuit which receives an output of the PLL circuit as an input, wherein a frequency divider circuit input in the PLL circuit is used as an output of the other circuit. 2. A PLL circuit and a timing circuit having an output of the PLL circuit as an input, and a frequency divider circuit input in the PLL circuit is an output of the timing circuit, and the P
A pulse generator characterized in that the phase relationship between the input of the LL circuit and the output of the timing circuit is always constant. 3. A CCD device comprising the digital circuit according to claim 1 or the pulse generator according to claim 2 built-in.