JPH08186477A - Timing signal generator - Google Patents

Abstract

PURPOSE: To generate the timing signal which has an arbitrary period to one period of one clock signal. CONSTITUTION: While the timing signal is generated by DFFs 102 and 103, an FF 107 holds the passage state that a CLK signal 104 passes delay gates 106 to 110, and the held passage state of delay gates 106 to 110 and the passage state of delay gates 106 to 110 due to a start signal 121 are compared with each other by a comparator 118. When they coincide with each other, a coincidence signal is outputted, and a DFF 120 outputs an output signal 122, which is synchronized with an arbitrary period to one period of the first clock signal, to a circuit block based on this coincidence signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to electronic circuits such as computers and peripheral equipment, and more particularly to a timing signal generator for generating a desired timing signal for data processing.

[0002]

2. Description of the Related Art Conventionally, in this type of electronic circuit, all operations are controlled based on a timing signal synchronized with a clock signal. Further, the unit of signal change is all performed in the clock cycle.

Further, there are large variations between the minimum and maximum operating times of electronic circuits such as operating temperature conditions of electronic circuits, power supply voltage conditions, and process conditions, and a large design margin is required to ensure accurate operation. I am taking it.

[0004]

However, in the above-mentioned conventional example, firstly, signal delays, pulse widths, etc. less than the clock cycle are created in the clock cycle, resulting in a significant loss of time.

Secondly, in order to increase the speed of electronic circuits, it is necessary to use a faster clock.

Thirdly, a large design margin is required for variations in operating speed caused by operating temperature, operating power supply voltage, process conditions, etc. of semiconductors composed of electronic circuits, which makes high-speed operation difficult. .

Fourth, when the clock itself is synchronized with a certain signal, synchronization is performed with a higher speed clock and the frequency is divided to create a pseudo synchronous clock.

As described above, with the timing signal based on the conventional configuration, it is difficult to increase the speed of the digital circuit, and there are problems such as power consumption and electromagnetic wave emission due to the use of the high speed clock.

The present invention has been made to solve the above problems, and an object of the first to fourth inventions of the present invention is to provide a circuit which receives two asynchronous clock signals. In the block, a timing signal having an arbitrary cycle with respect to one cycle of one clock signal is obtained by adjusting the output timing of the other clock signal so as to have an arbitrary cycle with respect to one cycle of one of the clock signals. Alternatively, it is to provide a timing signal generator capable of generating a pulse signal having an arbitrary cycle width for one cycle of one clock signal.

[0010]

According to a first aspect of the present invention, in an electronic circuit composed of a plurality of circuit blocks, a first clock signal which repeats a signal change at a constant cycle in each circuit block is provided. A clock source or clock input means for oscillating, and a plurality of logic gates for sequentially transmitting the input first clock signal or a second clock signal asynchronous with the first clock signal with a predetermined delay time. , A timing gate for generating a timing signal having an arbitrary cycle with respect to one cycle of the first clock signal, and the first clock signal for each logic gate while the timing signal is generated from the timing gate. Holding means for holding the passing state of passing through the gate, the passing state of the logic gate held by the holding means, and the second clock signal Comparison means for outputting a coincidence signal when a match by comparing the passing state of each logic gate by,
And a signal output gate for outputting to the other circuit block a second clock signal having an arbitrary cycle width for one cycle of the first clock signal based on the coincidence signal from the comparing means.

According to a second aspect of the present invention, in an electronic circuit composed of a plurality of circuit blocks, a clock source or a clock that oscillates a first clock signal that repeats signal changes at a constant cycle in each circuit block. Input means, a plurality of logic gates for sequentially transmitting and outputting the input first clock signal or a second clock signal asynchronous with the first clock signal with a predetermined delay time, and the first clock A timing gate for generating a timing signal having an arbitrary cycle with respect to one cycle of a signal, and a passage state in which the first clock signal passes through each logic gate while the timing gate generates the timing signal. Holding means for holding, detecting means for detecting a change in the passing state of the logic gate held by the holding means, and this detecting means. Selects the second clock signal output from a predetermined number-th logic gates based on passing state change of said detected logic gates and has a selection means for outputting the other circuit blocks.

According to a third aspect of the present invention, in an electronic circuit composed of a plurality of circuit blocks, a clock source or a clock that oscillates a first clock signal that repeats signal changes at a constant cycle in each circuit block. The input means, a plurality of logic gates for sequentially transmitting the input first clock signal with a predetermined delay time, and the first clock signal based on a trigger signal asynchronous with the first clock signal.
Holding means for holding the passing state of the clock signal of each of the logic gates, detecting means for detecting the passing state change of the logic gate held by the holding means, and the logic gate detected by the detecting means Selection means for selecting the first clock signal output from the logic gate of the predetermined number of stages in synchronization with the trigger signal based on the change of the passing state and outputting it to another circuit block.

According to a fourth aspect of the present invention, in an electronic circuit composed of a plurality of circuit blocks, a clock source or a clock that oscillates a first clock signal that repeats a signal change at a constant cycle in each circuit block. The input means, a plurality of logic gates for sequentially transmitting the input first clock signal with a predetermined delay time, and the first clock signal based on a trigger signal asynchronous with the first clock signal.
Holding means for holding the passing state of the clock signal passing through each logic gate, the passing state change of the logic gate held by the holding means and the passing state of the first clock signal sequentially passing through each logic gate. And comparing means for outputting a coincidence signal when they coincide with each other, and based on the coincidence signal from the comparing means, a pulse signal having one cycle width of the first clock from the input of the trigger signal to another And an output gate for sequentially outputting to the circuit block.

[0014]

In the first aspect of the present invention, the holding means holds the passage state in which the first clock signal passes through each logic gate while the timing signal is generated from the timing gate,
When the comparing means compares the held pass state of the logic gate with the pass state of each logic gate by the second clock signal and outputs a match signal when they match, a signal is output based on the match signal. The gate outputs a second clock signal having an arbitrary cycle width to one cycle of the first clock signal to another circuit block, and the first clock signal and the second clock signal asynchronous with the first clock signal are used to output the first clock signal. It is possible to generate a timing signal having an arbitrary cycle width with respect to one cycle of the clock signal.

In the second aspect, while the timing signal is being generated from the timing gate, the holding means holds the passing state of the first clock signal passing through each logic gate, and the held logic gate is held. When the change of the passing state is detected by the detecting means, the selecting means selects the second clock signal output from the logic gate of the predetermined number of stages based on the detected change of the passing state of the logic gate, and the other It is possible to output the pulse signal to the circuit block and generate a pulse signal having an arbitrary cycle width for one cycle of the first clock signal from the second clock signal that is asynchronous with the first clock signal.

[0016] In the third invention, the first means is provided by the holding means.
When the passing state of the first clock signal passing through each logic gate is held based on the trigger signal asynchronous with the clock signal, and the passing state change of the held logic gate is detected by the detecting means, Based on the detected change in the passing state of the logic gate, the selecting means selects the first clock signal output from the logic gate at the predetermined stage number synchronized with the trigger signal, and outputs it to another circuit block. , It is possible to generate a first clock signal that is synchronous with the asynchronous trigger signal.

In a fourth aspect of the present invention, the first holding means is used to hold the first clock signal asynchronously with the first clock signal.
Of the clock signal passing through each logic gate is held, and when the holding state change of the held logic gate is held by the holding means, the passing state change of the held logic gate is sequentially changed. The comparing means outputs a coincidence signal when the passage state of the first clock signal passing through the logic gate is compared and coincides with each other, and the output gate outputs the first signal from the input of the trigger signal based on the coincidence signal. It is possible to sequentially output the pulse signal of one cycle width of the clock to the other circuit block and generate the pulse signal of one cycle width of the first clock signal from the asynchronous trigger signal.

[0018]

【Example】

[First Embodiment] FIG. 1 is a block diagram illustrating a detailed configuration of a signal generating circuit in a timing signal generating device according to a first embodiment of the present invention, and corresponds to, for example, a pulse generating device for generating a timing signal.

In the figure, 101 is a measurement start signal for measuring beforehand the number of passage stages of a reference time of a delegate which is a delay circuit group, and 102 is the measurement start signal 101.
Is a D-type flip-flop (DFF) that synchronizes with the CLK signal 104, 103 is a flip-flop (DFF) that detects one CLK after being set in the flip-flop of the DFF 102, and 104 changes the signal level at a constant cycle. CLK signal, 105 is an OR gate, 106
Denoted by 110 are delay circuit groups each having the same delay characteristic.
Hereinafter referred to as a delay gate.

Reference numerals 111 to 116 denote the delay gate 10 described above.
Output signals 117 of each of 6 to 110 are flip-flops (F) which are storage means for holding the signal levels of the output signals 111 to 116 at a predetermined timing.
F) and 118 are comparators for comparing the value of each signal level held in the FF 117 with the current values of the output signals 111 to 116. When they match, a match signal 119 is generated. 120 is a DFF, which is a signal generation start signal 121
Is a flip-flop that is set by and is reset by the coincidence signal 119, and 122 is an output signal pulse.

In this embodiment, there are two processes for the operation, and the first process is a signal delay measuring process for measuring the delay condition of the delay circuit and storing it in the FF 117.
At the time of initialization and in order to absorb fluctuations in the operating environment, such as temperature fluctuations and voltage fluctuations, which are caused by changes in the operating speed of the delay circuit and peripheral electronic circuits, etc. To be done when the measurement is updated.

It is assumed that the second process is an actual pulse generation process and is not started simultaneously with the first process.

FIG. 2 is a timing chart showing the operation of the signal delay measuring process which is the first process in the signal generating circuit shown in FIG. 1, and the same signals as those in FIG. 1 are designated by the same reference numerals. is there.

In the figure, SF1 is the DFF shown in FIG.
102 is the output of the flip-flop, SF2 is the output of the flip-flop of the DFF 103 shown in FIG.
D10 is an output signal of each stage of the delay gates 106 to 110. Although the number of stages is 6 in the figure, it is needless to say that the number of stages can be increased as shown by "..." in the figure.

Further, T1 and T2 represent the start timing and measurement point of this process, respectively.

That is, this process is S at timing T1.
It is started by setting F1 and the signal of the output SF1 passes through each stage of the delay gate with some delay. Then, the output SF2 is set at the timing T2 after 1 CLK, and the delay situation of the output signals SD1 to SD10 at the moment of the timing T2 is stored in the flip-flop 117 by this signal.

In FIG. 2, the values held in the flip-flop 117 are such that the output signals SD1 to SD8 are at "H" level,
SD9 and later are "L" level. This value indicates the delay gate that has passed during a certain period of time, that is, one cycle of the CLK signal 104, that is, this corresponds to measuring the operating speed of the semiconductor chip that constitutes this circuit. The output signal SF1 is reset at timing T2,
After 1 CLK, the output signal SF2 is reset and the process ends.

FIG. 3 is a timing chart showing the timing of the pulse signal generating process which is the second process in the signal generating circuit shown in FIG. The same components as those in FIGS. 1 and 2 are designated by the same reference numerals.

In the figure, the signal generation start signal 121 is
The signal is input to the clock port of the DFF 120 shown in FIG. 1, and the pulse output is started by the signal.

SF3 is the flip-flop 1 shown in FIG.
20 output signals, which are the same as the output signal 122 shown in FIG.

SD1 to SD10 represent output signals of the respective delay gates. Further, the coincidence signal 119 is output from the comparator 118.

First, when the signal generation start signal 121 is input at the timing U1, the flip-flop 120 is set. This sets the output signal to H at SF3. At the same time, this signal is input to the delay gates 106 to 110 through the OR gate 105, and propagates through each gate with some delay. This is the signal waveform of the output signals SD1 to SD10 shown in FIG.

At this time, the output signals SD1 to SD1 are already output to the flip-flop (FF) 117 by the first process.
SD8 is held at "H" and output signal SD9 and thereafter is held at "L".

Next, at timing U2, the output signal SD8
Becomes “H”, which matches the value held in the FF 117. At this time, the comparator 118 outputs the coincidence signal 119, the flip-flop 120 is reset, and the output signal S
F3 is reset and the output signal 122 is reset to "L". Here, the time from when the output signal SF3 is set to when the output signal SD8 becomes “H” is equal to the time from timing T1 to T2 in FIG.

Therefore, the pulse width of the output signal (the pulse width defined by the timings U1 and U2) is equal to one cycle of the clock signal (CLK signal) 104.

As described above, according to this embodiment, C
From the signal generation start signal 121 which is completely asynchronous with the LK signal,
Accurate pulses can be generated in the cycle of one CLK signal 104.

In the conventional apparatus, when a pulse of 1 CLK width is produced, only one synchronized with the CLK signal 104 can be produced, but in the present embodiment, one cycle pulse of arbitrary timing can be produced. it can.

Further, according to the present invention, even if the operation speed of the semiconductor changes due to variations in the manufacturing process, fluctuations in temperature and voltage, the number of gate passages is always measured by measuring the number of passing gates in one cycle of the CLK signal 104. A clock width pulse can be accurately generated.

Further, in the present invention, the pulse is limited to one clock, but it will be explained that it is possible to accurately generate a half clock pulse or several clock pulses by changing the timing of storing in the flip-flop 117. There is no end.

Correspondence between this embodiment and each means of the first invention and its operation will be described below with reference to FIGS.

According to a first aspect of the invention, in an electronic circuit composed of a plurality of circuit blocks, a first clock signal (CLK) that repeats a signal change at a constant cycle in each circuit block.
Signal 104) and a plurality of logic gates for sequentially transmitting and outputting the input first clock signal or the second clock signal that is asynchronous with the first clock signal with a predetermined delay time. Delay gate 10
6 to 110), a timing gate (DFF 102, 103) that generates a timing signal having an arbitrary cycle with respect to one cycle of the first clock signal, and the timing signal is generated from the timing gate (FIG. 2). Hold timing (FF117) for holding the passing state of the first clock signal passing through each logic gate, and the passing state of the logic gate held by the holding means. And a comparison means (comparator 118) which outputs a coincidence signal when the passage states of the respective logic gates by the second clock signal are compared and coincides, and the first signal based on the coincidence signal from the comparison means. The second clock signal (output signal 122) that is synchronized with one cycle of the clock signal of the above is output to another circuit block (not shown). A signal output gate (DFF120), and while the timing signals are generated by the DFFs 102 and 103, the FF 117 holds the passage state in which the CLK signal 104 passes through each of the delay gates 106 to 110, and the held delay. Each delay gate 106-depending on the passing state of the gates 106-110 and the activation signal 121-
When the comparator 118 compares the passing state of 110 with the passing state and outputs a coincidence signal, D is generated based on the coincidence signal.
The FF 120 outputs an output signal 122, which is synchronized with one cycle of the first clock signal at an arbitrary cycle, to another circuit block, and outputs the first clock signal and the second clock signal asynchronous with the first clock signal. It is possible to generate a timing signal having an arbitrary cycle width for one cycle of the clock signal. [Second Embodiment] A second embodiment of the present invention is a DR based on a timing signal generated by a timing generation circuit.
This is applied to the switching signal between the Row address and the Column address of the AM access circuit.

Normally, the Row from the RAS output of the DRAM is
The address hold time is 10 ns.
To ensure ns, process conditions, temperature,
The operation speed of the semiconductor has a wide range depending on the voltage condition, and in the worst case, the speeding up of the memory access which does not require a triple margin is hindered.

As another method, RA is performed in CLK synchronization.
There is also a method of performing S and address switching in this order, but normal C
At the LK frequency, it also takes time.

The present embodiment is intended to solve this problem and to ensure an accurate address hold time regardless of the operation speed of the semiconductor.

FIG. 4 is a block diagram for explaining the detailed structure of the signal generating circuit in the timing signal generating device according to the second embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals. .

In the figure, reference numeral 201 denotes an edge detector, which detects a place where a signal next to the value input from the flip-flop 117 changes to "L" or "H", and "H" is detected there. Output.

Reference numeral 202 denotes a selector, which is the edge detector 2
Suitable delay signals 111 to 116 for the input from 01
To output the output signal 204 to the address selector (selector) 205. The address selector 205 is
Address input to DRAM from Row to Column
Switch to nN. 203 is a circuit input signal.

In this embodiment, the delay state of the delay circuit is measured by the first process as in the first embodiment. Since this embodiment is a DRAM controller, it is desirable to execute the first process at initialization and refresh.

Then, the flip-flop 117 has 1
It is assumed that the delay state of the CLK cycle is already stored. The edge detector 201 has a value on the flip-flop 117, for example, {H, H, H, ... H, L, L, ... L ”.
“H” is output to the signal line at the position where “H” changes to “L”, and “L” is output to the other signal lines.

In order to make the explanation easy to understand, specific numerical values will be described as an example.

First, it is assumed that 24 delay gates are passed during the CLK period of 60 ns. At this time, the flip-flop 117 outputs "H" for the first 24 signals and "L" for the subsequent signals. Edge detector 201
Outputs "H" to the point where it changes from "H" to "L", that is, the 24th signal. The selector 202 is constructed so as to always generate the timing of the address hold time of 10 ns, and if “H” is input to the 24th signal, the output of the delay gate in the fourth stage is output to the output signal 204 of the selector 202. Output as.

In other words, the logic of the selector 202 outputs a delay output of the number of stages divided by 60/6 which passed in 60 ns to obtain 10 ns.

As described above, in the present embodiment, the logic of the selector 202 realizes the creation of the timing at a constant rate of the clock cycle.

FIG. 5 is a timing chart for explaining a predetermined timing signal generating operation in the signal generating circuit shown in FIG.

First, when the RAS signal is output to the DRAM, the input signal 203 is input to the present timing signal generator, and the selector 202 selects the delay output of the fourth stage as described above, so the output signal 122 Outputs the output signal SD4 in the figure.

As a result, the address selector 205 switches between Row and Column, so that a hold time of 10 nS for the Row address from the RAS signal is guaranteed.

Further, since the selector 202 is configured to select the output signal from about 1/6 of the number of gates that have passed in the cycle of 1 CLK, even if the passing speed changes depending on the temperature and voltage conditions. Therefore, the address hold time of 10 nS can always be guaranteed accurately.

Further, in the present embodiment, only the timing detection of 1/6 of the clock cycle has been described.
This can be achieved with any value. Further, it may be longer than one cycle of the clock.

Further, in the present configuration, the flip-flop 117 is input from each stage of the delay gate, but it may be appropriately thinned out depending on the relationship between the measurement time and the timing of selection. When the number of stages is further large, it is possible to encode the number of passage stages and reduce the number of bits.

Correspondence between the present embodiment and each means of the second invention and its operation will be described below with reference to FIGS.

A second aspect of the present invention is an electronic circuit comprising a plurality of circuit blocks, wherein a first clock signal (CLK
A clock source or a clock input unit that oscillates the signal 104), and the first clock signal or a second clock signal that is asynchronous with the first clock signal that is input is sequentially transmitted with a predetermined delay time. A plurality of logic gates (delay gates 106 to 110) and a timing gate (DFF 102, 10) for generating a timing signal having an arbitrary cycle with respect to one cycle of the first clock signal.
3) and holding means (FF11) for holding the passage state in which the first clock signal passes through each logic gate while the timing signal is generated from the timing gate.
7) and detection means (edge detector 201) for detecting a change in the passing state of the logic gate held by the holding means.
And the delay gate 106 of a predetermined number of stages based on the change in the passing state of the logic gate detected by the detecting means.
To 110 for selecting the second clock signal (circuit input signal 203) output to another circuit block, and while the timing signals are generated from the DFFs 102 and 103, the FF 117 The passage state of the first clock signal passing through each logic gate is maintained,
When the change in the passing state of the held delay gates 106 to 110 is detected by the detecting means, the selector 202 outputs from the predetermined number of logic gates based on the detected change in the passing state of the delay gates 106 to 110. Circuit input signal 203 to be selected and output to another circuit block, and circuit input signal 203 asynchronous with CLK signal 104
From this, it is possible to generate a pulse signal (output signal 204) having an arbitrary cycle width for one cycle of the CLK signal 104. [Third Embodiment] A third embodiment of the present invention is an example in which the present invention is applied to a circuit for generating a CLK signal synchronized with a trigger signal.
In particular, this is an example in which a device for generating a VIDEO signal in synchronization with a horizontal synchronizing signal of a printer engine such as a laser beam printer is configured.

FIG. 6 is a block diagram for explaining the detailed structure of the signal generating circuit in the timing signal generator according to the third embodiment of the present invention. The same parts as those in FIGS. 1 and 4 are designated by the same reference numerals. I am doing it.

In the figure, 301 is VIDEO CLK
An oscillator 302 for generating a signal, a selector 302, selects a delay circuit output corresponding to the edge position according to the select signal input from the edge detector 201.

Reference numeral 303 denotes a counter, which is the selector 301.
Count with the delayed clock selected by
When the constant value is counted, a load signal is output to the parallel-serial converter 304. The parallel-serial converter 304 outputs a VIDEO signal in synchronization with the input clock.

A reset pulse generator 305 outputs a reset pulse to the flip-flop 307 at the falling edge of the trigger signal. 306 is an OR gate, and the flip-flop 307 holds the delay state at the rising edge of the trigger signal. A trigger signal 308 is generated in synchronization with a horizontal synchronization signal L (not shown) generated by the printer engine.
The print time H of the scan is held. Hereinafter, the timing signal generation operation in the signal generation circuit shown in FIG. 6 will be described with reference to the timing chart shown in FIG.

FIG. 7 is a timing chart for explaining the timing signal generating operation in the signal generating circuit shown in FIG.

In the figure, C output by 301
When the trigger signal 308 which constantly passes through the delay gates 106 to 110 becomes “H”, the LK holds the respective states of the delay gate output signals SD 1 to SD 8 in the flip-flop 307, and the edge detector 201 “ The change from "H" to "L" is detected, and "H" is output to the signal line. In the example shown in FIG. 7, the output signal SD3 corresponds.

The selector 302 is the edge detector 201.
Of the delay gate, the output of the delay gate at the edge is output as the CLK signal. As a result, the selector 302 generates CLK synchronized with the trigger signal. In synchronization with the clock, the PS converter 304 performs parallel-serial conversion, outputs a VIDEO signal, and prints.

When the counter 303 counts a fixed number, it sends a load signal to the parallel-serial converter 304 to load new data. When the printing time for one line ends, the trigger signal changes to "L", the reset pulse generator 305 generates a reset pulse at this falling edge, and the flip-flop 307 is reset to "0". At this time, the edge detector 201 stops the output, and the selector 302 also stops the clock output. Then, it waits for the trigger signal of the next line.

As described above, according to this embodiment, the CLK signal synchronized with the asynchronous trigger signal can be accurately generated.

Although the present embodiment is applied to the VIDEO CLK synchronizing circuit, it goes without saying that the method of generating the CLK synchronized with any asynchronous signal is the gist of the present invention.

Correspondence between this embodiment and each means of the third invention and its operation will be described below with reference to FIGS. 6 and 7.

A third aspect of the invention is an electronic circuit composed of a plurality of circuit blocks, in which a clock source (oscillator 301) or a clock for oscillating a first clock signal that repeats a signal change at a constant cycle in each circuit block. Based on an input means, a plurality of logic gates (delay gates 106 to 110) for sequentially transmitting and outputting the input first clock signal with a predetermined delay time, and a trigger signal asynchronous with the first clock signal. Holding means (FF307) for holding the passing state of the first clock signal passing through each logic gate, and detecting means (edge detector 201) for detecting a change in the passing state of the logic gate held by the holding means. ) And the theory of a predetermined number of stages synchronized with the trigger signal based on the change in the passing state of the logic gate detected by the detecting means. And selection means for outputting the other circuit blocks (the selector 302) selects the first clock signal output from the gate, the by FF307 1
The passing state of the first clock signal passing through each logic gate is held based on the trigger signal that is asynchronous with the clock signal, and the edge detector 201 detects the passing state change of the held logic gate. And the selector 3 based on the detected change in the passing state of the logic gate.
02 selects the first clock signal output from the logic gate of the predetermined stage number synchronized with the trigger signal and outputs it to another circuit block to generate the first clock signal synchronized with the asynchronous trigger signal. It is possible to do. [Fourth Embodiment] FIG. 8 is a block diagram illustrating a detailed configuration of a signal generating circuit in a timing signal generator according to a fourth embodiment of the present invention. The same components as those in FIG. 1 are designated by the same reference numerals. I am doing it.

In the figure, 401 is a flip-flop,
Reference numeral 402 is a trigger signal, 403 is an AND gate, and 404 is an inverter. 801 is a CLK signal.

In this embodiment, the CLK signal is constantly input to the delay gates 106 to 110, and the delayed output signals 111 to 116 are output. When the trigger signal 402 asynchronous with the CLK signal is input, the flip-flop 401 is set and the output signal becomes H.

At this time, the delay state of the output signals 111 to 116 is held in the flip-flop 117. The comparator 118 compares the value held in the flip-flop 117 with the value of the input output signals 111 to 116, and outputs a match signal when they match. The NND gate 403 and the inverter 404 are for masking the coincidence signal which is initially held in the flip-flop 117 and appears at the moment.

The comparator 118 outputs the coincidence signal when the same value as that held in the flip-flop 117 is input, that is, 1 CLK periodic wave. At that time, the flip-flop 401 to which the coincidence signal is output is reset. That is, the output signal is reset, and the output signal is output for exactly one CLK cycle. According to this embodiment, it is possible to generate a pulse of 1 CLK cycle from an arbitrary trigger signal that is asynchronous with the CLK signal. This can be applied to various pulses such as strobe signals for memory access and interface signals.

Correspondence between the present embodiment and each means of the fourth invention and its operation will be described below with reference to FIG.

In a fourth aspect of the invention, in an electronic circuit composed of a plurality of circuit blocks, a first clock signal (CLK
A clock source (not shown) or a clock input means for oscillating the signal 801), and a plurality of logic gates (delay gates 106 to 110) for sequentially transmitting and outputting the input first clock signal with a predetermined delay time. Holding means (FF307) for holding a passing state in which the first clock signal passes through each logic gate based on a trigger signal asynchronous with the first clock signal, and the logic gate held by the holding means Of the first clock signal that sequentially passes through each logic gate by comparing the change of the passing state of the first clock signal and the passing state of the first clock signal. An output gate that sequentially outputs a pulse signal of one cycle width of the first clock to another circuit block from the input of the trigger signal based on a coincidence signal. DFF401) and have, FF11
When the pass state in which the first clock signal passes through each logic gate is held by 7 based on the trigger signal asynchronous with the one clock signal, the pass state change of the held logic gate and each logic are sequentially performed. The first passing through the gate
Of the clock signal, the comparator 118 outputs a coincidence signal in the case of coincidence, and based on the coincidence signal, the DFF 401 outputs a pulse of one cycle width of the first clock from the input of the trigger signal. It is possible to sequentially output signals to other circuit blocks and generate a pulse signal having one cycle width of the first clock signal from the asynchronous trigger signal.

According to each of the above-described embodiments, the number of passing logic gates is counted by a clock signal having a constant period, so that the operating environment and the operating time of the chip process are indirectly measured, and the actual gate Since the operation is performed in the operation time, it is possible to generate a signal at the same time and operate so that a signal having the same pulse width can be obtained regardless of whether the chip operation is slow or fast. Therefore, it is possible to absorb the variation in the operation speed, which the semiconductor device originally has, between the electronic circuit blocks.

[0081]

As described above, the first aspect of the present invention
According to the invention, while the timing signal is generated from the timing gate, the holding means holds the passing state in which the first clock signal passes through each logic gate, and holds the passing state of the held logic gate. When the comparison means compares the passing states of the respective logic gates by the second clock signal and outputs a coincidence signal when they coincide with each other, the signal output gate outputs one cycle of the first clock signal based on the coincidence signal. On the other hand, since the second clock signal that synchronizes at an arbitrary cycle is output to another circuit block, the first clock signal and the second clock signal that is asynchronous are arbitrarily selected for one cycle of the first clock signal. It is possible to generate a timing signal that is synchronized with the cycle.

According to the second invention, while the timing signal is generated from the timing gate, the first holding means holds the timing signal.
When the passing state of the clock signal of each of the logic gates is held and the holding state change of the held logic gate is detected by the detecting means, based on the detected passing state change of the logic gate, Since the selecting means selects the second clock signal output from the logic gate in the predetermined number of stages and outputs it to the other circuit block, the first clock signal and the second clock signal asynchronous with the first clock signal are used to output the first clock signal. It is possible to generate a pulse signal having an arbitrary cycle width for one cycle of the clock signal.

According to the third invention, the first means is provided by the holding means.
When the passing state of the first clock signal passing through each logic gate is held based on the trigger signal asynchronous with the clock signal, and the passing state change of the held logic gate is detected by the detecting means, Based on the detected change in the passing state of the logic gate, the selecting means selects the first clock signal output from the logic gate at the predetermined stage number synchronized with the trigger signal and outputs the selected first clock signal to another circuit block. , A first clock signal that is synchronous with the asynchronous trigger signal can be generated.

According to the fourth aspect of the present invention, the first holding means is used to hold the first signal based on the trigger signal asynchronous with the one clock signal.
Of the clock signal passing through each logic gate is held, and when the holding state change of the held logic gate is held by the holding means, the passing state change of the held logic gate is sequentially changed. The comparing means outputs a coincidence signal when the passage state of the first clock signal passing through the logic gate is compared and coincides with each other, and the output gate outputs the first signal from the input of the trigger signal based on the coincidence signal. Since the pulse signal having the 1-cycle width of the clock is sequentially output to the other circuit blocks, the pulse signal having the 1-cycle width of the first clock signal can be generated from the asynchronous trigger signal.

Therefore, it is possible to generate a timing signal having an arbitrary cycle with respect to one cycle of one clock signal or a pulse signal with an arbitrary cycle width with respect to one cycle of one clock signal.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a detailed configuration of a signal generating circuit according to a first embodiment of the invention.

FIG. 2 is a timing chart showing an operation of a signal delay measuring process which is a first process in the signal generating circuit shown in FIG.

3 is a timing chart showing the timing of a pulse signal generation process which is a second process in the signal generation circuit shown in FIG.

FIG. 4 is a block diagram illustrating a detailed configuration of a signal generation circuit in a timing signal generation device showing a second embodiment of the present invention.

5 is a timing chart explaining a predetermined timing signal generating operation in the signal generating circuit shown in FIG.

FIG. 6 is a block diagram illustrating a detailed configuration of a signal generation circuit in a timing signal generation device showing a third embodiment of the present invention.

7 is a timing chart illustrating a timing signal generating operation in the signal generating circuit shown in FIG.

FIG. 8 is a block diagram illustrating a detailed configuration of a signal generation circuit in a timing signal generation device showing a fourth embodiment of the present invention.

[Explanation of symbols]

 102 DFF 103 DFF 105 OR gate 106 Delay gate 107 Delay gate 108 Delay gate 109 Delay gate 110 Delay gate 117 Delay gate 117 FF 118 Comparator 120 DFF 122 Output signal

Claims (4)

[Claims] 1. In an electronic circuit composed of a plurality of circuit blocks, a clock source or a clock input means for oscillating a first clock signal that repeats a signal change at a constant cycle in each circuit block, and the input circuit. A plurality of logic gates for sequentially transmitting and outputting the first clock signal or the second clock signal asynchronous with the first clock signal with a predetermined delay time, and arbitrary for one cycle of the first clock signal A timing gate that generates a timing signal having a period, a holding unit that holds a passage state in which the first clock signal passes through each logic gate while the timing signal is being generated from the timing gate, and the holding unit. Comparing the passing state of the logic gate held by the means with the passing state of each logic gate by the second clock signal, And a comparing means for outputting a coincidence signal, and a second means having an arbitrary period width for one period of the first clock signal based on the coincidence signal from the comparing means.
And a signal output gate for outputting the clock signal of the above to another circuit block. 2. In an electronic circuit composed of a plurality of circuit blocks, a clock source or a clock input means for oscillating a first clock signal that repeats a signal change at a constant cycle in each circuit block, and the input circuit. A plurality of logic gates for sequentially transmitting and outputting the first clock signal or the second clock signal asynchronous with the first clock signal with a predetermined delay time, and arbitrary for one cycle of the first clock signal A timing gate that generates a timing signal having a period, a holding unit that holds a passage state in which the first clock signal passes through each logic gate while the timing signal is being generated from the timing gate, and the holding unit. Detecting means for detecting a change in the passing state of the logic gate held by the means, and the logic gate detected by the detecting means And a selecting means for selecting the second clock signal output from the logic gate in the predetermined number of stages based on the change of the passing state of the above and outputting it to another circuit block. 3. In an electronic circuit composed of a plurality of circuit blocks, a clock source or a clock input means for oscillating a first clock signal that repeats a signal change in a constant cycle in each circuit block, and the input circuit. A plurality of logic gates that sequentially output the first clock signal with a predetermined delay time, and a passage through which the first clock signal passes through each logic gate based on a trigger signal that is asynchronous with the first clock signal. Holding means for holding the state, detection means for detecting a change in the passing state of the logic gate held by the holding means, and the trigger signal based on the change in the passing state of the logic gate detected by the detecting means Selecting means for selecting the first clock signal output from the logic gate of a predetermined number of stages to be synchronized and outputting it to another circuit block. A timing signal generator characterized in that. 4. In an electronic circuit composed of a plurality of circuit blocks, a clock source or a clock input means for oscillating a first clock signal that repeats a signal change at a constant cycle in each circuit block, and the input circuit A plurality of logic gates that sequentially output the first clock signal with a predetermined delay time, and a passage through which the first clock signal passes through each logic gate based on a trigger signal that is asynchronous with the first clock signal. When the holding means for holding the state and the passing state change of the logic gate held by the holding means are compared with the passing state of the first clock signal sequentially passing through the respective logic gates, a coincidence signal is obtained when they coincide with each other. And a pulse signal of one cycle width of the first clock from the input of the trigger signal based on the coincidence signal from the comparing means. A timing signal generator having an output gate for sequentially outputting to another circuit block.