JPH08186253A - Low-noise semiconductor device and its production - Google Patents

Abstract

PURPOSE: To provide a semiconductor device which can sufficiently reduce 1/f noise even when it is refined. CONSTITUTION: Impurity diffusion lumps 14a and 15a are formed apart from the surface of a silicon substrate 10 and the lumps 14a and 15a are used as source area 14 and drain area 15, respectively. A carrier is conducted between the areas 14 and 15 while it is not in contact with a gate insulation film 16, so 1/f noise can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device used, for example, in a first stage amplifier of a sensor, and more particularly, it controls the amount of current between a source region and a drain region by adjusting a gate voltage applied to a gate electrode. And a method for manufacturing the same.

[0002]

2. Description of the Related Art Generally, a MOS field effect transistor (hereinafter referred to as "MOSFET") includes, for example, an n-type semiconductor substrate 101 of a first conductivity type, as shown in FIG. The semiconductor substrate 101 is divided into a plurality of regions by the element isolation oxide film 102, and the channels 10 for conducting carriers in the semiconductor substrate 101 are divided into the divided regions.
3 and a second conductivity type p-type source region 105 and p-type drain region 1 formed in the semiconductor substrate 101 with the channel region 104 interposed therebetween.
06 are formed. A gate electrode 108 is provided on the surface of the channel region 104 via a gate oxide film 107. In the channel region 104, the semiconductor substrate 101
The channel 103 is formed so as to come into contact with the surface of the gate oxide film 107, that is, the interface with the gate oxide film 107.
3 by the source region 105 and the drain region 106
An electric current flows between them.

It is known that a large 1 / f noise is generated when a first stage amplifier of a sensor is constructed by using this MOSFET. When the sensor needs to detect a low frequency signal with high sensitivity, the first stage amplifier of the sensor must be S /
Improvement of N ratio (signal to noise ratio) is required. Therefore, it is necessary to reduce 1 / f of MOSFET. Moreover, if the MOSFET is miniaturized to highly integrate the semiconductor device, 1 / f noise is generally increased. In other words, in order to realize a sensor device in which the sensor and its signal processing circuit are highly integrated, it is becoming extremely important to reduce the noise of the transistor forming the first-stage amplifier.

[0004]

The 1 / f noise is considered to be caused by the disorder of the semiconductor substrate surface which occurs when a gate oxide film is formed on the semiconductor substrate surface. Therefore, attempts have been made to separate the channel from the surface of the semiconductor substrate in order to reduce the 1 / f noise of the MOSFET, but there is a problem in any method.

For example, there is a method of depleting the vicinity of the interface with the gate oxide film in the semiconductor substrate by applying a constant voltage to the gate electrode. In this method, the voltage applied to the gate must be newly established. The circuit configuration and operating conditions become complicated. Therefore, it is not preferable from the viewpoint of high integration of the semiconductor device and reduction of manufacturing cost.

Further, as shown in FIG. 7, the channel region 1
There is a method of forming a p-type buried layer 109 having a conductivity type opposite to that of the semiconductor substrate 101 in 04, and depleting the vicinity of the interface with the gate oxide film 107 by a built-in potential generated between the gate electrode 108 and the buried layer 109.
However, when this method is adopted, the gate electrode 108
Since the source region 105 and the drain region 106 are formed by ion-implanting impurities using the mask as a mask, the gate oxide film 107, the source region 105, and the drain region are diffused in order to diffuse the impurities in the lateral direction. 1
Inevitably, the portions 105a and 106a in contact with 06 are generated. Since carriers concentrate on these contact portions 105a and 106a, it is difficult to prevent the generation of 1 / f noise. Especially for high integration, MOSFE
When T is miniaturized, the ratio of such contact portions 105a and 106a in the carrier path between the source region 105 and the drain region 106 becomes large, and it becomes easy to be influenced by 1 / f noise.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor device capable of sufficiently reducing 1 / f noise even by miniaturization.

[0008]

In order to achieve the above object, according to the first invention, a semiconductor substrate having a first conductivity type and a channel forming a channel for conducting carriers in the semiconductor substrate are provided. A region, a source region and a drain region of the second conductivity type formed in the semiconductor substrate with the channel region sandwiched therebetween, and a gate electrode provided on the surface of the channel region via a gate insulating film. In a semiconductor device in which the amount of current between the source region and the drain region is controlled by adjusting the applied gate voltage, the source region and the drain region are:
There is provided a low noise semiconductor device including an impurity diffusion mass formed away from a surface of a semiconductor substrate.

According to the second aspect of the present invention, a buried layer of the second conductivity type is formed between the impurity diffusion blocks of the source region and the drain region so as to separate from the surface of the semiconductor substrate and induce formation of a channel.

Further, according to the third invention, a semiconductor substrate having the first conductivity type, a channel region for forming a channel for conducting carriers in the semiconductor substrate, and a semiconductor substrate in the semiconductor substrate with the channel region sandwiched therebetween. A source region and a drain region of the second conductivity type formed in the channel region, and a gate electrode provided on the surface of the channel region with a gate insulating film interposed therebetween, and the source region is adjusted by adjusting the gate voltage applied to the gate electrode. And a semiconductor manufacturing method for manufacturing a semiconductor device for controlling a current amount between drain regions, a step of forming a gate electrode of a predetermined shape on a semiconductor substrate, and ion implantation using a gate electrode as a mask Forming an impurity diffusion mass to be a source region and a drain region away from the substrate surface. That the semiconductor manufacturing process is provided.

Further, according to the fourth invention, in the semiconductor manufacturing method according to the feature of the third invention, ion implantation is performed using the interlayer insulating film covering the gate electrode as a mask, and the semiconductor substrate surface and the impurity diffusion mass are formed. The method is characterized by including a step of forming a conductive path connecting the two and a step of forming a source electrode and a drain electrode connected to the conductive path on the surface of the semiconductor substrate.

Furthermore, according to the fifth invention, a semiconductor substrate having the first conductivity type, and a channel region for forming a channel for conducting carriers in the semiconductor substrate,
A source region and a drain region of the second conductivity type formed in the semiconductor substrate with the channel region sandwiched therebetween, and a gate electrode provided on the surface of the channel region via a gate insulating film are applied to the gate electrode. In a semiconductor manufacturing method for manufacturing a semiconductor device in which a current amount between a source region and a drain region is controlled by adjusting a gate voltage, a step of forming a gate electrode in a predetermined shape on a semiconductor substrate; And the step of forming an electrode groove from the surface of the semiconductor substrate, and ion implantation is performed in the deep part of the electrode groove to form an impurity diffused mass under the surface of the semiconductor substrate that spreads from the deep part and becomes a source region and a drain region. A method for manufacturing a semiconductor is provided.

[0013]

According to the structure of the first aspect of the invention, when a current flows between the source region and the drain region, a channel is formed between the impurity diffusion masses separated from the surface of the semiconductor substrate. This channel does not contact the gate insulating film on the surface of the channel region.

Further, according to the structure of the second invention, when a current flows between the source region and the drain region, a channel is formed in the buried layer. This channel does not contact the gate insulating film on the surface of the channel region.

Further, according to the structure of the third invention, by performing ion implantation using the gate electrode as a mask,
An impurity diffused mass is formed inside the semiconductor substrate, away from the surface of the semiconductor substrate. The impurity diffused mass does not come into contact with the gate electrode. Therefore, 1 / f noise is significantly reduced in the semiconductor device using the impurity diffused mass as the source region and the drain region.

Further, according to the structure of the fourth invention, the conductive path is formed at a position separated from the gate electrode by the ion implantation. The conductive path connects the impurity diffused mass and the source or drain electrode.

Further, according to the structure of the fifth invention, by implanting ions into the deep portions of the electrode trenches on both sides of the gate electrode, an impurity diffused mass separated from the surface of the semiconductor substrate is formed inside the semiconductor substrate. It The impurity diffused mass does not come into contact with the gate electrode. Therefore, 1 / f noise is significantly reduced in the semiconductor device using the impurity diffused mass as the source region and the drain region.

[0018]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows the structure of a semiconductor device according to the first embodiment of the present invention, a so-called p-type MOSFET. This MO
The SFET is an n-type semiconductor substrate having a first conductivity type.
A silicon substrate 10 is provided, and an element region 10a is formed on the silicon substrate 10 by an element isolation oxide film 11. In the element region 10a, a channel region 13 forming a channel 12 for conducting carriers in the silicon substrate 10 and a p-type (second conductivity type) formed in the silicon substrate 10 with the channel region 13 interposed therebetween. )
Source region 14 and drain region 15 are provided.

On the surface of the channel region 13, a gate oxide film 16 as a gate insulating film and a gate electrode 17 made of n-type polysilicon are formed so as to overlap each other, and an interlayer insulating film 18 covers these surfaces. .

Source region 14 and drain region 15
Are impurity diffusion blocks 14a and 15a formed away from the surface of the silicon substrate 10 and the silicon substrate 10 respectively.
Conductive paths 14b and 15b connecting the surface and the impurity diffused masses 14a and 15a are included. A p-type buried layer 19 for inducing carriers forming the channel 12 is formed between the source region 14 and the drain region 15. The buried layer 19 has a depth of about 5 to 20 nm. The buried layer 19 allows the silicon substrate 10
The vicinity of the surface of is in a depleted state.

The ends of the conductive paths 14b and 15b, that is,
A source electrode 20 and a drain electrode 21 made of metal are formed on the surface of the substrate 10 in the source region 14 and the drain region 15.
Is formed. Source electrode 20 and drain electrode 21
The amount of current in between is controlled by adjusting the gate voltage applied to the gate electrode 17.

According to this MOSFET, the source region 1
4 and the impurity diffusion masses 14a, 1 of the drain region 15
Since the channel 12 is formed between 5a, the carrier flow does not come into contact with the gate oxide film 16 and 1 / f
The noise is about 20 to 3 at around 100Hz compared to the conventional one.
It was demonstrated to be reduced by 0%. In addition, the buried layer 1
Since the source region 14 and the drain region 15 do not come into contact with the gate oxide film 16 even when the depth of 9 is reduced to approach the gate oxide film 16, the mutual conductance is improved by the channel 12 approaching the surface of the substrate 10. (About 10% of the conventional level) and 1 / f noise suppression can be achieved at the same time.

Next, a method of manufacturing this MOSFET will be described. As shown in FIG. 2A, the element isolation oxide film 11 is formed on the silicon substrate 10 by the LOCOS method. Then, after forming an oxide film 22 in the element region 10a partitioned by the element isolation oxide film 11, ion implantation is performed to form a p-type buried layer 19. At this time, the acceleration energy (ion acceleration voltage) of ion implantation and the dose amount determine the depth and diffusion concentration of the buried layer 19. For example, when boron B ⁺ is used as an impurity,
The acceleration energy is 30 keV and the dose is 10 ¹² atoms /
It is set to about cm ² . This allows depths of 5-20n
A buried layer 19 having a thickness of about m is formed.
The n-type layer remains from the upper part of 9 to the surface of the substrate 10.

As shown in FIG. 2B, after the polysilicon 23 is deposited on the oxide film 22, the polysilicon 23 deposited by RIE (ion reaction etching) using the resist 24 pattern as a mask is used as a gate electrode. Process into 17 shapes. Then, using the gate electrode 17 as a mask, ion implantation is performed again, and at both ends of the p-type buried layer 19,
A pair of p-type impurity diffusion masses 14a and 15a separated from the surface of the silicon substrate 10 are formed (see FIG. 2C). At this time, the ion implantation is performed using boron B ⁺ under the conditions of an acceleration energy of 50 keV and a dose of about 10 ¹⁴ atoms / cm ² . This ion implantation does not reduce the resistance of the layer between the impurity diffusion blocks 14a and 15a and the surface of the substrate 10.

The resist 24 is removed, and contact holes 25 for the source electrode 20 and the drain electrode 21 are formed in the oxide film 22. As a result, the gate oxide film 16 is processed into a predetermined shape (see FIG. 3A). After that, FIG.
As shown in (B), an interlayer insulating film 18 is formed so as to cover the gate oxide film 16 and the gate electrode 17. Ion implantation is performed using this interlayer insulating film 18 as a mask to form conductive paths 14b and 15b connecting the surface of the silicon substrate 10 and the impurity diffused masses 14a and 15a. Finally, the source electrode 20 and the drain electrode 21 made of metal are formed in the contact hole 25, and the metal electrode for the gate electrode 17 is formed to obtain the MOSFET shown in FIG.

When the semiconductor substrate is p-type and the source region, drain region and buried layer are n-type, n
Type MOSFET can be obtained. N MOSFET
Even in the case of the p-type, the obtained effect is similar to that of the p-type.

Further, as described above, instead of going through the step of connecting the semiconductor substrate surface and the impurity diffused mass with a conductive path,
A source electrode and a drain electrode may be formed in the groove through a step of forming a groove reaching the impurity diffusion mass on the surface of the semiconductor substrate.

FIG. 4 shows the structure of a semiconductor device according to the second embodiment of the present invention, a so-called n-type MOSFET. This MO
The SFET is a p-type semiconductor device having the first conductivity type.
A mold silicon substrate 30 is provided. The MOSFET has a configuration similar to that of the first embodiment described above, and the silicon substrate 30
A channel region 31 that forms a channel, and an n-type source region 32 and a drain region 33 of the second conductivity type that are formed so as to sandwich the channel region 31 are formed therein.

The characteristic feature of this second embodiment is that this M
A step of forming electrode trenches from the surface of the silicon substrate 30 on both sides of the gate electrode 34 by the impurity diffusion blocks 32a and 33a in the OSFET, and a step of implanting ions into the deep portions of the electrode trenches using impurities such as phosphorus P ^+. The point is that it is formed through.

The method of manufacturing this MOSFET will be described in detail. First, as in the case of the above-described first embodiment, the element region is formed by the oxide film 35 for element isolation, and the oxide film for the gate insulating film (thickness 25 nm). Is deposited and the buried layer 36 is formed (see FIG. 2A). The buried layer 36 is formed by
When the surface concentration of the silicon substrate 30 is about 4 × 10 ¹⁶ atoms / cm ² , phosphorus P ⁺ is used as an impurity, the acceleration energy is 160 keV, and the dose is 2.5 × 10 ¹² atoms / cm ^2.
Ion implantation is performed under the condition of cm ² . As a result, the n-type buried layer 36 (depth of about 10 nm from the gate oxide film) having a peak concentration of about 10 ¹⁷ atoms / cm ³ is formed.

Then, similarly to FIG. 2B, after p-type polysilicon is deposited, the polysilicon deposited by RIE is processed into the shape of the gate electrode 34 by using the pattern of the resist 37 as a mask. Subsequently, the same resist 37 is used to process the gate oxide film 39 into a shape corresponding to the gate electrode 34, and the RIE is used to grind the silicon substrate 30 from the surface of the silicon substrate 30 by about 0.1 μm to form electrode grooves. 40 is formed (see FIG. 5A).

As shown in FIG. 5B, the silicon substrate 3
Ion implantation is performed again with the surface 37 covered with the resist 37. For the ion implantation, for example, phosphorus P ⁺ is used as an impurity, the acceleration energy is 100 keV, and the dose amount is 5 × 1.
It is performed under the condition of 0 ¹⁴ atoms / cm ² . By this ion implantation, impurities are diffused from the deep portion of the electrode groove 40, and n-type impurity diffusion blocks 32a and 33a are formed below the surface of the silicon substrate 30.
Is formed. At this time, even if the impurities are diffused in the lateral direction, the diffusion of the impurity diffusion blocks 32a and 33a does not reach the gate oxide film 39.

After that, the resist 37 is removed, and FIG.
As shown in (C), an interlayer insulating film 41 is deposited to a thickness of about 500 nm, and the gate oxide film 39, the gate electrode 34, and the surface of the silicon substrate 30 sandwiched between the two contact holes 40 are covered with the interlayer insulating film 41.

Finally, the source electrode 42 and the drain electrode 43 made of metal are formed in the contact hole 40, and the metal electrode for the gate electrode 34 is formed, and the MOSF shown in FIG. 4 is formed.
ET is obtained.

In the MOSFET thus obtained, the flow of carriers does not contact the gate oxide film 39,
The 1 / f noise is about 2 at around 100Hz compared to the conventional one.
It was demonstrated that the reduction was 0 to 30%. Further, even if the buried layer 36 is made shallow to approach the gate oxide film 39, there is no contact with the gate oxide film 39 in the source region 32 and the drain region 33. It is possible to simultaneously improve the conductance (about 10% as compared with the conventional one) and suppress 1 / f noise.

If the semiconductor substrate is n-type and the source region, drain region and buried layer are p-type, p
Type MOSFET can be obtained. MOSFET is p
Even in the case of the n-type, the obtained effect is similar to that of the n-type.

Further, in any of the embodiments, by appropriately changing the ion implantation conditions in the first ion implantation step, a normally-on or normally-off element can be obtained. In this case, 1 / f noise is reduced as compared with the conventional element regardless of the element type.

[0039]

As described above, according to the first aspect of the present invention, since the channel does not contact the gate insulating film, 1 / f noise is significantly reduced. In particular, even when the semiconductor device is miniaturized for high integration, contact between the channel and the gate insulating film is avoided, and the influence of 1 / f noise is reduced.

According to the second aspect of the invention, the second conductive type buried layer can surely form a channel apart from the surface of the semiconductor substrate.

Further, according to the third invention, the semiconductor device according to the first invention can be easily manufactured.

Furthermore, according to the fourth aspect of the invention, since the impurity diffusion mass and the source or drain electrode are connected by the conductive path away from the gate electrode, the carrier never contacts the gate electrode. Therefore, 1
/ F noise is reduced.

Furthermore, according to the fifth invention, the semiconductor device according to the first invention can be easily manufactured.

[Brief description of drawings]

FIG. 1 is a sectional view showing a structure of a MOSFET according to a first embodiment of the present invention.

FIG. 2 is a process drawing for explaining the manufacturing method of the MOSFET of FIG.

FIG. 3 is a process drawing for explaining the manufacturing method of the MOSFET in FIG. 1.

FIG. 4 is a sectional view showing the structure of a MOSFET according to a second embodiment of the present invention.

FIG. 5 is a process chart for explaining the manufacturing method of the MOSFET in FIG.

FIG. 6 is a cross-sectional view showing the structure of a conventional MOSFET.

FIG. 7 is a cross-sectional view showing the structure of a conventional MOSFET.

[Explanation of symbols]

10, 30 Silicon substrate as semiconductor substrate, 12
Channel, 13, 31 channel region, 14, 32 source region, 14a, 15a, 32a, 33a impurity diffusion mass, 14b, 15b conductive path, 15, 33 drain region, 16, 39 gate oxide film as gate insulating film,
17, 34 Gate electrodes, 40 Grooves for electrodes.

Claims (5)

[Claims] 1. A semiconductor substrate having a first conductivity type, a channel region for forming a channel for conducting carriers in the semiconductor substrate, and a second conductivity formed in the semiconductor substrate with the channel region interposed therebetween. Type source region and drain region, and a gate electrode provided on the surface of the channel region through a gate insulating film, and adjusting the gate voltage applied to the gate electrode, the amount of current between the source region and the drain region. The low noise semiconductor device according to claim 1, wherein the source region and the drain region include an impurity diffusion mass formed apart from the surface of the semiconductor substrate. 2. A buried layer of the second conductivity type is formed between the impurity diffusion blocks of the source region and the drain region, the buried layer being away from the surface of the semiconductor substrate and inducing the formation of a channel. The low-noise semiconductor device described. 3. A semiconductor substrate having a first conductivity type, a channel region for forming a channel for conducting carriers in the semiconductor substrate, and a second conductivity formed in the semiconductor substrate with the channel region interposed therebetween. Type source region and drain region, and a gate electrode provided on the surface of the channel region through a gate insulating film, and adjusting the gate voltage applied to the gate electrode, the amount of current between the source region and the drain region. In a semiconductor manufacturing method for manufacturing a semiconductor device for controlling a semiconductor device, a step of forming a gate electrode in a predetermined shape on a semiconductor substrate, ion implantation using a gate electrode as a mask And a step of forming an impurity diffusion mass to be a region and a drain region. 4. A step of forming a conductive path connecting between the semiconductor substrate surface and the impurity diffusion mass by performing ion implantation using an interlayer insulating film covering the gate electrode as a mask, and forming a conductive path on the semiconductor substrate surface. 4. The method of manufacturing a semiconductor according to claim 3, further comprising the step of forming a source electrode and a drain electrode that are connected to each other. 5. A semiconductor substrate having a first conductivity type, a channel region for forming a channel for conducting carriers in the semiconductor substrate, and a second conductivity formed in the semiconductor substrate with the channel region sandwiched therebetween. Type source region and drain region, and a gate electrode provided on the surface of the channel region through a gate insulating film, and adjusting the gate voltage applied to the gate electrode, the amount of current between the source region and the drain region. In a semiconductor manufacturing method for manufacturing a semiconductor device for controlling a semiconductor device, a step of forming a gate electrode in a predetermined shape on a semiconductor substrate, a step of forming an electrode groove from the surface of the semiconductor substrate on both sides of the gate electrode, Impurities are implanted below the surface of the semiconductor substrate by ion implantation to extend from the deep portion to form source and drain regions. And a step of forming a substance diffusion mass.