JPH08181585A - Delay circuit - Google Patents

Abstract

PURPOSE: To reduce temperature dependency by providing a delay inverter and an N-channel MOS transistor(TR) and a capacitor and connecting an input terminal to a gate of the MOS TR. CONSTITUTION: When a level at an input terminal 10 changes from H to L, an N-channel MOS TR Qn is turned off and a capacitor C is disconnected, a level of an output terminal 14 is changed at a high speed. On the other hand, when a level at the input terminal 10 changes from L to H, the MOS TR Qn is turned on and the capacitor C is connected to an output 12 of a delay inverter 11, then the fall of the output 12 slows down and a level change at the output terminal 14 is delayed attended therewith. Only the rise of the level of the input terminal 10 is delayed in this way and the delay time mainly depends on the capacitor C, the temperature dependency is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay circuit, and more particularly to a delay circuit having a small pattern area and being less affected by temperature.

[0002]

2. Description of the Related Art In semiconductor integrated circuits such as DRAMs,
In particular, a delay circuit that delays only the rising or falling of the pulse signal is generally used. The configuration and input / output waveform of this type of delay circuit are shown in FIGS. The delay circuit shown in FIG. 5 is composed of a NAND circuit (3) in which an input terminal (1) and an output of an even-numbered stage delay inverter (2) are connected. As shown in FIG. 6, the operation of this circuit is such that when the input terminal (1) changes from the H level to the L level, the output (4) and the output terminal (5) of the NAND circuit (3) rise at high speed. However, when the L level changes to the H level, the change of the output terminal (5) is delayed by the delay time of the delay inverter (1). That is, according to this circuit, only the rising edge of the signal at the input terminal (1) can be delayed.

On the other hand, the delay circuit shown in FIG. 6 is composed of a NOR circuit (33) in which the input terminal (1) and the output of the even-numbered stage delay inverter (1) are connected, and the input terminal (1) Changes from the H level to the L level, the output (44) and the output terminal (5) of the NOR circuit (33) rise with a delay of the delay time of the delay inverter (1), but from the L level to the H level. When changing, the output terminal (5) rises at high speed. That is, according to this circuit, only the falling edge of the signal at the input terminal (1) can be delayed.

[0004]

However, since the above delay circuit has a large number of elements, the pattern area becomes large, and basically the delay adjustment is performed by the inverter.
There is a problem that the temperature dependence of the delay time increases.

[0005]

In order to solve the above problems, a delay circuit according to claim 1 has an input terminal (10) and an input terminal (10) as shown in FIG. 1 or 3. A three-stage delay inverter (11) connected, an N-channel MOS transistor Qn and a capacitor C connected in series between the output of the delay inverter (11) and the ground potential Vss, and The input terminal (10) is connected to the gate of the N-channel type MOS transistor Qn.

A delay circuit according to a second aspect of the present invention, as shown in FIG. 4 or 6, has an input terminal (10) and a three-stage delay inverter (1) connected to the input terminal (10).
1), a P-channel type MOS transistor Qp and a capacitor C which are connected in series between the output of the delay inverter (11) and the power supply potential Vcc, and the input terminal (10) is connected to the N-channel type. MOS transistor Qp
It is characterized by being connected to the gate of.

[0007]

According to the delay circuit of claim 1, when the input terminal (10) changes from the H level to the L level, the N-channel type MOS transistor Qn is turned off and the capacitor C is disconnected. (14) changes at high speed. On the other hand, when the input terminal (10) changes from L level to H level, the N-channel MOS transistor Qn is turned on and the capacitor C outputs the delay inverter (11) output (12). Since the output (12) is delayed, the change of the output terminal (14) is delayed accordingly.

According to the delay circuit of the second aspect,
When the input terminal (10) changes from the H level to the L level, the P-channel MOS transistor Qp turns on and the capacitor C causes the output (12) of the delay inverter (11).
, The output (12) rises slowly, and the change of the output terminal (14) is also delayed accordingly. On the other hand, when the input terminal (10) changes from the H level to the L level, the N channel type MOS transistor Qp
Turns off and the capacitor C is disconnected, so that the output terminal (14) changes at high speed.

As described above, according to the delay circuit described above, only the fall or rise of the input terminal (10) can be delayed, but the delay time can be mainly determined by the capacitor C, so that it can be compared with the conventional example. The temperature dependence can be significantly reduced. Further, if the capacitor C is formed of, for example, a MOS capacitor under the power supply line, the pattern area does not increase at all, so that the pattern area can be made smaller than in the conventional example.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A delay circuit according to an embodiment of the present invention will be described below with reference to the drawings. (1) First Embodiment As shown in FIG. 1, the delay circuit according to the present embodiment has three stages of delay inverters (1) connected to an input terminal (10).
1) and the output (1) of the final stage of the delay inverter (11)
2) and an N-channel MOS transistor Qn and a capacitor C which are connected in series between the ground potential Vss and an input terminal A of the N-channel MOS transistor Qn.
It is connected to the gate of. Then, the output terminal (14) is taken out from the output of the final stage of the delay inverter (11) through the two-stage waveform shaping inverter (13).

The operation of this delay circuit will be described with reference to FIGS. When the input terminal (10) changes from the H level to the L level, the N-channel MOS transistor Qn is turned off in response to this, and the capacitor C is disconnected from the output (12) of the delay inverter (11). 12) rises at high speed, and in response to this, the output terminal (14) also rises at high speed.

Next, the input terminal (10) changes from L level to H level.
When the voltage rises to the level, the N-channel type MOS transistor Qn turns on and the capacitor C turns on the delay inverter (1
It is connected to the output (12) of 1). At this time, the final stage inverter of the delay inverter (11) has a delay time td1.
Since the H level is maintained during that time, the capacitor C is charged during that time. After that, an L level is output from the delay inverter (11), but since the electric charge accumulated in the capacitor C must be discharged, as shown in the figure, it takes a discharge time td2 for the output (12) to reach the L level. Need. When the output (12) cuts the threshold value of the waveform shaping inverter (13), the output terminal (1
4) changes.

As described above, according to the present embodiment, only the rising of the input terminal (1) can be delayed, but the delay time can be mainly determined by the capacitor C, so that it depends on the temperature as compared with the conventional example. It is possible to significantly reduce the sex. Further, if the capacitor C is formed of, for example, a MOS capacitor under the power supply line, the pattern area does not increase at all, so that the pattern area can be made smaller than in the conventional example.

As shown in FIG. 3, N-channel type M
The connection order of the OS transistor Qn and the capacitor C may be reversed. However, in this case, since the capacitor C cannot be configured by the MOS capacitance, for example, it is configured by the capacitance between the first layer polysilicon and the second layer polysilicon.
Due to the parasitic capacitance Cp, the accuracy of the delay time may deteriorate. Therefore, the delay circuit shown in FIG. 1 can be constructed more simply and is superior in accuracy. (2) Second Embodiment A delay circuit according to the present embodiment has a three-stage delay inverter (11) connected to an input terminal (10) as shown in FIG.
And a P-channel MOS transistor Qp and a capacitor C which are connected in series between the output (12) of the delay inverter (11) and the power supply potential Vcc, and the input terminal (10) is connected to an N-channel MOS. It is connected to the gate of the transistor Qp. Then, the output terminal (14) is taken out from the output of the final stage of the delay inverter (11) through the two-stage waveform shaping inverter (13).

The operation of this delay circuit will be described with reference to FIGS. When the input terminal (10) changes from the H level to the L level, the output (12) starts rising in response to this, but when the output (12) exceeds the threshold voltage of the P-channel type MOS transistor Qp, the P The channel type MOS transistor Qp turns on and the capacitor C
Is connected to the output (12), the rising edge is delayed to charge the capacitor C. Therefore, the change of the output terminal (14) is also delayed via the waveform shaping inverter (13).

Next, the input terminal (10) changes from L level to H level.
When the level changes, the P-channel MOS transistor Qp is turned off in response to this, and the capacitor C is disconnected from the output (12) of the delay inverter (11), so that the output (12) falls at a high speed and this Upon reception, the output terminal (14) also falls at a high speed. As described above, according to the present embodiment, only the falling edge of the input terminal (10) can be delayed, but the delay time can be mainly determined by the capacitor C, so that its temperature dependence is higher than that of the conventional example. It can be significantly reduced. Further, if the capacitor C is formed of, for example, a MOS capacitor under the power supply line, the pattern area does not increase at all, so that the pattern area can be made smaller than in the conventional example.

As shown in FIG. 6, a P-channel type M
The connection order of the OS transistor Qp and the capacitor C may be reversed. However, in this case, since the capacitor C cannot be configured by the MOS capacitance, for example, it is configured by the capacitance between the first layer polysilicon and the second layer polysilicon.
Due to the parasitic capacitance Cp, the accuracy of the delay time may deteriorate. Therefore, the delay circuit shown in FIG. 4 can be configured more simply and is more accurate.

[0018]

As described above, according to the present invention,
Only the fall or rise of the input terminal can be delayed, but the delay time is mainly the capacitor C.
The temperature dependence can be significantly reduced as compared with the conventional example. further,
Regarding the capacitor C, for example, MO under the power line
If formed by the S capacitance or the like, the pattern area does not increase at all, so there is an advantage that the pattern area can be made smaller than in the conventional example.

[Brief description of drawings]

FIG. 1 is a first circuit diagram illustrating a delay circuit according to a first embodiment of the present invention.

FIG. 2 is a waveform diagram illustrating an operation of the delay circuit according to the first exemplary embodiment of the present invention.

FIG. 3 is a second circuit diagram illustrating the delay circuit according to the first embodiment of the present invention.

FIG. 4 is a first circuit diagram illustrating a delay circuit according to a second embodiment of the present invention.

FIG. 5 is a waveform diagram illustrating the operation of the delay circuit according to the second embodiment of the present invention.

FIG. 6 is a second circuit diagram illustrating a delay circuit according to a second embodiment of the present invention.

FIG. 7 is a first circuit diagram illustrating a delay circuit according to a conventional example.

FIG. 8 is a first waveform diagram illustrating an operation of a delay circuit according to a conventional example.

FIG. 9 is a second circuit diagram illustrating a delay circuit according to a conventional example.

FIG. 10 is a second diagram for explaining the operation of the delay circuit according to the conventional example.
It is a waveform diagram of.

[Explanation of symbols]

 10 Input Terminal 11 Delay Inverter 12 Delay Inverter Output 13 Waveform Shaping Inverter 14 Output Terminal Qn N-Channel MOS Transistor C Capacitor Qp P-Channel MOS Transistor

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/822

Claims (2)

[Claims] 1. An input terminal, an odd number of stages of delay inverters connected to the input terminal, and an N-channel type M connected in series between an output of the delay inverter and a ground potential.
A delay circuit having an OS transistor and a capacitor, wherein the input terminal is connected to the gate of the N-channel type MOS transistor. 2. An input terminal, an odd number of stages of delay inverters connected to the input terminal, and a P-channel type M connected in series between the output of the delay inverter and the power supply potential.
A delay circuit having an OS transistor and a capacitor, wherein the input terminal is connected to the gate of the N-channel type MOS transistor.