JPH0818049A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a MOS transistor with a shallower junction by forming raised source/drain with less number of processes. CONSTITUTION:By leaving oxide film 8 at the upper portion and the side wall of polysilicon gate electrode 6, silicon substrate is exposed at the source/drain part. Then, N-type amorphous silicon is formed. After that, amorphous silicon at the source/drain part is single-crystallized by a proper heat treatment, thus forming an epotaxial layer. Then, the amorphous silicon is selectively etched to form raised source/drains 11, 11. After that, N--type impurity is diffused from the raised source/drain 11 by a proper heat treatment, thus forming n<-> layers 12, 12 and hence forming the n<-> layers 12, 12 by one heat treatment and manufacturing an N-channel MOS transistor with a shallow junction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to an MO of a raised source / drain structure.
The present invention relates to a method for manufacturing an S transistor.

[0002]

2. Description of the Related Art Conventionally, in miniaturized MOS transistors, shallow junction formation has been required to suppress the short channel effect. However, when forming the diffusion layer by ion implantation, it is difficult to make the depth 50 nm or less,
There are limits to the formation of shallow junctions. Moreover, since the resistance of the source / drain increases as the junction becomes shallower, the driving force of the MOS transistor is significantly reduced due to the parasitic resistance.

In order to solve the above problems associated with the shallow junction formation, a MOS transistor having a raised source / drain structure has been proposed (SSWong et al .; IEDM Technol.
ogyDigest, P.634, 1984). As a method for forming a rise source / drain structure, a method proposed by SSWong et al. And a method using a disposable spacer (JRPh
iester et al .; IEDM Technology Digest, P.885, 1992) has been proposed. Hereinafter, a method of manufacturing an n-channel MOS transistor will be described as an example.

Normal Method After forming the gate electrode, a nitride film is formed on the gate electrode.
Then, phosphorus is ion-implanted to form the low concentration diffusion layer n ⁻ layer. Next, a sidewall spacer of an insulating film is formed on the side wall of the gate electrode. After that, silicon is selectively epitaxially grown on the exposed source / drain portions of the substrate to raise the source / drain portions. Subsequently, arsenic is implanted to form a high-concentration n ⁺ layer.
After that, the nitride film on the gate electrode is removed.

Method Using Disposable Spacer After forming the gate electrode, an oxide film is formed on the gate electrode.
Next, a sidewall spacer of a nitride film is formed on the side wall of the gate electrode. After that, silicon is selectively epitaxially grown on the source / drain portions to raise the source / drain portions. Subsequently, arsenic is implanted to form a high-concentration n ⁺ layer. After that, side wall space
Remove the service. Subsequently, phosphorus is ion-implanted to form a low concentration n ⁻ layer. Then, the side wall is formed again.

[0006]

However, in the conventional method, it is difficult to control the desired junction depth because the diffusion of impurities in the n ⁻ layer is affected by the thermal history during the formation of the epitaxial layer. There was such a problem. On the other hand, the disposable - Saburusupe - The method using the service n after n ⁺ layer formation ^- to form a layer, n ^- layers are not subjected to thermal history during the epitaxial growth. Therefore, it is possible to accurately diffuse the n ⁻ layer to a predetermined region. However, this method has a problem in that the sidewall spacer must be removed and then formed again, resulting in an increase in the number of steps.

Also, these raised source / drain structure transistors, unlike ordinary MOS transistors, have a structure in which the source / drain portions are raised, so that the capacitance between the gate and the drain increases. There is a problem that the operating speed of the transistor becomes slow.
The present invention relates to a method of manufacturing a semiconductor device and solves the above problems.

[0008]

According to another aspect of the present invention, there is provided a semiconductor device manufacturing method, wherein an impurity region having a shallow junction is formed in a substrate by diffusion from a raised source / drain portion formed on a semiconductor substrate. It is a thing. A method of manufacturing a semiconductor device according to a second aspect of the present invention includes a step of forming a gate insulating film and a gate electrode on a semiconductor substrate,
A step of forming an insulating film thereon, a step of exposing both sides of the gate electrode in the semiconductor substrate, and a step of forming conductive silicon opposite to the semiconductor substrate on at least the exposed semiconductor substrate. It includes and.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device, which comprises a step of forming a gate insulating film and a gate electrode on a semiconductor substrate, a step of forming an insulating film thereon. Exposing both sides of the gate electrode in the semiconductor substrate, forming a conductive amorphous silicon opposite to the semiconductor substrate on at least the exposed semiconductor substrate, and a part of the amorphous silicon,
The method includes a step of solid-phase growing the exposed substrate as a seed to form a single crystal, and a step of heat-treating the substrate.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device in which relatively heavy ions are implanted near an interface between the substrate and the conductive silicon or amorphous silicon. Further, in the method for manufacturing a semiconductor device according to the invention of claim 5, the amorphous silicon existing in a portion other than the single crystallized portion is selectively etched.

In the method of manufacturing a semiconductor device according to the sixth aspect of the present invention, the single crystallized silicon has certain facets. In the method of manufacturing a semiconductor device according to the invention of claim 7, the single crystallized silicon is silicidized.

[0012]

Function: That is, the risen source composed of silicon etc.
By forming the impurity region by diffusion from the drain portion, a low concentration and shallow junction can be formed on the substrate. Further, since the rise source / drain portion is made of single crystal silicon and the heat treatment is performed to diffuse the impurities, it is easy to control the junction depth.

Further, by implanting relatively heavy ions (eg, Si ions) near the interface between the substrate and the rise source / drain portion, the natural oxide film at this interface is destroyed. In addition, since single-crystallized silicon has a certain facet, it is possible to suppress an increase in capacitance between the gate and the drain.

Further, by siliciding the single crystallized silicon, the resistance value of this portion is lowered.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is embodied in an N-channel MOS transistor having a raised source / drain structure will be described below with reference to the drawings. 1 to 11 are schematic cross-sectional views showing a manufacturing process of a semiconductor device according to an embodiment of the present invention.

Step 1 (see FIG. 1): An element isolation region 2 is formed on the P-type single crystal silicon 1 by a normal LOCOS method, and channel injection for controlling the threshold voltage is performed (illustration). Omitted). Then, the gate oxide film 3 having an appropriate thickness (for example, about 80 Å) is formed on the surface of the silicon substrate 1.
To form. Any method (oxidation method, CVD method, PVD method, etc.) may be used to form the gate oxide film 3.

Step 2 (see FIG. 2): A polysilicon film 4 having an appropriate thickness (for example, about 2300 Å) is formed on the gate oxide film 3. Any method (oxidation method, CVD method, PVD method, etc.) may be used to form the polysilicon film 4. Then, an oxide film 5 having an appropriate thickness (for example, about 250 Å) is formed on the polysilicon film 4. What method (oxidation method, CVD method,
PVD method or the like) may be used.

Step 3 (see FIG. 3): The oxide film 5, the polysilicon film 4 and the gate oxide film 3 are anisotropically etched by using a lithographic technique and an etching technique to have an appropriate height (eg, A polysilicon gate electrode 6 of about 2630Å) is formed. Step 4 (see FIG. 4): An oxide film 7 having an appropriate thickness (for example, about 100 Å) is formed on the silicon substrate 1 and the gate electrode 6. Any method (oxidation method, CVD method, PVD method, etc.) may be used for forming the oxide film 7.

Step 5 (see FIG. 5): Using reactive ion etching equipment, gas species and gas flow rate ratio; CHF ₃ /
CF ₄ / Ar = 20/20/400, power density; 1.7W
/ Cm ² , pressure; 100 mTorr, anisotropic etching is performed to expose the semiconductor substrate 1 in the region corresponding to the source / drain formation region, and leave the oxide film 8 on the side wall and the upper portion of the gate electrode 6. .

By the etching in step 5, the oxide film 7 on the gate electrode 6 is also etched, but since the oxide film on the gate electrode 6 is sufficiently thick (the oxide film in step 2). No. 5 is formed, and the oxide film 7 is further formed in step 4 so that the film thickness is about 300 to 350 Å), and it is not completely etched. Step 6 (see FIG. 6): The natural oxide film on the semiconductor substrate 1 in the source / drain portions is removed (not shown), and the N-type amorphous silicon 9 having an appropriate thickness (for example, about 1500 Å) 9 is formed.
Are formed on the silicon substrate 1 and the silicon oxide film 8.

In the step 6, there are the following four methods for removing the natural oxide film and forming the N-type amorphous silicon 9. (1) Pressure: about 900 ° C in a high vacuum of about 1 × 10 ^-7 torr
The natural oxide film on the source / drain is removed by the heat treatment (1) (not shown). Subsequently, amorphous silicon containing N-type impurities (such as phosphorus and arsenic) having a concentration of about 3 × 10 ²⁰ cm ⁻³ is formed on the silicon substrate 1 and the silicon oxide film 8. Any method (a CVD method, a PVD method, or the like) may be used for forming the amorphous silicon.

(2) Pressure: A natural oxide film on the source / drain is removed by heat treatment at about 900 ° C. in a high vacuum of about 1 × 10 ⁻⁷ torr (not shown). Subsequently, amorphous silicon is formed on the silicon substrate 1 and the silicon oxide film 8. Any method (a CVD method, a PVD method, or the like) may be used for forming the amorphous silicon. After that, N-type impurities are implanted so that the peak of the impurity concentration in the amorphous silicon is about 3 × 10 ²⁰ cm ⁻³ .

(3) Amorphous silicon containing N-type impurities with a concentration of about 3 × 10 ²⁰ cm ^-3 is used as the silicon substrate 1.
And on the silicon oxide film 8. What method (CVD method, P method, etc.) is used to form this amorphous silicon.
VD method) may be used. After that, under the condition that a peak appears near the interface between the amorphous silicon and the substrate 1, relatively heavy ions (for example, silicon ions, phosphorus ions,
Arsenic ions, etc.) are implanted to destroy the natural oxide film at the interface between the amorphous silicon and the substrate 1 and mix with silicon to remove the natural oxide film (not shown).

(4) Amorphous silicon is formed on the silicon substrate 1 and the silicon oxide film 8. What method (CVD method,
PVD method or the like) may be used. After that, the peak of the N-type impurity concentration in the amorphous silicon is about 3 × 10 ^20.
The first impurity implantation is performed so as to be about cm ⁻³ (not shown). Then, as the second impurity implantation, relatively heavy ions (for example, silicon ions, phosphorus ions, arsenic ions, etc.) are implanted under the condition that a peak appears near the interface between the amorphous silicon and the substrate 1, and the amorphous silicon and the substrate 1 are implanted. The natural oxide film at the interface of is destroyed and mixed with silicon to remove the natural oxide film (not shown). In this method, the order of the first impurity implantation and the second impurity implantation may be reversed.

Step 7 (see FIG. 7): Amorphous silicon 9 is single-crystallized by a solid phase epitaxy method using the substrate 1 as a seed under appropriate heat treatment conditions (for example, about 600 ° C. for 5 minutes) to form a source. The epitaxial layer 10 is formed on the drain. On the edge side of the gate electrode 6 and the edge side of the element isolation region 2 of this epitaxial layer 10, the direction of the side of each pattern of the gate electrode 6 and the element isolation region 2 with respect to the semiconductor substrate 1, that is, in step 6. The gate of the source / drain formation region where the substrate 1 is exposed
Substrate 1 at each boundary with the electrode 6 or the element isolation region 2.
Facets are formed depending on the direction to. {111} if the pattern direction is the [011] direction
Facets are formed and {11 if the direction is [010]
0} facets are formed.

In step 7, the oxide film 8 and the amorphous silicon 9 on the element isolation region 2 remain in the amorphous phase under the heat treatment conditions of this embodiment because crystalline silicon serving as a seed does not exist. Further, since the oxide film 8 is formed also on the side wall of the polysilicon gate electrode 9, solid-phase growth does not proceed from the polysilicon gate electrode 9.

In step 7, since the temperature of the epitaxial layer 10 during the solid phase growth is sufficiently low, the diffusion of impurities from the epitaxial layer 10 into the semiconductor substrate 1 hardly occurs. Step 8 (see FIG. 8): By a wet etching method, a selective etching solution of CH ₃ COOH: HNO ₃ : HF: H ₂ O = 160: 70: 4.5: 10 is used at room temperature for an appropriate time (for example, about 10 minutes). ) In the etching of this step 8 in which the amorphous silicon 9 is selectively removed by immersion to form the raised source drains 11 and 11, the etching rate of the amorphous silicon 9 is higher than that of the epitaxial layer 10. Since it is also fast, it is possible to completely remove the amorphous silicon 9 by optimizing the immersion time. Step 9 (see FIG. 9): Subsequently, heat treatment is performed to remove the amorphous silicon 9 from the raised source / drain 11, 11. The low-concentration diffusion layers n ⁻ layers 12 and 12 are formed by impurity diffusion.

For example, when amorphous silicon 9 is formed by doping phosphorus at the same time, the n ^- layer 1 having a junction depth of about 0.05 μm is formed by heat treatment at 800 ° C. for 30 minutes.
2, 12 are formed. As a result, an N-channel MOS transistor having a rise source / drain structure is formed. Step 10 (see FIG. 10): After that, an insulating film (for example, a silicon oxide film) is deposited on the raised source / drain 11, 11, the oxide film 8 and the element isolation region 2 (not shown). Any method (for example, CVD, PVD, etc.) may be used for depositing this insulating film.

Subsequently, a spacer 13 is formed on the side wall of the gate electrode 6 and the edge side of the element isolation region 2 by anisotropic etching of the insulating film. After that, a source electrode, a drain electrode, and a gate electrode are formed. Further, when the gate electrode 6, the source electrode and the drain electrode are silicided (see FIG. 11), a metal film (for example, titanium, cobalt, tungsten, etc.) is formed on at least the gate electrode 6 and the raised source / drain 11, 11. ) Is formed (not shown). Any method (for example, a sputtering method) may be used to form this metal film. Then, by appropriate heat treatment (for example, lamp annealing method, about 650 ° C.), the gate electrode 6 and the raised source / drain 11,
11 to form a silicide 14.

In this step 10, the spacer 13 is
When the contact holes are formed on the raised source / drain 11, 11 and the vicinity of the edge of the raised source / drain 11, 11 is etched due to a mask shift in the lithography process, the substrate 1 It is provided to avoid etching. When the raised source / drain 11, 11 is silicidized, this spacer 13 is used as the raised source / drain 1.
It has a function of avoiding a short circuit between the source / drain and the substrate 1 due to silicidation of the facets 1 and 11 to the substrate 1.

To summarize the above manufacturing process, first, the oxide film 8 is left on the upper and side walls of the polysilicon gate electrode 6,
The silicon substrate 1 is exposed at the source / drain portions.
Then, N-type amorphous silicon 9 is formed. Thereafter, the amorphous silicon 9 in the source / drain portion is monocrystallized by an appropriate heat treatment to form the epitaxial layer 1
Form 0. Subsequently, the amorphous silicon 9 is selectively etched to raise the raised source / drain 11, 1
1 is formed. After that, appropriate heat treatment is performed to diffuse N-type impurities from the raised source / drain 11, 11 to form the n ⁻ layers 12, 12.

That is, in this embodiment, the temperature at the time of forming the raised source / drain 11, 11 is about 600 ° C. which is the processing temperature of the solid phase epitaxial, and the thermal diffusion of the N-type impurities at this time is almost the same. Not equal to Since the n ⁻ layers 12 and 12 can be formed by performing impurity diffusion to an arbitrary depth and controlling the junction depth by one subsequent heat treatment, a shallow junction N-channel MOS transistor can be manufactured.

In this embodiment, the side wall spacer is
The number of steps can be reduced because it is not necessary to form the sacrificial film once and then form it again. Further, since facets are formed on the rised source / drain 11 of this embodiment, as shown in FIG. 11, the gate-drain capacitance is about 75 compared to the rised source / drain without facet. % (= {(5.2-1.3) /5.2} × 100) can be reduced.

Incidentally, the present invention is not limited to the above embodiment, but may be carried out as follows. A P-channel MOS transistor having a raised source / drain structure is also manufactured in the same manner as in the above embodiment.
In that case, the P-type single crystal silicon substrate 1 is replaced with an N-type single crystal silicon substrate or an N well layer, the N-type impurities are replaced with P-type impurities (for example, boron ions), and the N-type amorphous silicon 9 is replaced with P. Type amorphous silicon. The other steps are the same as in the above embodiment. As a result, a high-concentration raised source / drain and a low-concentration p ^- layer can be formed on the N-type single crystal silicon substrate.

The polysilicon gate electrode 6 is replaced with a metal gate.
Replaced with The amorphous silicon forming step in (1), (2), (3), and (4) of step 6 is replaced with the following steps. That is, polysilicon is formed on the silicon substrate 1 and the silicon oxide film 8. Any method (a CVD method, a PVD method, or the like) may be used for forming the polysilicon. After that, relatively heavy ions (for example, silicon, arsenic, phosphorus, etc.) are injected into the polysilicon to be amorphized to form amorphous silicon.

[0036]

According to the method of manufacturing a semiconductor device of the present invention, since the impurity region is formed by diffusion from the rise source / drain portion made of silicon or the like, the desired junction depth can be obtained with a small number of steps. The semiconductor device can be obtained. Further, since the rise source / drain portion is made of single crystal silicon and the heat treatment is performed to diffuse the impurities, it is easy to control the junction depth.

Further, by implanting relatively heavy ions (for example, Si ions) near the interface between the substrate and the raised source / drain portion, the natural oxide film at this interface is destroyed, so that it is possible to remove the impurities in a vacuum. Compared to the work of removing the natural oxide film by heat treatment, it does not require much labor. In addition, since single-crystallized silicon has constant facets, an increase in capacitance between the gate and the drain can be suppressed and characteristics as a transistor can be improved.

Further, since the resistance value of this portion is lowered by siliciding the single crystallized silicon, the characteristics as a transistor can be improved.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to an embodiment of the invention.

FIG. 2 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 7 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 8 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 9 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 10 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 11 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 12 is a diagram comparing the gate-drain capacitance according to the presence or absence of facets in the example and the conventional example.

[Explanation of symbols]

 1 P-type single crystal silicon substrate (semiconductor substrate) 3 Gate oxide film (gate insulating film) 6 Polysilicon gate electrode (gate electrode) 8 Silicon oxide film (insulating film) 11 Rised source / drain

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[Procedure amendment]

[Submission date] July 19, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] Full text

[Correction method] Change

[Correction content]

[Document name] Statement

Title: Method for manufacturing semiconductor device

[Claims]

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to an MO of a raised source / drain structure.
The present invention relates to a method for manufacturing an S transistor.

[0002]

2. Description of the Related Art Conventionally, in miniaturized MOS transistors, shallow junction formation has been required to suppress the short channel effect. However, when forming the diffusion layer by ion implantation, it is difficult to make the depth 50 nm or less,
There are limits to the formation of shallow junctions. Moreover, since the resistance of the source / drain increases as the junction becomes shallower, the driving force of the MOS transistor is significantly reduced due to the parasitic resistance.

In order to solve the above problems associated with the shallow junction formation, a MOS transistor having a raised source / drain structure has been proposed (SSWong et al .; IEDM Technol.
ogyDigest, P.634, 1984). As a method for forming a rise source / drain structure, a method proposed by SSWong et al. And a method using a disposable spacer (JRPh
iester et al .; IEDM Technology Digest, P.885, 1992) has been proposed. Hereinafter, a method of manufacturing an n-channel MOS transistor will be described as an example.

Normal Method After forming the gate electrode, a nitride film is formed on the gate electrode.
Then, phosphorus is ion-implanted to form the low concentration diffusion layer n ⁻ layer. Next, a sidewall spacer of an insulating film is formed on the side wall of the gate electrode. After that, silicon is selectively epitaxially grown on the exposed source / drain portions of the substrate to raise the source / drain portions. Subsequently, arsenic is implanted to form a high-concentration n ⁺ layer.
After that, the nitride film on the gate electrode is removed.

Method Using Disposable Spacer After forming the gate electrode, an oxide film is formed on the gate electrode.
Next, a sidewall spacer of a nitride film is formed on the side wall of the gate electrode. After that, silicon is selectively epitaxially grown on the source / drain portions to raise the source / drain portions. Subsequently, arsenic is implanted to form a high-concentration n ⁺ layer. After that, side wall space
Remove the service. Subsequently, phosphorus is ion-implanted to form a low concentration n ⁻ layer. Then, the side wall is formed again.

[0006]

However, in the conventional method, it is difficult to control the desired junction depth because the diffusion of impurities in the n ⁻ layer is affected by the thermal history during the formation of the epitaxial layer. There was such a problem. On the other hand, the disposable - Saburusupe - The method using the service n after n ⁺ layer formation ^- to form a layer, n ^- layers are not subjected to thermal history during the epitaxial growth. Therefore, it is possible to accurately diffuse the n ⁻ layer to a predetermined region. However, this method has a problem in that the sidewall spacer must be removed and then formed again, resulting in an increase in the number of steps.

Also, these raised source / drain structure transistors, unlike ordinary MOS transistors, have a structure in which the source / drain portions are raised, so that the capacitance between the gate and the drain increases. There is a problem that the operating speed of the transistor becomes slow.
The present invention relates to a method of manufacturing a semiconductor device and solves the above problems.

[0008]

According to another aspect of the present invention, there is provided a semiconductor device manufacturing method, wherein an impurity region having a shallow junction is formed in a substrate by diffusion from a raised source / drain portion formed on a semiconductor substrate. It is a thing. A method of manufacturing a semiconductor device according to a second aspect of the present invention includes a step of forming a gate insulating film and a gate electrode on a semiconductor substrate,
A step of forming an insulating film thereon, a step of exposing both sides of the gate electrode in the semiconductor substrate, and a step of forming conductive silicon opposite to the semiconductor substrate on at least the exposed semiconductor substrate. It includes and.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device, which comprises a step of forming a gate insulating film and a gate electrode on a semiconductor substrate, a step of forming an insulating film thereon. Exposing both sides of the gate electrode in the semiconductor substrate, forming a conductive amorphous silicon opposite to the semiconductor substrate on at least the exposed semiconductor substrate, and a part of the amorphous silicon,
A step of solid-phase growing the exposed substrate as a seed to single crystallize it.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein the step of forming at least the exposed semiconductor substrate with silicon having a conductivity opposite to that of the semiconductor substrate, or a part of the amorphous silicon, After the step of solid-phase growing the exposed substrate as a seed to single crystallize it, the substrate is heat-treated. In addition, claim 5
In the method of manufacturing a semiconductor device according to the invention, ions are implanted near the interface between the substrate and the conductive silicon or amorphous silicon.

According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein the amorphous silicon present in a portion other than a single crystallized portion is selectively etched.
In the method of manufacturing a semiconductor device according to the invention of claim 7, the single-crystallized silicon has a constant facet. In the method of manufacturing a semiconductor device according to the invention of claim 8, the single crystallized silicon is silicidized.

[0012]

Function: That is, the risen source composed of silicon etc.
By forming the impurity region by diffusion from the drain portion, a low concentration and shallow junction can be formed on the substrate. Further, since the rise source / drain portion is made of single crystal silicon and the heat treatment is performed to diffuse the impurities, it is easy to control the junction depth.

Also, by implanting ions (for example, a relatively desired ion such as Si is desirable) near the interface between the substrate and the raised source / drain portion, the natural oxide film at this interface is destroyed. . In addition, since single-crystallized silicon has a certain facet, it is possible to suppress an increase in capacitance between the gate and the drain.

Further, by siliciding the single crystallized silicon, the resistance value of this portion is lowered.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is embodied in an N-channel MOS transistor having a raised source / drain structure will be described below with reference to the drawings. 1 to 11 are schematic cross-sectional views showing a manufacturing process of a semiconductor device according to an embodiment of the present invention.

Step 1 (see FIG. 1): An element isolation region 2 is formed on the P-type single crystal silicon 1 by a normal LOCOS method, and channel injection for controlling the threshold voltage is performed (illustration). Omitted). Then, the gate oxide film 3 having an appropriate thickness (for example, about 80 Å) is formed on the surface of the silicon substrate 1.
To form. Any method (oxidation method, CVD method, PVD method, etc.) may be used to form the gate oxide film 3.

Step 2 (see FIG. 2): A polysilicon film 4 having an appropriate thickness (for example, about 2300 Å) is formed on the gate oxide film 3. Any method (a CVD method, a PVD method, or the like) may be used to form the polysilicon film 4. Then, an oxide film 5 having an appropriate thickness (for example, about 250 Å) is formed on the polysilicon film 4. This oxide film 5
What method (oxidation, CVD, PVD
Method) may be used.

Step 3 (see FIG. 3): The oxide film 5, the polysilicon film 4 and the gate oxide film 3 are anisotropically etched by using a lithographic technique and an etching technique to have an appropriate height (eg, A polysilicon gate electrode 6 of about 2630Å) is formed. Step 4 (see FIG. 4): An oxide film 7 having an appropriate thickness (for example, about 100 Å) is formed on the silicon substrate 1 and the gate electrode 6. Any method (oxidation method, CVD method, PVD method, etc.) may be used for forming the oxide film 7.

Step 5 (see FIG. 5): Using reactive ion etching equipment, gas species and gas flow rate ratio; CHF ₃ /
CF ₄ / Ar = 20/20/400, power density; 1.7W
/ Cm ² , pressure; 100 mTorr, anisotropic etching is performed to expose the semiconductor substrate 1 in the region corresponding to the source / drain formation region, and leave the oxide film 8 on the side wall and the upper portion of the gate electrode 6. .

By the etching in step 5, the oxide film 7 on the gate electrode 6 is also etched, but since the oxide film on the gate electrode 6 is sufficiently thick (the oxide film in step 2). No. 5 is formed, and the oxide film 7 is further formed in step 4 so that the film thickness is about 300 to 350 Å), and it is not completely etched. Step 6 (see FIG. 6): The natural oxide film on the semiconductor substrate 1 in the source / drain portions is removed (not shown), and the N-type amorphous silicon 9 having an appropriate thickness (for example, about 1500 Å) 9 is formed.
Are formed on the silicon substrate 1 and the silicon oxide film 8.

In the step 6, there are the following four methods for removing the natural oxide film and forming the N-type amorphous silicon 9. (1) Pressure: about 900 ° C in a high vacuum of about 1 × 10 ^-7 torr
The natural oxide film on the source / drain is removed by the heat treatment (1) (not shown). Subsequently, amorphous silicon containing N-type impurities (such as phosphorus and arsenic) having a concentration of about 3 × 10 ²⁰ cm ⁻³ is formed on the silicon substrate 1 and the silicon oxide film 8. Any method (a CVD method, a PVD method, or the like) may be used for forming the amorphous silicon.

(2) Pressure: A natural oxide film on the source / drain is removed by heat treatment at about 900 ° C. in a high vacuum of about 1 × 10 ⁻⁷ torr (not shown). Subsequently, amorphous silicon is formed on the silicon substrate 1 and the silicon oxide film 8. Any method (a CVD method, a PVD method, or the like) may be used for forming the amorphous silicon. After that, N-type impurities are implanted so that the impurity concentration in the amorphous silicon is about 3 × 10 ²⁰ cm ⁻³ in the entire film.

(3) Amorphous silicon containing N-type impurities with a concentration of about 3 × 10 ²⁰ cm ^-3 is used as the silicon substrate 1.
And on the silicon oxide film 8. What method (CVD method, P method, etc.) is used to form this amorphous silicon.
VD method) may be used. After that, under the condition that a peak appears near the interface between the amorphous silicon and the substrate 1, relatively heavy ions (for example, silicon ions, phosphorus ions,
Arsenic ions, etc.) are implanted to destroy the natural oxide film at the interface between the amorphous silicon and the substrate 1 and mix with silicon to remove the natural oxide film (not shown).

(4) Amorphous silicon is formed on the silicon substrate 1 and the silicon oxide film 8. What method (CVD method,
PVD method or the like) may be used. After that, the concentration of N-type impurities in the amorphous silicon is about 3 × in the entire film.
The first impurity implantation is performed so as to be about 10 ²⁰ cm ⁻³ (not shown). Then, as the second impurity implantation, relatively heavy ions (for example, silicon ions, under the condition that a peak appears near the interface between the amorphous silicon and the substrate 1).
(Phosphorus ions, arsenic ions, etc.) are implanted to destroy the natural oxide film at the interface between the amorphous silicon and the substrate 1 and mix with silicon to remove the natural oxide film (not shown). In this method, the order of the first impurity implantation and the second impurity implantation may be reversed.

Step 7 (see FIG. 7): Amorphous silicon 9 is single-crystallized by a solid phase epitaxy method using the substrate 1 as a seed under appropriate heat treatment conditions (for example, about 600 ° C. for 5 minutes) to form a source. The epitaxial layer 10 is formed on the drain. On the edge side of the gate electrode 6 and the edge side of the element isolation region 2 of this epitaxial layer 10, the direction of the side of each pattern of the gate electrode 6 and the element isolation region 2 with respect to the semiconductor substrate 1, that is, in step 6. The gate of the source / drain formation region where the substrate 1 is exposed
Substrate 1 at each boundary with the electrode 6 or the element isolation region 2.
Facets are formed depending on the direction to. {111} if the pattern direction is the [011] direction
Facets are formed and {11 if the direction is [010]
0} facets are formed.

In step 7, the oxide film 8 and the amorphous silicon 9 on the element isolation region 2 remain in the amorphous phase under the heat treatment conditions of this embodiment because crystalline silicon serving as a seed does not exist. Further, since the oxide film 8 is formed also on the side wall of the polysilicon gate electrode 6, solid phase growth does not proceed from the polysilicon gate electrode 6.

In step 7, since the temperature of the epitaxial layer 10 during the solid phase growth is sufficiently low, the diffusion of impurities from the epitaxial layer 10 into the semiconductor substrate 1 hardly occurs. Step 8 (see FIG. 8): CH ₃ COOH: HNO ₃ : HF: H ₂ O = 160: 70: 4.5: 10 or H ₃ PO at room temperature by the wet etching method.
_The amorphous silicon 9 is selectively removed by immersing it in a selective etching solution such as ₄ (phosphoric acid) for an appropriate time (for example, about 10 minutes), and the rise source / drain 1
In the etching of this step 8 for forming the layers 1 and 11, the etching rate of the amorphous silicon 9 is faster than that of the epitaxial layer 10. Therefore, the immersion time is optimized to completely remove the amorphous silicon 9. Step 9 (see FIG. 9): Subsequently, heat treatment is performed to form low-concentration diffusion layers n ⁻ layers 12 and 12 by impurity diffusion from the raised source drains 11 and 11.

For example, when amorphous silicon 9 is formed by doping phosphorus at the same time, the n ^- layer 1 having a junction depth of about 0.05 μm is formed by heat treatment at 800 ° C. for 30 minutes.
2, 12 are formed. As a result, an N-channel MOS transistor having a rise source / drain structure is formed. Step 10 (see FIG. 10): After that, an insulating film (for example, a silicon oxide film) is deposited on the raised source / drain 11, 11, the oxide film 8 and the element isolation region 2 (not shown). Any method (for example, CVD, PVD, etc.) may be used for depositing this insulating film.

Subsequently, a spacer 13 is formed on the side wall of the gate electrode 6 and the edge side of the element isolation region 2 by anisotropic etching of the insulating film. After that, a source electrode, a drain electrode, and a gate electrode are formed. Further, when the gate electrode 6, the source electrode and the drain electrode are silicided (see FIG. 11), a metal film (for example, titanium, cobalt, tungsten, etc.) is formed on at least the gate electrode 6 and the raised source / drain 11, 11. ) Is formed (not shown). Any method (for example, a sputtering method) may be used to form this metal film. Then, by appropriate heat treatment (for example, lamp annealing method, about 650 ° C.), the gate electrode 6 and the raised source / drain 11,
A silicide 14 is formed on 11.

In such a raised source / drain structure, the thickness up to the junction is sufficient (for example, 150
(0 Å or more), even if silicide is formed, it is very advantageous to prevent the junction leak due to the spike accompanying the silicidation. In this process 10, the spacer 13 causes a mask shift in the lithography process when the contact holes are formed on the raised source / drain 11, 11, and the raised source / drain 11,
It is provided in order to avoid etching on the substrate 1 when the vicinity of the edge 11 is etched.

In addition, the raised source / drain 11, 1
In the case of silicidizing 1, the spacer 13
It has a function of avoiding a short circuit between the source / drain and the substrate 1 due to silicidation from the facet portions of the raised source / drain 11, 11 to the substrate 1. To summarize the above manufacturing process, first, the oxide film 8 is left on the upper and side walls of the polysilicon gate electrode 6, and the silicon substrate 1 is exposed at the source / drain portions. Then, N-type amorphous silicon 9 is formed. After that, appropriate heat treatment is applied.
The amorphous silicon 9 in the drain and drain portions is monocrystallized to form an epitaxial layer 10. Subsequently, the amorphous silicon 9 is selectively etched to form the raised source / drain 11, 11. After that, by appropriate heat treatment, the raised source / drain 11, 11 is formed.
To diffuse n-type impurities to form n ⁻ layers 12 and 12.

That is, in this embodiment, the temperature at the time of forming the raised source / drain 11, 11 is about 600 ° C. which is the processing temperature of the solid phase epitaxial, and the thermal diffusion of the N-type impurities at this time is almost the same. Not equal to Since the n ⁻ layers 12 and 12 can be formed by performing impurity diffusion to an arbitrary depth and controlling the junction depth by one subsequent heat treatment, a shallow junction N-channel MOS transistor can be manufactured.

In this embodiment, the side wall spacer is
The number of steps can be reduced because it is not necessary to form the sacrificial film once and then form it again. Further, since facets are formed on the rised source / drain 11 of this embodiment, as shown in FIG. 11, the gate-drain capacitance is about 75 compared to the rised source / drain without facet. % (= {(5.2-1.3) /5.2} × 100) can be reduced.

Incidentally, the present invention is not limited to the above embodiment, but may be carried out as follows. A P-channel MOS transistor having a raised source / drain structure is also manufactured in the same manner as in the above embodiment.
In that case, the P-type single crystal silicon substrate 1 is replaced with an N-type single crystal silicon substrate or an N well layer, the N-type impurities are replaced with P-type impurities (for example, boron ions), and the N-type amorphous silicon 9 is replaced with P. Type amorphous silicon. The other steps are the same as in the above embodiment. As a result, a high-concentration raised source / drain and a low-concentration p ^- layer can be formed on the N-type single crystal silicon substrate.

The polysilicon gate electrode 6 is replaced with a metal gate.
Replaced with The amorphous silicon forming step in (1), (2), (3), and (4) of step 6 is replaced with the following steps. That is, polysilicon is formed on the silicon substrate 1 and the silicon oxide film 8. Any method (a CVD method, a PVD method, or the like) may be used for forming the polysilicon. After that, relatively heavy ions (for example, silicon, arsenic, phosphorus, etc.) are injected into the polysilicon to be amorphized to form amorphous silicon.

[0036]

According to the method of manufacturing a semiconductor device of the present invention, since the impurity region is formed by diffusion from the rise source / drain portion made of silicon or the like, the desired junction depth can be obtained with a small number of steps. The semiconductor device can be obtained. Further, since the rise source / drain portion is made of single crystal silicon and the heat treatment is performed to diffuse the impurities, it is easy to control the junction depth.

Further, by implanting relatively heavy ions (for example, Si ions) near the interface between the substrate and the raised source / drain portion, the natural oxide film at this interface is destroyed, so that it is possible to remove the impurities in a vacuum. Compared to the work of removing the natural oxide film by heat treatment, it does not require much labor. In addition, since single-crystallized silicon has constant facets, an increase in capacitance between the gate and the drain can be suppressed and characteristics as a transistor can be improved.

Further, since the resistance value of this portion is lowered by siliciding the single crystallized silicon, the characteristics as a transistor can be improved.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to an embodiment of the invention.

FIG. 2 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 7 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 8 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 9 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 10 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 11 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 12 is a diagram comparing the gate-drain capacitance according to the presence or absence of facets in the example and the conventional example.

[Explanation of symbols] 1 P-type single crystal silicon substrate (semiconductor substrate) 3 Gate oxide film (gate insulating film) 6 Polysilicon gate electrode (gate electrode) 8 Silicon oxide film (insulating film) 11 Rised silicon -Su drain 14 Silicide

Claims (7)

[Claims] 1. A method of manufacturing a semiconductor device, wherein an impurity region having a shallow junction is formed in a substrate by diffusion from a raised source / drain portion formed on a semiconductor substrate. 2. A step of forming a gate insulating film and a gate electrode on a semiconductor substrate, a step of forming an insulating film thereon, and a step of exposing both sides of the gate electrode in the semiconductor substrate. And a step of forming silicon having a conductivity opposite to that of the semiconductor substrate on at least the exposed semiconductor substrate, the method for manufacturing a semiconductor device. 3. A step of forming a gate insulating film and a gate electrode on a semiconductor substrate, a step of forming an insulating film thereon, and a step of exposing both sides of the gate electrode in the semiconductor substrate. And a step of forming at least the exposed semiconductor substrate with amorphous silicon having a conductivity opposite to that of the semiconductor substrate, and solid-phase growing a part of the amorphous silicon using the exposed substrate as a seed. A method of manufacturing a semiconductor device, comprising: a step of single crystallization; and a step of heat-treating a substrate. 4. The method of manufacturing a semiconductor device according to claim 2, wherein relatively heavy ions are implanted near an interface between the substrate and the conductive silicon or amorphous silicon. 5. The method for manufacturing a semiconductor device according to claim 3, wherein the amorphous silicon present in a portion other than the single-crystallized portion is selectively etched. 6. The method of manufacturing a semiconductor device according to claim 3, wherein the single-crystallized silicon has constant facets. 7. The method of manufacturing a semiconductor device according to claim 3, wherein the single-crystallized silicon is silicidized.