JPH08179371A - Thin film transistor liquid crystal display device and its driving method - Google Patents
Thin film transistor liquid crystal display device and its driving methodInfo
- Publication number
- JPH08179371A JPH08179371A JP32249794A JP32249794A JPH08179371A JP H08179371 A JPH08179371 A JP H08179371A JP 32249794 A JP32249794 A JP 32249794A JP 32249794 A JP32249794 A JP 32249794A JP H08179371 A JPH08179371 A JP H08179371A
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- Japan
- Prior art keywords
- sub
- liquid crystal
- thin film
- film transistor
- electrode
- Prior art date
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Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、広視野角を実現する薄
膜トランジスタ液晶表示装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor liquid crystal display device which realizes a wide viewing angle.
【0002】[0002]
【従来の技術】薄膜トランジスタ液晶表示装置は、近
年、ワークステーション、パーソナルコンピュータ、ポ
ータブルテレビ等に広く利用されており、さらに利用範
囲は拡大する傾向にある。従来の薄膜トランジスタ液晶
表示装置における問題として、視野角が狭いことが挙げ
られる。視野角拡大を実現する手段としては、特開平0
2−000012号、02−310534号、03−1
22621号、04−348323号、04−3483
24号、05−107556号各公報で提案されている
ような、画素分割構成が挙げられる。これは、画素電極
を副画素電極に分割し、各副画素毎に異なる透過率
(T)−ソース電圧振幅(V)特性をもたせるという方
法である。2. Description of the Related Art In recent years, thin film transistor liquid crystal display devices have been widely used in workstations, personal computers, portable televisions and the like, and their use range tends to expand. A problem with the conventional thin film transistor liquid crystal display device is that the viewing angle is narrow. As means for increasing the viewing angle, Japanese Patent Laid-Open No.
2-000012, 02-310534, 03-1
22621, 04-348323, 04-3483
There is a pixel division structure as proposed in each of Japanese Patent No. 24 and 05-107556. This is a method in which the pixel electrode is divided into sub-pixel electrodes and each sub-pixel has a different transmittance (T) -source voltage amplitude (V) characteristic.
【0003】しかし、画素分割の構成は、原理的にソー
ス信号電圧の一部しか液晶に印加されず、結果としてソ
ース電圧の振幅が大きくなっていた。However, in the pixel division structure, in principle, only a part of the source signal voltage is applied to the liquid crystal, resulting in a large amplitude of the source voltage.
【0004】[0004]
【発明が解決しようとする課題】そこで、本発明は、画
素分割構成をとる薄膜トランジスタ液晶表示装置におい
て、ソース電圧振幅の低減を目的とする。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to reduce the source voltage amplitude in a thin film transistor liquid crystal display device having a pixel division structure.
【0005】[0005]
【課題を解決するための手段】上記の問題を解決するた
めに、本発明は、第1の基板上にゲート配線、ソース配
線、蓄積容量配線がマトリクス状に形成され、ゲート配
線とソース配線との各交点にドレイン電極、画素電極、
および、ゲート配線の電位によりソース配線とドレイン
電極の導通を調節する薄膜トランジスタが形成され、第
1の基板に対向して設置された第2の基板上に対向電極
が形成され、画素電極が複数の副画素電極から形成さ
れ、ドレイン電極と各副画素電極間毎に転移容量が存在
し、各副画素電極と対向電極間毎に液晶容量が存在する
薄膜トランジスタ液晶表示装置で、蓄積容量配線が複数
の副蓄積容量配線から形成され、各副画素電極と各副蓄
積容量配線間毎に蓄積容量を形成する。In order to solve the above-mentioned problems, the present invention provides a gate wiring, a source wiring, and a storage capacitance wiring formed in a matrix on a first substrate. Drain electrode, pixel electrode,
In addition, a thin film transistor that adjusts conduction between the source wiring and the drain electrode according to the potential of the gate wiring is formed, a counter electrode is formed over a second substrate which is provided so as to face the first substrate, and a plurality of pixel electrodes are provided. In a thin film transistor liquid crystal display device that is formed from sub-pixel electrodes, has a transition capacitance between the drain electrode and each sub-pixel electrode, and has a liquid crystal capacitance between each sub-pixel electrode and a counter electrode, a plurality of storage capacitance lines are provided. The storage capacitors are formed from the sub-storage capacitance lines, and the storage capacitance is formed between each sub-pixel electrode and each sub-storage capacitance line.
【0006】また、ドレイン電極と少なくとも1つの副
画素電極間に転移容量が存在せず、直接電気的に接続し
ている、あるいは、少なくとも1つの副画素電極と副蓄
積容量配線間に、蓄積容量が存在せず、電気的に切断さ
れている、あるいは、前段のゲート配線が少なくとも1
つの副蓄積容量配線を兼用している等の構成であっても
よい。Further, there is no transition capacitance between the drain electrode and the at least one subpixel electrode, and the drain electrode and the at least one subpixel electrode are directly electrically connected, or the storage capacitance is provided between the at least one subpixel electrode and the substorage capacitance line. Is not present and is electrically disconnected, or the gate wiring in the previous stage is at least 1
It may be configured such that one sub-storage capacitor wiring is also used.
【0007】そして、薄膜トランジスタのオン期間にソ
ース電極の電位がドレイン電極に伝達され、オフ期間に
各副蓄積容量配線、対向電極の電位が変化して、各副画
素電極の電位が変調される。Then, the potential of the source electrode is transmitted to the drain electrode during the ON period of the thin film transistor, and the potentials of the sub-storage capacitance lines and the counter electrode are changed during the OFF period to modulate the potential of the sub-pixel electrodes.
【0008】また、少なくとも1つの副蓄積容量配線の
電位が一定である、あるいは、対向電極の電位が一定で
ある等の方法であってもよい。Alternatively, the method may be such that the potential of at least one sub-storage capacitance wiring is constant, or the potential of the counter electrode is constant.
【0009】[0009]
【作用】上記の手段によれば、各転移容量、液晶容量、
蓄積容量の3種類の容量値、および、各副蓄積容量配線
に印加される蓄積補償電位、対向電位の2種類の電圧値
を、適宜、副画素ごとに変化させることにより、各副画
素のT−V特性を変化させることができる。同時に、液
晶印加電圧を、ソース電圧振幅に加えて、蓄積補償電
位、対向電位の電圧振幅で生成するため、ソース電圧振
幅を低減することが可能となる。According to the above means, each transition capacitance, liquid crystal capacitance,
By appropriately changing, for each sub-pixel, the T value of each sub-pixel, the three kinds of capacitance values of the storage capacitor and the two kinds of voltage values of the storage compensation potential and the counter potential applied to each sub-storage capacitance wiring are appropriately changed. The −V characteristic can be changed. At the same time, since the liquid crystal applied voltage is generated with the voltage amplitude of the storage compensation potential and the counter potential in addition to the source voltage amplitude, the source voltage amplitude can be reduced.
【0010】[0010]
【実施例】本発明の実施例における薄膜トランジスタ液
晶表示装置の、等価回路図を(図1)に、電位関係図を
(図2)に、T−V特性図を(図3)に示す。EXAMPLE An equivalent circuit diagram (FIG. 1), a potential relationship diagram (FIG. 2) and a TV characteristic diagram (FIG. 3) of a thin film transistor liquid crystal display device in an example of the present invention are shown.
【0011】(図1)において、1はゲート配線、2は
ソース配線、3は蓄積容量配線で、第1の基板上にマト
リクス状に形成されている。本実施例では、前段のゲー
ト配線が蓄積容量配線3を兼用している。4はドレイン
電極、5は画素電極、6はゲート配線1の電位によりソ
ース配線2とドレイン電極4の導通を調節する薄膜トラ
ンジスタで、ゲート配線1とソース配線2との各交点に
形成されている。7は第1の基板に対向して設置された
第2の基板上に形成された対向電極である。5a、5b
は、それぞれ、副画素電極a、副画素電極bで、8は、
ドレイン電極4と副画素電極b5b間に存在しする転移
容量である。9a、9bは、それぞれ、副画素電極a5
a、副画素電極b5bと対向電極7間に存在する液晶容
量a、液晶容量bである。10a、10bは、それぞれ、副
画素電極a5a、副画素電極b5bと蓄積容量配線3間
に形成された蓄積容量a、蓄積容量bである。11は薄膜
トランジスタのゲートドレイン寄生容量である。In FIG. 1, 1 is a gate wiring, 2 is a source wiring, and 3 is a storage capacitor wiring, which are formed in a matrix on the first substrate. In this embodiment, the gate wiring at the previous stage also serves as the storage capacitance wiring 3. Reference numeral 4 is a drain electrode, 5 is a pixel electrode, 6 is a thin film transistor which adjusts the conduction between the source wiring 2 and the drain electrode 4 by the potential of the gate wiring 1, and is formed at each intersection of the gate wiring 1 and the source wiring 2. Reference numeral 7 is a counter electrode formed on the second substrate, which is installed so as to face the first substrate. 5a, 5b
Are subpixel electrode a and subpixel electrode b, and 8 is
It is a transfer capacitance existing between the drain electrode 4 and the sub-pixel electrode b5b. 9a and 9b are sub-pixel electrodes a5, respectively.
a is the liquid crystal capacitance a and liquid crystal capacitance b existing between the sub-pixel electrode b5b and the counter electrode 7. Reference numerals 10a and 10b are a storage capacitor a and a storage capacitor b formed between the subpixel electrode a5a, the subpixel electrode b5b and the storage capacitor wiring 3, respectively. Reference numeral 11 is a gate-drain parasitic capacitance of the thin film transistor.
【0012】(図2)において、101はゲート配線1
に印加されるゲート電位、102はソース配線2に印加
されるソース電位、103は前段のゲート配線が兼用し
ている蓄積容量配線3に印加される蓄積補償電位、10
7は対向電極に印加される対向電位である。本実施例で
は、対向電極の電位は一定である。In FIG. 2, 101 is a gate wiring 1.
, 102 is a source potential applied to the source wiring 2, 103 is a storage compensation potential applied to the storage capacitance wiring 3 which is also used by the gate wiring in the previous stage, 10
Reference numeral 7 is a counter potential applied to the counter electrode. In this embodiment, the potential of the counter electrode is constant.
【0013】(図3)において、201aは液晶容量a
におけるT−V特性a、201bは液晶容量bにおける
T−V特性b、201cは、T−V特性aおよびT−V
特性bを各画素面積で重み付け平均した画素全体のT−
V特性である。横軸はソース電位振幅(片側)、縦軸は
パネルの透過率を示す。In FIG. 3, 201a is a liquid crystal capacitance a.
In the liquid crystal capacitance b, the T-V characteristics a and 201b in FIG.
Characteristic b is weighted and averaged by each pixel area, and
It is a V characteristic. The horizontal axis shows the source potential amplitude (one side), and the vertical axis shows the transmittance of the panel.
【0014】本実施例によれば、転移容量、液晶容量、
蓄積容量の3種類の容量値、および、蓄積補償電位、対
向電位の2種類の電圧値を、適宜、副画素ごとに変化さ
せることにより、各副画素のT−V特性を変化させるこ
とができる。同時に、液晶印加電圧を、ソース電圧振幅
に加えて、蓄積補償電圧、対向電圧の電圧振幅で生成す
るため、ソース電圧振幅を低減することが可能となる。
実際に、視野角特性は従来例と同等のレベルに保ちつ
つ、全白から全黒までをソース電圧振幅(片側)2.5
Vで実現することが可能である。According to this embodiment, the transition capacitance, the liquid crystal capacitance,
The T-V characteristic of each sub-pixel can be changed by appropriately changing the three types of capacitance values of the storage capacitance and the two types of voltage values of the storage compensation potential and the counter potential for each sub-pixel. . At the same time, the liquid crystal applied voltage is generated by the storage compensation voltage and the counter voltage in addition to the source voltage amplitude, so that the source voltage amplitude can be reduced.
Actually, while keeping the viewing angle characteristics at the same level as the conventional example, the source voltage amplitude (one side) from all white to all black is 2.5.
It can be realized with V.
【0015】なお、本実施例では、前段のゲート配線が
蓄積容量配線を兼用していたが、蓄積容量配線は独立し
た配線であるという構成も考えられる。また、蓄積容量
配線が複数の副蓄積容量配線から形成され、各副画素電
極と各副蓄積容量配線間毎に蓄積容量を形成し、前段の
ゲート配線が少なくとも1つの副蓄積容量配線を兼用し
ている、あるいは、全蓄積容量配線が独立した配線であ
るという構成も考えられる。さらに、複数の副画素電極
のうち、少なくとも1つの副画素電極と副蓄積容量配線
間に、蓄積容量が存在せず、電気的に切断されている構
成も考えられる。In this embodiment, the gate wiring in the preceding stage also serves as the storage capacitance wiring, but the storage capacitance wiring may be an independent wiring. In addition, the storage capacitance wiring is formed of a plurality of sub storage capacitance wirings, and a storage capacitance is formed between each sub pixel electrode and each sub storage capacitance wiring, and the preceding gate wiring also serves as at least one sub storage capacitance wiring. Alternatively, a configuration may be considered in which all the storage capacitor wirings are independent wirings. Further, a configuration may be considered in which there is no storage capacitance between at least one subpixel electrode and the substorage capacitance line among the plurality of subpixel electrodes, and the subpixel electrodes are electrically disconnected.
【0016】また、本実施例では、対向電極の電位は一
定であったが、対向電極の電位が変化する方法も考えら
れる。また、複数の副蓄積容量配線が形成されるとき、
少なくとも1つの副蓄積容量配線の電位が一定である方
法も考えられる。上記のいずれの場合も、本実施例と、
同様の効果が期待できる。In the present embodiment, the potential of the counter electrode is constant, but a method of changing the potential of the counter electrode may be considered. In addition, when a plurality of sub storage capacitor wirings are formed,
A method is also conceivable in which the potential of at least one sub storage capacitor wiring is constant. In any of the above cases, with this embodiment,
The same effect can be expected.
【0017】[0017]
【発明の効果】以上に説明したように、本発明によれ
ば、各転移容量、液晶容量、蓄積容量の3種類の容量
値、および、蓄積補償電位、対向電位の2種類の電圧値
を、適宜、副画素ごとに変化させることにより、各副画
素のT−V特性を変化させることができる。同時に、液
晶印加電圧を、ソース電圧振幅に加えて、蓄積補償電
位、対向電位の電圧振幅で生成するため、ソース電圧振
幅を低減することが可能となる。As described above, according to the present invention, three types of capacitance values of each transition capacitance, liquid crystal capacitance, and storage capacitance, and two types of voltage values of storage compensation potential and counter potential, By appropriately changing each sub-pixel, the TV characteristic of each sub-pixel can be changed. At the same time, since the liquid crystal applied voltage is generated with the voltage amplitude of the storage compensation potential and the counter potential in addition to the source voltage amplitude, the source voltage amplitude can be reduced.
【図1】本発明の実施例における薄膜トランジスタ液晶
表示装置の等価回路図FIG. 1 is an equivalent circuit diagram of a thin film transistor liquid crystal display device according to an embodiment of the present invention.
【図2】本発明の実施例における薄膜トランジスタ液晶
表示装置に印加される電位の電位関係図FIG. 2 is a potential relationship diagram of potentials applied to a thin film transistor liquid crystal display device in an example of the present invention.
【図3】本発明の実施例における薄膜トランジスタ液晶
表示装置の透過率(T)−ソース電圧振幅(V)特性図FIG. 3 is a characteristic diagram of transmittance (T) -source voltage amplitude (V) of a thin film transistor liquid crystal display device according to an embodiment of the present invention.
1 ゲート配線 2 ソース配線 3 蓄積容量配線 4 ドレイン電極 5 画素電極 5a 画素電極a 5b 画素電極b 6 薄膜トランジスタ 7 対向電極 8 転移容量 9 液晶容量 9a 液晶容量a 9b 液晶容量b 10 蓄積容量 10a 蓄積容量a 10b 蓄積容量b 101 ゲート電位 102 ソース電位 103 蓄積補償電位 107 対向電位 201a 液晶容量aにおけるT−V特性a 201b 液晶容量bにおけるT−V特性b 201c 画素全体のT−V特性 1 gate wiring 2 source wiring 3 storage capacity wiring 4 drain electrode 5 pixel electrode 5a pixel electrode a 5b pixel electrode b 6 thin film transistor 7 counter electrode 8 transition capacity 9 liquid crystal capacity 9a liquid crystal capacity a 9b liquid crystal capacity b 10 storage capacity 10a storage capacity a 10b Storage capacitance b 101 Gate potential 102 Source potential 103 Storage compensation potential 107 Counter potential 201a TV characteristic a in liquid crystal capacitance a 201b TV characteristic b in liquid crystal capacitance b 201c TV characteristic of the whole pixel
Claims (7)
蓄積容量配線がマトリクス状に形成され、前記ゲート配
線と前記ソース配線との各交点にドレイン電極、画素電
極、および、前記ゲート配線の電位により前記ソース配
線と前記ドレイン電極の導通を調節する薄膜トランジス
タが形成され、前記第1の基板に対向して設置された第
2の基板上に対向電極が形成され、前記画素電極が複数
の副画素電極から形成され、前記ドレイン電極と各前記
副画素電極間毎に転移容量が存在し、各前記副画素電極
と前記対向電極間毎に液晶容量が存在する薄膜トランジ
スタ液晶表示装置で、蓄積容量配線が複数の副蓄積容量
配線から形成され、各前記副画素電極と各前記副蓄積容
量配線間毎に蓄積容量を形成することを特徴とする薄膜
トランジスタ液晶表示装置。1. A gate wiring, a source wiring, and a wiring on a first substrate.
Storage capacitor wirings are formed in a matrix, and a drain electrode, a pixel electrode, and a thin film transistor that adjusts conduction between the source wiring and the drain electrode by a potential of the gate wiring at each intersection of the gate wiring and the source wiring. A counter electrode is formed on a second substrate that is disposed opposite to the first substrate, the pixel electrode is formed of a plurality of sub-pixel electrodes, and the drain electrode and each of the sub-pixel electrodes are formed. In a thin film transistor liquid crystal display device in which a transition capacitance exists for each sub-pixel electrode and a liquid crystal capacitance exists between the sub-pixel electrode and the counter electrode, a storage capacitance line is formed of a plurality of sub-storage capacitance lines, and each sub-pixel electrode And a storage capacitor is formed between each of the sub storage capacitor wirings.
極間に転移容量が存在せず、直接電気的に接続してい
る、請求項1記載の薄膜トランジスタ液晶表示装置。2. The thin film transistor liquid crystal display device according to claim 1, wherein there is no transition capacitance between the drain electrode and the at least one subpixel electrode, and the drain electrode and the at least one subpixel electrode are electrically connected directly.
配線間に、蓄積容量が存在せず、電気的に切断されてい
る、請求項1記載の薄膜トランジスタ液晶表示装置。3. The thin film transistor liquid crystal display device according to claim 1, wherein there is no storage capacitance between at least one subpixel electrode and the substorage capacitance line, and the storage capacitance is electrically disconnected.
積容量配線を兼用している、請求項1記載の薄膜トラン
ジスタ液晶表示装置。4. The thin film transistor liquid crystal display device according to claim 1, wherein the gate wiring in the preceding stage also serves as at least one sub storage capacitance wiring.
の電位がドレイン電極に伝達され、オフ期間に各副蓄積
容量配線、対向電極の電位が変化して、各副画素電極の
電位が変調されることを特徴とする、請求項1記載の薄
膜トランジスタ液晶表示装置の駆動法。5. The potential of the source electrode is transmitted to the drain electrode during the ON period of the thin film transistor, and the potentials of the sub-storage capacitance lines and the counter electrode are changed during the OFF period to modulate the potential of each sub-pixel electrode. The method for driving a thin film transistor liquid crystal display device according to claim 1, wherein:
一定である、請求項5記載の薄膜トランジスタ液晶表示
装置の駆動法。6. The method of driving a thin film transistor liquid crystal display device according to claim 5, wherein the potential of at least one sub-storage capacitance line is constant.
載の薄膜トランジスタ液晶表示装置の駆動法。7. The method of driving a thin film transistor liquid crystal display device according to claim 5, wherein the potential of the counter electrode is constant.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32249794A JP2993384B2 (en) | 1994-12-26 | 1994-12-26 | Thin film transistor liquid crystal display device and driving method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32249794A JP2993384B2 (en) | 1994-12-26 | 1994-12-26 | Thin film transistor liquid crystal display device and driving method thereof |
Publications (2)
Publication Number | Publication Date |
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JPH08179371A true JPH08179371A (en) | 1996-07-12 |
JP2993384B2 JP2993384B2 (en) | 1999-12-20 |
Family
ID=18144311
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005301226A (en) * | 2004-04-08 | 2005-10-27 | Samsung Electronics Co Ltd | Liquid crystal display and display plate used for the same |
JP2007241282A (en) * | 2006-03-06 | 2007-09-20 | Au Optronics Corp | Transflective liquid crystal display |
WO2011001707A1 (en) * | 2009-06-29 | 2011-01-06 | シャープ株式会社 | Display device and method for driving same |
US7868976B2 (en) | 2006-05-10 | 2011-01-11 | Au Optronics Corporation | Transflective liquid crystal display with gamma harmonization |
-
1994
- 1994-12-26 JP JP32249794A patent/JP2993384B2/en not_active Expired - Fee Related
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005301226A (en) * | 2004-04-08 | 2005-10-27 | Samsung Electronics Co Ltd | Liquid crystal display and display plate used for the same |
JP2007241282A (en) * | 2006-03-06 | 2007-09-20 | Au Optronics Corp | Transflective liquid crystal display |
JP2011022590A (en) * | 2006-03-06 | 2011-02-03 | Au Optronics Corp | Transflective liquid crystal display |
JP4638891B2 (en) * | 2006-03-06 | 2011-02-23 | 友達光電股▲ふん▼有限公司 | Transflective LCD |
US7868976B2 (en) | 2006-05-10 | 2011-01-11 | Au Optronics Corporation | Transflective liquid crystal display with gamma harmonization |
US8427414B2 (en) | 2006-05-10 | 2013-04-23 | Au Optronics Corporation | Transflective liquid crystal display with gamma harmonization |
WO2011001707A1 (en) * | 2009-06-29 | 2011-01-06 | シャープ株式会社 | Display device and method for driving same |
Also Published As
Publication number | Publication date |
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