JPH0817770A - Lapping method of silicon wafer and lapping slurry - Google Patents
Lapping method of silicon wafer and lapping slurryInfo
- Publication number
- JPH0817770A JPH0817770A JP17595294A JP17595294A JPH0817770A JP H0817770 A JPH0817770 A JP H0817770A JP 17595294 A JP17595294 A JP 17595294A JP 17595294 A JP17595294 A JP 17595294A JP H0817770 A JPH0817770 A JP H0817770A
- Authority
- JP
- Japan
- Prior art keywords
- lapping
- slurry
- silicon wafer
- powder
- solvent
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、シリコンウェーハのラ
ッピング方法およびそのラッピング時に使用されるスラ
リ中の界面活性剤の濃度に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of lapping a silicon wafer and a concentration of a surfactant in a slurry used in the lapping.
【０００２】[0002]
【従来の技術】一般に、スライシング後のシリコンウェ
ーハのラッピングは、主にＦｅ系の金属から構成された
上下定盤にウェーハを挟み込み、ウェーハを遊星運動さ
せることにより行われる。このとき、ラッピングスラリ
を一定の割合で定盤全面に供給する。ラッピングスラリ
は、一般に純水もしくは弱アルカリ系の溶剤中に、アル
ミナ（Ａｌ2Ｏ3）、ジルコニア（ＺｒＯ2）または炭化
珪素（ＳｉＣ）等のパウダを混入して構成されている。
このパウダとしては、その粒度が＃１０００〜＃１２０
０のものが使用されている。2. Description of the Related Art In general, lapping of a silicon wafer after slicing is performed by sandwiching the wafer between upper and lower surface plates mainly made of Fe-based metal, and causing the wafer to make a planetary motion. At this time, the lapping slurry is supplied to the entire surface of the surface plate at a constant rate. The lapping slurry is generally formed by mixing powder of alumina (Al 2 O 3 ), zirconia (ZrO 2 ) or silicon carbide (SiC) into pure water or a weak alkaline solvent.
This powder has a grain size of # 1000 to # 120.
0 is used.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、このよ
うな従来のシリコンウェーハのラッピング方法にあって
は、スラリ中のパウダが作業中に固まり、キズ、ワレ等
の不良を多発し易い環境を生み出していた。さらに、生
産性を考慮するとき、ラッピング荷重は、高いほうが好
ましいが、高くし過ぎると、キズ、ワレ等の上記不良を
さらに発生し易いという問題が生じていた。However, in such a conventional silicon wafer lapping method, the powder in the slurry is hardened during the work, and an environment in which defects such as scratches and cracks are likely to occur is created. It was Further, when considering the productivity, it is preferable that the lapping load is high, but if the lapping load is too high, there arises a problem that the above defects such as scratches and cracks are more likely to occur.
【０００４】そこで、本願発明者は、鋭意研究の結果、
スラリ中に界面活性剤を含ませた場合、その濃度に応じ
て、スラリ中でのパウダの固まり（クラスタ）度合、つ
まり分散効果が大きく異なることを知見した。図３は界
面活性剤濃度とラッピングパウダの平均粒径との関係を
示している。この分散効果が低下した状態でシリコンウ
ェーハをラッピングに供した場合、粒度の大きいパウダ
とシリコンウェーハ表面が擦り合わされてウェーハ上に
キズとしての軌跡が残留する。一方、パウダ粒径が極端
に小さい場合や、スラリ中のパウダ濃度が極端に低い場
合は、シリコンウェーハと定盤との直接接触によるキズ
を生じる。こうした現象によるキズ不良低減のため、ス
ラリ中のパウダの分散効果を一定値以上に規制すること
が重要である。Therefore, the inventor of the present application, as a result of earnest research,
We have found that when a surfactant is included in the slurry, the degree of clustering of the powder in the slurry, that is, the dispersion effect, greatly differs depending on the concentration of the surfactant. FIG. 3 shows the relationship between the surfactant concentration and the average particle size of the wrapping powder. When a silicon wafer is subjected to lapping in a state where the dispersion effect is reduced, powder having a large grain size and the surface of the silicon wafer are rubbed with each other, and a trace of scratches remains on the wafer. On the other hand, when the powder particle size is extremely small or the powder concentration in the slurry is extremely low, scratches are caused by direct contact between the silicon wafer and the surface plate. In order to reduce defects due to such phenomena, it is important to regulate the dispersion effect of powder in the slurry to a certain value or more.
【０００５】さらに、界面活性剤の濃度が上昇するにし
たがってスラリの表面張力は指数関数的に減少する（図
４）。この表面張力の減少に伴いパウダの平均粒子径も
小さくなる（図５）。平均粒子径が小さくなれば、分散
効果が大きくなる。以上のことから、パウダ粒子構成成
分と溶媒成分との間の物理量で決定されるところの表面
張力を一定範囲に設定しておけば、常にキズ等の不良の
発生を低減することができることを知見した。Furthermore, the surface tension of the slurry exponentially decreases as the surfactant concentration increases (FIG. 4). As the surface tension decreases, the average particle size of the powder also decreases (Fig. 5). The smaller the average particle size, the greater the dispersion effect. From the above, it was found that the occurrence of defects such as scratches can always be reduced by setting the surface tension, which is determined by the physical quantity between the powder particle constituent component and the solvent component, within a certain range. did.
【０００６】また、ラッピングレートとキズ不良項目と
の関係についても研究した。その結果、図２に示すよう
に、ラッピングレートが大きい場合、生産性は良好であ
るが不良率が高くなる。これは、適正なスラリ条件であ
っても、定盤との擦れが促進されやすい環境にあること
によると考えられる。したがって、不良率が一定となる
１０μｍ／分以下のラッピングレートで生産することが
最も有利であることが判る。なお、ラッピングレートは
主として荷重の調整による。Further, the relationship between the lapping rate and the defective item of scratch was also studied. As a result, as shown in FIG. 2, when the lapping rate is high, the productivity is good but the defective rate is high. It is considered that this is due to the fact that the rubbing with the surface plate is easily promoted even under appropriate slurry conditions. Therefore, it can be seen that it is most advantageous to produce at a lapping rate of 10 μm / min or less where the defect rate becomes constant. The lapping rate is mainly due to the adjustment of the load.
【０００７】そこで、本発明の目的は、ラッピングにお
けるキズ等の不良を低減することである。また、本発明
の他の目的は、生産性を損なうことがないラッピング方
法を提供することである。Therefore, an object of the present invention is to reduce defects such as scratches in lapping. Another object of the present invention is to provide a lapping method that does not impair productivity.
【０００８】[0008]
【課題を解決するための手段】請求項１に記載の発明
は、使用するラッピングスラリの表面張力を３８ｄｙｎ
ｅ／ｃｍ以下にしたラッピング方法である。特に、３０
〜３４ｄｙｎｅ／ｃｍとする。According to the invention described in claim 1, the surface tension of the lapping slurry used is 38 dyn.
It is a lapping method with e / cm or less. Especially 30
~ 34 dyne / cm.
【０００９】また、請求項３に記載の発明は、請求項１
のラッピングスラリを使用し、かつ、そのラッピングレ
ートを１０μｍ／分以下とする。さらに、請求項４に記
載の発明は、ラッピングレートを１０μｍ／分以下にす
る方法である。The invention described in claim 3 is the same as claim 1
The lapping slurry is used and the lapping rate is 10 μm / min or less. Furthermore, the invention described in claim 4 is a method of setting the lapping rate to 10 μm / min or less.
【００１０】また、請求項５〜８に記載した発明は、表
面張力が３８ｄｙｎｅ／ｃｍ以下のラッピングスラリを
提供する。The invention described in claims 5 to 8 provides a lapping slurry having a surface tension of 38 dyne / cm or less.
【００１１】[0011]
【作用】請求項１、２に記載した発明によれば、溶媒中
のラッピングパウダの分散効果を適正に保つことがで
き、シリコンウェーハ表面のキズ等の不良を低減するこ
とができる。According to the first and second aspects of the present invention, the effect of dispersing the lapping powder in the solvent can be properly maintained, and defects such as scratches on the surface of the silicon wafer can be reduced.
【００１２】また、請求項３、４に記載した発明では、
生産性を高めつつ、スラリ中のパウダの固まりによる定
盤とシリコンウェーハとの擦れを最小限に止め、キズ発
生を抑制する。According to the invention described in claims 3 and 4,
While improving productivity, it minimizes the friction between the surface plate and the silicon wafer due to the powder mass in the slurry, and suppresses the occurrence of scratches.
【００１３】さらに、請求項５〜８の発明に係るラッピ
ングスラリを用いてラッピングすることにより、キズ等
の発生が少ないシリコンウェーハを得ることができる。Further, by lapping using the lapping slurry according to the invention of claims 5 to 8, a silicon wafer with few scratches and the like can be obtained.
【００１４】[0014]
【実施例】以下、本発明の実施例を図面を参照して説明
する。図１は、シリコンウェーハのラッピングにおける
界面活性剤濃度とキズ不良発生率との関係を示してい
る。このグラフは、界面活性剤濃度４重量％、界面活性
剤濃度１重量％の各場合における、ラッピングレート９
μｍ／分でウェーハをラッピング処理した場合のキズ不
良の発生率を比較したものである。サンプルＮｏ．１〜
３（１重量％）とＮｏ．４〜１０（４重量％）との間で
は、キズ不良発生率が顕著に減少していることが判る。
使用したシリコンウェーハは、６インチのＣＺウェー
ハ、（１００）、Ｐ型またはＮ型、抵抗は１〜５０オー
ム・ｃｍである。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the relationship between the surfactant concentration and the flaw defect occurrence rate in lapping a silicon wafer. This graph shows a lapping rate of 9 when the surfactant concentration is 4% by weight and the surfactant concentration is 1% by weight.
It is a comparison of occurrence rates of flaw defects when lapping the wafer at μm / min. Sample No. 1 to
3 (1% by weight) and No. It can be seen that the scratch defect occurrence rate significantly decreases between 4 and 10 (4% by weight).
The silicon wafer used is a 6-inch CZ wafer, (100), P-type or N-type, and the resistance is 1 to 50 ohm · cm.
【００１５】この実施例に用いた設備は以下の仕様であ
る。 ラッピングマシン：スピードファム（株）製、「２０
Ｂ」 スラリ： １）界面活性剤：パレス化学（株）製、「ＬＡＰ−Ｐ−
５１Ａ」 ２）防錆剤：パレス化学（株）製、「ＬＡＰ−Ｐ−５
１」 ３）パウダ：不二見研磨剤工業（株）製、「ＦＯ＃１０
００」 なお、使用するパウダとしてはスラリの組成等に応じて
＃６００〜＃２０００程度のものを使用することができ
る。The equipment used in this example has the following specifications. Wrapping machine: "20" manufactured by Speed Fam Co., Ltd.
B "Slurry: 1) Surfactant: manufactured by Palace Chemical Co., Ltd.," LAP-P-
51A "2) Rust preventive agent: manufactured by Palace Chemical Co., Ltd.," LAP-P-5 "
1 ”3) Powder:“ FO # 10 ”manufactured by Fujimi Abrasive Industry Co., Ltd.
00 ”It should be noted that the powder to be used may be about # 600 to # 2000 depending on the composition of the slurry and the like.
【００１６】[0016]
【発明の効果】本発明は、シリコンウェーハのラッピン
グにあって、キズ等の不良を低減することができる。ま
た、生産性を良好に維持しつつ、不良率を一定として、
最も有利な条件でラッピングウェーハを生産することが
できる。The present invention can reduce defects such as scratches when lapping a silicon wafer. Also, while maintaining good productivity, the defect rate is kept constant,
Lapping wafers can be produced under the most advantageous conditions.
【図１】本発明の一実施例に係るラッピングにおけるキ
ズ発生率と界面活性剤濃度との関係を示すグラフであ
る。FIG. 1 is a graph showing a relationship between a scratch occurrence rate and a surfactant concentration in lapping according to an example of the present invention.
【図２】本発明に係るラッピングレートとキズ発生率と
の関係を示すグラフである。FIG. 2 is a graph showing a relationship between a lapping rate and a scratch occurrence rate according to the present invention.
【図３】本発明に係るラッピングにおける界面活性剤濃
度とパウダの平均粒径との関係を示すグラフである。FIG. 3 is a graph showing the relationship between the surfactant concentration and the average particle size of powder in the wrapping according to the present invention.
【図４】本発明に係るラッピングにおける界面活性剤濃
度とスラリの表面張力との関係を示すグラフである。FIG. 4 is a graph showing the relationship between the surfactant concentration and the surface tension of slurry in lapping according to the present invention.
【図５】本発明に係るラッピングにおけるスラリの表面
張力とパウダの平均粒径との関係を示すグラフである。FIG. 5 is a graph showing the relationship between the surface tension of the slurry and the average particle diameter of the powder in lapping according to the present invention.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 松下 秀樹 東京都千代田区岩本町３丁目８番16号 三 菱マテリアルシリコン株式会社内 (72)発明者 田中 正樹 東京都千代田区岩本町３丁目８番16号 三 菱マテリアルシリコン株式会社内 (72)発明者 高石 和成 東京都千代田区岩本町３丁目８番16号 三 菱マテリアルシリコン株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Hideki Matsushita 3-8-16 Iwamoto-cho, Chiyoda-ku, Tokyo Sanryo Material Silicon Co., Ltd. (72) Masaki Tanaka 3--8, Iwamoto-cho, Chiyoda-ku, Tokyo No. 16 Sanritsu Material Silicon Co., Ltd. (72) Inventor Kazunari Takaishi 3-8-16 Iwamotocho, Chiyoda-ku, Tokyo Sanritsu Material Silicon Co., Ltd.
Claims (7)
されるシリコンウェーハ用のラッピングスラリを使用し
てシリコンウェーハをラッピングするシリコンウェーハ
のラッピング方法において、 上記ラッピングスラリの表面張力を３８ｄｙｎｅ／ｃｍ
以下としたシリコンウェーハのラッピング方法。1. A method of lapping a silicon wafer using a lapping slurry for a silicon wafer comprising a solvent and a lapping powder, wherein the surface tension of the lapping slurry is 38 dyne / cm.
The following methods for lapping silicon wafers.
〜３４ｄｙｎｅ／ｃｍとした請求項１に記載のシリコン
ウェーハのラッピング方法。2. The surface tension of the lapping slurry is set to 30.
The method for lapping a silicon wafer according to claim 1, wherein the lapping method is about 34 dyne / cm.
リを使用してシリコンウェーハをラッピングするラッピ
ング方法にあって、 シリコンウェーハ１枚当りのラッピングレートを１０μ
ｍ／分以下とした請求項１に記載のシリコンウェーハの
ラッピング方法。3. A lapping method for lapping a silicon wafer using the lapping slurry according to claim 1, wherein a lapping rate per silicon wafer is 10 μm.
The method for lapping a silicon wafer according to claim 1, wherein the lapping rate is not more than m / min.
て、ウェーハ１枚当りのラッピングレートを１０μｍ／
分以下としたシリコンウェーハのラッピング方法。4. In lapping a silicon wafer, the lapping rate per wafer is 10 μm /
Lapping method for silicon wafers of less than a minute.
剤とからなるラッピングスラリであって、 その表面張力を３８ｄｙｎｅ／ｃｍ以下としたとしたラ
ッピングスラリ。5. A lapping slurry comprising a solvent, a lapping powder and a surfactant, the lapping slurry having a surface tension of 38 dyne / cm or less.
である請求項５に記載のラッピングスラリ。6. The lapping slurry according to claim 5, wherein the solvent is pure water or an alkaline solvent.
は炭化珪素である請求項５に記載のラッピングスラリ。7. The lapping slurry according to claim 5, wherein the lapping powder is alumina or silicon carbide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17595294A JP3061531B2 (en) | 1994-07-04 | 1994-07-04 | Silicon wafer lapping method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17595294A JP3061531B2 (en) | 1994-07-04 | 1994-07-04 | Silicon wafer lapping method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0817770A true JPH0817770A (en) | 1996-01-19 |
| JP3061531B2 JP3061531B2 (en) | 2000-07-10 |
Family
ID=16005127
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17595294A Expired - Lifetime JP3061531B2 (en) | 1994-07-04 | 1994-07-04 | Silicon wafer lapping method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3061531B2 (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000003509A (en) * | 1998-06-29 | 2000-01-15 | 김영환 | Method for preventing polishing material used for chemical mechanical polishing process from condensing |
| US6177343B1 (en) | 1995-09-14 | 2001-01-23 | Sanyo Electric Co., Ltd. | Process for producing semiconductor devices including an insulating layer with an impurity |
| US6214749B1 (en) | 1994-09-14 | 2001-04-10 | Sanyo Electric Co., Ltd. | Process for producing semiconductor devices |
| US6235648B1 (en) | 1997-09-26 | 2001-05-22 | Sanyo Electric Co., Ltd. | Semiconductor device including insulation film and fabrication method thereof |
| US6288438B1 (en) | 1996-09-06 | 2001-09-11 | Sanyo Electric Co., Ltd. | Semiconductor device including insulation film and fabrication method thereof |
| US6326318B1 (en) | 1995-09-14 | 2001-12-04 | Sanyo Electric Co., Ltd. | Process for producing semiconductor devices including an insulating layer with an impurity |
| US6690084B1 (en) | 1997-09-26 | 2004-02-10 | Sanyo Electric Co., Ltd. | Semiconductor device including insulation film and fabrication method thereof |
| US6794283B2 (en) | 1998-05-29 | 2004-09-21 | Sanyo Electric Co., Ltd. | Semiconductor device and fabrication method thereof |
| US6825132B1 (en) | 1996-02-29 | 2004-11-30 | Sanyo Electric Co., Ltd. | Manufacturing method of semiconductor device including an insulation film on a conductive layer |
| US6831015B1 (en) | 1996-08-30 | 2004-12-14 | Sanyo Electric Co., Ltd. | Fabrication method of semiconductor device and abrasive liquid used therein |
| US6917110B2 (en) | 2001-12-07 | 2005-07-12 | Sanyo Electric Co., Ltd. | Semiconductor device comprising an interconnect structure with a modified low dielectric insulation layer |
| US6984167B2 (en) | 2002-10-29 | 2006-01-10 | Tatsumori Ltd. | Polishing agent and lapping method |
-
1994
- 1994-07-04 JP JP17595294A patent/JP3061531B2/en not_active Expired - Lifetime
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6214749B1 (en) | 1994-09-14 | 2001-04-10 | Sanyo Electric Co., Ltd. | Process for producing semiconductor devices |
| US6268657B1 (en) | 1995-09-14 | 2001-07-31 | Sanyo Electric Co., Ltd. | Semiconductor devices and an insulating layer with an impurity |
| US6177343B1 (en) | 1995-09-14 | 2001-01-23 | Sanyo Electric Co., Ltd. | Process for producing semiconductor devices including an insulating layer with an impurity |
| US6326318B1 (en) | 1995-09-14 | 2001-12-04 | Sanyo Electric Co., Ltd. | Process for producing semiconductor devices including an insulating layer with an impurity |
| US6825132B1 (en) | 1996-02-29 | 2004-11-30 | Sanyo Electric Co., Ltd. | Manufacturing method of semiconductor device including an insulation film on a conductive layer |
| US6831015B1 (en) | 1996-08-30 | 2004-12-14 | Sanyo Electric Co., Ltd. | Fabrication method of semiconductor device and abrasive liquid used therein |
| US6288438B1 (en) | 1996-09-06 | 2001-09-11 | Sanyo Electric Co., Ltd. | Semiconductor device including insulation film and fabrication method thereof |
| US6235648B1 (en) | 1997-09-26 | 2001-05-22 | Sanyo Electric Co., Ltd. | Semiconductor device including insulation film and fabrication method thereof |
| US6690084B1 (en) | 1997-09-26 | 2004-02-10 | Sanyo Electric Co., Ltd. | Semiconductor device including insulation film and fabrication method thereof |
| US6794283B2 (en) | 1998-05-29 | 2004-09-21 | Sanyo Electric Co., Ltd. | Semiconductor device and fabrication method thereof |
| KR20000003509A (en) * | 1998-06-29 | 2000-01-15 | 김영환 | Method for preventing polishing material used for chemical mechanical polishing process from condensing |
| US6917110B2 (en) | 2001-12-07 | 2005-07-12 | Sanyo Electric Co., Ltd. | Semiconductor device comprising an interconnect structure with a modified low dielectric insulation layer |
| US6984167B2 (en) | 2002-10-29 | 2006-01-10 | Tatsumori Ltd. | Polishing agent and lapping method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3061531B2 (en) | 2000-07-10 |
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