JPH0817494B2 - Driving circuit for matrix liquid crystal display - Google Patents

Description

The present invention relates to a drive circuit for a matrix liquid crystal display.

Conventionally, various types of liquid crystal have been put into practical use, such as guest-host type, color-polarizing plate type, and color filter type, but there are problems such as high-density pixel technology, three primary color generation methods, and improvement of brightness in image display. Yes, and what has been tried so far is TFT
It is a method to solve the problem by using an active matrix liquid crystal panel such as.

In a conventional matrix liquid crystal display drive circuit,
In order to supply a video signal of three primary colors corresponding to the color arrangement to a matrix liquid crystal display in which pixels arranged in a matrix are associated with the three primary colors, analog video signals of the three primary colors are selected and driven by a matrix circuit. Supply to the circuit was done. However, in this configuration, switching noise when driving the analog switches that form the matrix circuit becomes a problem. The level fluctuation when the analog switch is switched is superimposed on the analog video signal to become a video signal containing level fluctuation noise, and when the video signal is displayed, the image quality is deteriorated. In addition, as another problem, in order to select a video signal including a high frequency component via an analog switch, it is necessary to increase the size of the analog switch to provide a flat frequency characteristic up to a high band. There is also a contradictory problem that the parasitic capacitance of the switch becomes large and the high frequency signal is dull.

An object of the present invention is to solve such a problem and reduce the influence of circuit noise of a matrix circuit when selecting a three-primary-color video signal according to the color arrangement of a liquid crystal display on the video signal to reduce the video signal. It is to realize a drive circuit that enhances the S / N ratio and that enables a high-quality color display on a matrix liquid crystal display.

That is, the present invention is a drive circuit for a matrix liquid crystal display in which a plurality of pixels are arranged in a matrix and the three primary colors are associated with the pixels in the array in a predetermined order, and an analog video signal of the three primary colors is output. Signal processing circuit, an AD conversion circuit of three series for converting the analog video signals of the three primary colors into digital video signals of the three primary colors, and an arrangement order of the primary colors associated with the pixels of the matrix liquid crystal display. And a matrix circuit for selectively outputting the digital video signals of the three primary colors output from the AD conversion circuit, and pixels of pixels in each column of the matrix liquid crystal display according to the digital video signal output from the matrix circuit. And a drive circuit for outputting a display body signal supplied to the electrodes.

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of main components of a liquid crystal display color television using a drive circuit for a matrix liquid crystal display of the present invention. Portions not directly related to the present invention have been omitted or simply shown. Reference numeral 1 in FIG. 1 denotes a color television signal processing circuit, which receives television radio waves, performs sync signal separation, color signal processing, etc., and generates RGB three primary color signals. The configuration itself of this color television signal processing circuit is a well-known technique. The analog video signals of the three primary colors of RGB are respectively connected to AD conversion circuits 2, 3 and 4 and converted into digital signals at a predetermined clock timing. For television, 4-bit digitization is sufficient. The frequency of the AD conversion clock changes according to the number of pixels in the horizontal direction of the dot matrix liquid crystal display body 11. In the case of a small TV, the number of pixels in both the vertical and horizontal directions is half that of a normal home TV receiver, so the AD conversion clock is 4 at that time.
It becomes a clock of ~ 5MHz. It is conceivable to provide a matrix switching circuit after analog output of RGB and use only one AD conversion circuit. But as a frequency band
In order to pass a video signal containing a frequency component up to around 3MHz, an analog switch having flat frequency characteristics up to a high frequency must be constructed. In particular, for liquid crystal color televisions, monolithic circuits, preferably CMOS circuits, are desired with the aim of downsizing and low power consumption. However, in the CMOS-IC, in order to improve the high frequency characteristics of the analog switch, it is necessary to increase the size of the transistor forming the analog switch to reduce the ON resistance. However, when the transistor becomes large, the parasitic capacitance becomes large, so that the input capacitance of the analog switch itself also increases, and the high frequency characteristics of the input video signal deteriorate.

Furthermore, since the switching signal of the analog switch is a clock of 4 to 5 MHz corresponding to the sampling time of the pixel, it is extremely difficult to suppress the leakage of switching noise generated by the clock signal in the analog video signal to be switched. .

Therefore, in the present invention, after AD conversion is performed in three systems corresponding to the three primary colors of color, the converted digital video signals are rearranged using a matrix circuit to form a color video signal sequence. Since the digitized video signal has a binary value of 0 and 1, it is needless to say that it is more resistant to noise by switching with a high-speed clock than an analog video signal. The control circuit 6 receives various horizontal synchronizing signals and vertical synchronizing signals from the color television signal processing circuit 1 to generate various timing signals. This includes an AD conversion clock, an electrode selection clock for the common electrode drive circuit 7, an AC inversion signal, a data write clock for the pixel electrode drive circuits 8-10, a latch pulse, an AC inversion signal, and a timing signal for the matrix circuit 5. Etc. are included. Pixel electrode drive circuit 8 ~
10 is required to read 4-bit data output from the matrix circuit into the shift register in series at a predetermined timing and transfer the data to the memory by the latch pulse synchronized with the selection clock of the common electrode. It has a built-in memory. 16 from 4-bit data
The conversion of gradation into a drive signal is also performed in the pixel electrode drive circuit. The dot matrix liquid crystal display 11 employs a pixel electrode structure having a triple inversion matrix structure as shown in FIG. 2 in the example of the present invention. However, in essence, it is not necessary to stick to the triple matrix. However, when signals are distributed in an array of three primary colors as in a color television, the triple matrix is easy in terms of circuit processing.

FIG. 2 shows how the pixel electrodes are arranged, which is an example of the liquid crystal display used in the present invention. Reference numerals 12 to 14 denote lead-out electrode terminals, and the rows of the terminals 12 and the rows of the terminals 14 are formed in different stages so that the connection terminal pitch is equivalently widened. As shown in the figure, the row of the terminals 12 extracts the RGBRGB signal row from the first horizontal scanning signal and displays it, and further extracts the BRGBRG signal row from the sixth horizontal scanning signal to display. Configure. Therefore, 4-bit data to the pixel electrode drive circuit 8 connected to the column of the terminal 12 is created as a signal of the RGB column from the (1 + 6n) horizontal scanning signal in the matrix circuit. Here, n is 0 or a positive integer. The pixel electrode drive circuit 9 is connected to the terminal row 14, but in this case, BR
It is a G or RGB signal sequence. However, the pixel electrode drive circuit 10 connected to the terminal row 13 may be a signal row only for GBR. It is important to note that the arrangement of RGB of the three primary colors is not limited to the main row, but there are various arrangements. FIG. 2 shows a part of the pixel electrode. In practice, this arrangement is repeated to form 30,000 to 50,000 pixels or more. Corresponding to each pixel electrode,
A color filter for generating the three primary colors of RGB is arranged. The display electrode only controls the degree of on / off of the liquid crystal, and the actual color is to see the light of the white backlight placed on the back through the color filter.

FIG. 3 is a logic diagram of a part of the configuration of the matrix circuit, and shows a circuit for creating supply data to the pixel electrode drive circuit 8. Reference numeral 15 is a 6-divided circuit, a horizontal synchronizing signal is input to the terminal 16, and 6n + 1,6n + 2,6n + 3,6n + 4,6n + 5,6n + 6
It is formed so that one horizontal scanning period can be identified. That is,
When the first horizontal synchronizing signal is input, the output 1 becomes high level, the other outputs are low level, and when the second horizontal synchronizing signal is input, the output 2 is output.
Is set to a high level and other outputs are set to a low level. Reference numeral 17 is a circuit for dividing the AD conversion clock into three, and the AD conversion clock is input to the input 18. This clock has the same cycle as the clock for reading data into the pixel electrode drive circuit.
This is used for rearranging color signals such as RGB. 19 is an AND circuit signal, and 20 is an OR circuit symbol. R _{1 to} R ₈ are the outputs of the AD conversion circuit 2 receiving the red signal, and G _{1 to} G ₈ are the same as AD.
Outputs of the conversion circuit 3, B _{1 to} B ₈ are outputs of the AD conversion circuit 4. As a result, the inputs D _{1 to} D ₈ to the pixel electrode drive circuit ₈
In the horizontal scanning period of 6n + 1, the signal sequence of RGBRGB, 6n + 6
The signal sequence of BRGBRG is generated in the horizontal scanning period of. Other signal trains can be formed in the same manner. In this example, the drive signal of the common electrode is switched every three horizontal scanning periods, so that the clock can be formed by using the output a of the three-division circuit 17 in FIG.

As described above, the present invention can obtain the following remarkable effects.

a) When selected and output in the state of an analog video signal, the changed analog level is superimposed as a result of switching and is displayed as noise as it is, but the level fluctuation noise does not affect the discrimination of the binary of the digital signal. In the present invention, the matrix circuit is configured to selectively output in the state of the digital video signal.
It is hardly affected by level fluctuation noise when selectively outputting primary color video signals.

b) In the matrix circuit, since the video signal is selected in the form of a digital signal, the size of the digital switch element forming the matrix circuit can be reduced,
In a small digital switch element, level fluctuation and parasitic capacitance are reduced as compared with an analog switch, so that noise generation is reduced.

c) Since the digital video signal is selected by the matrix circuit for inputting / outputting the digital signal, the circuit does not have a large size like an analog switch, and the circuit can be integrated, whereby the matrix circuit can be downsized.

As described above, according to the present invention, when the video signals of the three primary colors are selected and output according to the arrangement order of the primary colors associated with the pixels of the matrix liquid crystal display, the digital video signals are selectively output via the matrix circuit. Therefore, it is possible to reduce the influence of noise on the video signal, improve the S / N ratio of the video signal, and obtain high-quality video with less noise.

[Brief description of drawings]

FIG. 1 is a block diagram of main components of a liquid crystal display color television using the matrix liquid crystal display of the present invention. 1 ... Color television signal processing circuit 2-4 ... AD conversion circuit 5 ... Matrix circuit 6 ... Control circuit 7 ... Common electrode drive circuit 8-10 ... Pixel electrode drive circuit 11 ... Dot matrix liquid crystal display FIG. 2 shows a part of how the pixel electrodes are arranged. 12 to 14 ... Lead-out terminal portion of pixel electrode FIG. 3 is a logic diagram of a part of the configuration of the matrix circuit. 15 …… 6 division circuit 17 …… 3 division circuit 19 …… AND circuit symbol 20 …… OR circuit symbol

Claims (2)

[Claims] 1. A drive circuit for a matrix liquid crystal display in which a plurality of pixels are arranged in a matrix, and three primary colors are associated with the pixels in the array in a predetermined order, and an analog video signal of the three primary colors is output. A signal processing circuit,
Three series of AD conversion circuits for respectively converting the three primary color analog video signals into three primary color digital video signals, and the AD conversion circuit according to the arrangement order of the primary colors associated with the pixels of the matrix liquid crystal display. A matrix circuit for selectively outputting the digital video signals of the three primary colors to be output by, and a display for supplying the pixel electrodes of the pixels of each column of the matrix liquid crystal display body according to the digital video signals output from the matrix circuit. A drive circuit for a matrix liquid crystal display, comprising: a drive circuit for outputting a signal. 2. The matrix circuit, when ABC is one selected from six permutations of three primary colors, ABC in the first horizontal scanning period, BCA in the second horizontal scanning period, and third. 3. The drive circuit for the matrix liquid crystal display according to claim 1, wherein the digital video signals are repeatedly selected and output in the CAB order during the horizontal scanning period.