JPH08172136A - Mos inverter forming method - Google Patents

Abstract

PURPOSE: To minimize the delay in MOS inverters while securing a drive capacity by narrowing down a semiconductor layer between the MOS inverters in a region between the MOS inverters. CONSTITUTION: When providing a circuit where a plurality of stages of MOS inverters are connected in series within an LSI, semiconductor layers with the same polarity are commonly used for a plurality of MOS inverters to form the MOS inverters. In that case, the width of the semiconductor layers is narrowed down between the MOS inverters. For example, inverters I1 and I2 of an inverted amplifier INV consisting of three stages of MOS inverters I1-I3 are formed by common P-type semiconductor part PL1 and N-type semiconductor part NL1 and the L3 is formed by P-type semiconductor layer PL2 and N-type semiconductor layer NL2. Then, a narrow part S1 is provided at the semiconductor layer PL1 and a narrow part S3 is provided at the semiconductor layer NL1. Also, a narrow part S2 is provided at the semiconductor layer PL2 and a narrow part S4 is provided at the semiconductor layer NL2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a MOS inverter, and more particularly to a method for forming a MOS inverter when a circuit in which a plurality of stages of MOS inverters are connected in series, for example, an inverting amplifier is formed in an LSI.

[0002]

2. Description of the Related Art The inventors of the present invention have filed Japanese Patent Application No. 05-020.
No. 676 proposes the multiplication circuit shown in FIG. This multiplication circuit outputs an analog voltage obtained by multiplying the analog input voltage by a digital multiplier by the weight of capacitive coupling, and outputs this output as two-stage inverting amplifiers INV1 and INV.
2 or INV3, INV2 to ensure stability and accuracy of the output. These inverting amplifiers are composed of three-stage MOS inverters, the output of which is connected to the input via a feedback capacitance. The inverting amplifier secures the linearity and stability of the output by a large open gain obtained by multiplying the gain of the MOS inverter triple.

Here, a sufficient amount of current supply is necessary to increase the drive capability of the inverting amplifier, but when the current becomes large, the parasitic capacitance of each transistor generally increases and the circuit delay becomes large. there were.

[0004]

SUMMARY OF THE INVENTION The present invention was devised to solve the above-mentioned conventional problems, and provides a method for forming a MOS inverter capable of minimizing the delay of the MOS inverter while ensuring the drive capability. The purpose is to provide.

[0005]

A method of forming a MOS inverter according to the present invention narrows a semiconductor layer extending between MOS inverters between MOS inverters.

[0006]

According to the present invention, since the current between the MOS inverters is suppressed, the parasitic capacitance of the transistor is reduced, and the current supply amount of the final stage MOS inverter is not limited, so that the drive capability is guaranteed.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, one embodiment of a MOS inverter forming method according to the present invention will be described with reference to the drawings.

FIG. 1 shows a three-stage MOS inverter I1, I
2 shows an LSI pattern of an inverting amplifier INV composed of 2 and I3, wherein the inverters I1 and I2 are formed by using a common P-type semiconductor portion PL1 and N-type semiconductor portion NL1.
I3 is formed by the P-type semiconductor layer PL2 and the N-type semiconductor layer NL2. A drain voltage Vdd and a source voltage Vss are connected to PL1 and NL1 via contacts (metal portions penetrating the semiconductor layer) C1 and C2. On the other hand, PL2 and NL2 are connected to the drain voltage Vdd and the source voltage Vss via contacts C7 and C8.

The semiconductor layers PL1 and NL1 have contacts C3 and C4 for the first-stage output and contacts C for the second-stage output.
5 and C6 are provided, and the output is led to the subsequent stage through the polysilicon portion PS connected to these contacts.

The semiconductor layers PL2, NL2 are provided with contacts C9, C10 for the third stage output, and the output is led to the latter stage through the polysilicon portion PS connected to these contacts.

The contact C is formed on the semiconductor layer PL1.
The narrowed portion S1 is provided between the contacts C1 and C5, and the narrowed portion S1 is placed between the contacts C2 and C6 in the semiconductor layer NL1.
3 is provided. Further, the semiconductor layer PL2 is provided with a narrowed portion S2 at a position between the contacts C7 and C9, and the semiconductor layer NL2 is provided at a position between the contacts C8 and C10.
A narrowed portion S4 is provided.

These narrowed portions S1 and S3 are provided with an inverter I2
Output current is regulated, and this current reduction reduces the parasitic capacitance of the transistor forming I2. The delay of the inverter I2 is suppressed by the reduction of the parasitic capacitance, and the responsiveness is improved. The formation of the constricted portion generally causes the output instability and the increase of the parasitic capacitance on the input side due to the narrow channel effect. However, these adverse effects are less in the second stage inverter, and rather the effect of improving the responsiveness by reducing the parasitic capacitance on the output side is obtained. high. On the other hand, the narrowed portions S2 and S4 regulate the output current of the inverter I3 at the final stage, whereby a power saving effect is obtained. The final stage inverter may have the same adverse effect as the first stage inverter, but the size of the narrowed portion (the degree of the diaphragm) should be determined in consideration of the balance between the power saving effect and the drive capability. is there.

Although the above embodiments relate to a three-stage inverter, a circuit in which a plurality of stages of MOS inverters are connected in series is used in an LSI by commonly using semiconductor layers of the same polarity across a plurality of MOS inverters. It can be applied to any configuration provided.

[0012]

As described above, in the method of forming a MOS inverter according to the present invention, since the semiconductor layer extending between the MOS inverters is narrowed between the MOS inverters, the current between the MOS inverters is suppressed and the parasitic capacitance of the transistor is reduced. Response performance is improved and the final stage MOS
Since the current supply amount of the inverter is not limited, it has an excellent effect that the drive capacity is guaranteed.

[Brief description of drawings]

FIG. 1 is a plan view showing one embodiment of a method for forming a MOS inverter according to the present invention.

FIG. 2 is a circuit diagram showing a circuit example to which the present invention can be applied.

[Explanation of symbols]

 INV. . . Inverting amplifiers I1, I2, I3. . . MOS inverter PL. . . P layer NL. . . N layers C1, C2, C3, C4, C5, C6. . . Contact PS. . . Polysilicon S1, S2, S3, S4. . . Stenosis Vdd. . . Drain voltage Vss. . . Source voltage.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Makoto Yamamoto 3-5-18 Kitazawa, Setagaya-ku, Tokyo Takayama Building Co., Ltd. (72) Inventor Nao Takatori 3-5-18 Kitazawa, Setagaya-ku, Tokyo Takayama Building Shares Company Takayamauchi

Claims (2)

[Claims] 1. When a circuit in which a plurality of stages of MOS inverters are connected in series is provided in an LSI, a semiconductor layer having the same polarity is commonly used over a plurality of MOS inverters.
A method of forming an S inverter, wherein a width of a semiconductor layer is narrowed between MOS inverters. 2. The method for forming a MOS inverter according to claim 1, wherein the circuit is an inverting amplifier whose input and output are connected via a feedback capacitance.