JPH08167712A - Semiconductor device and ic - Google Patents

Abstract

PURPOSE: To reduce the fall time of an IGBT included in an IC by ordinary IC technology without irradiation with an electron beam by extracting a second conductivity type semiconductor layer including a collector region formed of a first conductivity type semiconductor layer as an electrode. CONSTITUTION: A heavily doped control collector layer 4 is provided on an N-type substrate 1, and brought into ohmic contact with an output electrode 4b. The potential of a second conductivity type semiconductor layer including the layer 4 made of a first conductivity type semiconductor is output as an electrode, and a circuit for short-circuiting a collector electrode 3a to a control electrode at the time of OFF of a lateral IGBT is added in an IC including the IGBT. Thus, carrier flowing to a MOS is fed from the layer 4 to the control collector electrode via the second layer and the electrode 3a via short-circuiting. Thus, at the time of OFF of the IGBT, the injection of excess carriers from the first layer to the second layer is eliminated, and hence a fall time can be shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a lateral IBGT (In
IC with output gate of modulated gate bipolar transistor
The present invention relates to a semiconductor device that speeds up switching speed and reduces switching loss.

[0002]

2. Description of the Related Art An IC having a lateral IBGT as an output stage
Nikkei Microdevices, June 1990 issue, 85
As shown in FIG. 2 and FIG. 2, an upper arm element that is a source switch and a lower arm element that is a sink switch are configured as a totem pole with a lateral IGBT. It is a three-phase brushless motor drive inverter IC composed of a minute drive circuit. The frequency of the inverter circuit is set to a high frequency that exceeds the audible range to reduce noise, and to increase switching loss, electron beam irradiation is used to control the lifetime to increase the switching speed when off. ing. The operation of the IGBT will be described below. FIG. 5 shows an example of a cross-sectional structure of a lateral IGBT, which is an enhancement type. This structure consists of NMOS transistor and PN
It has a composite structure of P bipolar transistors. N
A substrate forming a NMOS transistor and a channel forming layer 5 are formed on the surface of the mold substrate 1, and an N emitter layer 6 (N emitter of IGBT) serving as a source is formed in the channel forming layer 5. The channel forming layer 5 and the N emitter layer 6 are short-circuited by the electrode 6a (IGBT emitter electrode). The gate of the NMOS transistor is formed by forming polycrystalline Si 7 on the N-type substrate 1 with a gate oxide film 8 interposed. The channel forming layer 5 and the N emitter layer 6 are polycrystalline S
It is formed using i7 as a diffusion mask. On the other hand, in the PNP bipolar transistor, the P emitter layer 3 is formed on the other surface and the P emitter (IGBT collector layer) and the N type substrate 1 are N
The base and channel forming layer 5 are formed as a collector. The electrodes of the IGBT are composed of a gate electrode 7a for taking out the polycrystalline Si 7, an emitter electrode 6a for short-circuiting the channel forming layer 5 and the N emitter layer 6, and a collector electrode 3a for taking out the P emitter layer 3 (P emitter). The ON operation in this structure is performed by applying a positive voltage to the gate of the NMOS transistor to make the channel conductive, whereby the emitter electrode 6a, the N emitter layer 6, the surface channel inversion layer of the channel forming layer 5, the N-type substrate 1 are formed. , P emitter layer 3, an electron current flows to the collector electrode 3a. This electron current becomes a base current of the PNP bipolar transistor, holes are injected from the P emitter layer 3 into the N-type substrate 1, and flow through the channel forming layer 5 to the emitter electrode 6a as a hole current. In the off operation, 0 V is applied to the gate to cut off the electron current. Electrons that remain transiently after applying 0 V to the gate are extracted to the collector electrode 3a. On the other hand, holes continue to be injected from the P emitter layer 3 and become excess carriers until the electron current stops flowing. The holes are extracted to the emitter electrode 6a through the channel forming layer 5. In general, the mobility of holes is about 1/3 of that of electrons, so I
The disappearance of the hole current is dominant in the tf of GBT. The electron beam irradiation accelerates the disappearance of the hole current by shortening the lifetime of holes that become surplus carriers when turned off.

In another conventional example, a MOS transistor for short-circuiting the P emitter and the N base is provided in the IGBT device disclosed in Japanese Patent Laid-Open No. 1-57674, and an electron current at the time of turning off is not passed through the P emitter layer. By pulling out, the excess injection of holes is eliminated and the turn-off speed is improved, but the manufacturing process is complicated and it is difficult to apply to an integrated circuit including a plurality of IGBTs.

[0004]

In order to reduce the switching loss of the above-mentioned prior art, the lifetime of holes injected from the P emitter layer 3 is controlled by electron beam irradiation, and IG
This is achieved by shortening the fall time (tf) when BT is off. On the other hand, the current capability per unit area of the IGBT is improved as the number of holes injected from the collector layer increases, and there is a trade-off relationship between the reduction of tf by electron beam irradiation and the improvement of current capability. That is, tf
It is necessary to improve the current capacity of the IGBT by the reduction of the above, which causes an increase in the cell area of the IBGT. Further, since the lifetime is shortened, there is a problem that it is difficult to use a bipolar element in a device that constitutes an IC. Further, in the method in which the MOS for short-circuiting the P emitter and the N base is built in the cell of the IGBT, the manufacturing process is complicated, and an external circuit is required to control the short-circuited MOS, and it is difficult to apply to an IC including a plurality of IGBTs. .

An object of the present invention is to include an IGBT which is included in an IC by an ordinary IC technology without irradiating an electron beam.
Another object of the present invention is to provide a semiconductor device that reduces the tf of.

[0006]

The above-mentioned object is to achieve lateral I.
In the GBT, a circuit for extracting the potential of the second conductivity type semiconductor layer including the collector layer made of the first conductivity type semiconductor as an electrode (control collector electrode) and short-circuiting the collector electrode and the control collector electrode when the lateral IGBT is turned off. Is added in the IC containing the IGBT.

[0007]

Since the collector electrode and the control collector electrode are short-circuited when the IGBT is off, the carriers flowing to the MOS pass through the collector layer made of the first conductivity type semiconductor and the second conductivity type semiconductor layer (control collector layer). Control collector electrode,
It operates so as to flow to the collector electrode through the short circuit.
As a result, when the IGBT is off, excess carriers are not injected from the first conductivity type semiconductor layer into the second conductivity type semiconductor layer, so that tf can be shortened.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. Figure 1 shows the cross-sectional structure of a lateral IGBT. FIG.
The structure is similar to the structure shown in FIG. 4 and is different in that a high-concentration control collector layer 4 is provided on the N-type substrate 1, and a terminal is provided in ohmic contact with the extraction electrode 4b. FIG. 2 shows an upper arm element, which is a source switch, and a lower arm element, which is a sink switch, having a totem pole structure with a lateral IGBT, and these elements for driving the upper and lower IGBTs are integrated in one chip. Lower arm IGB
T is driven by an inverter composed of a PMOS 203 and an NMOS 204 which are powered by VCC by logically controlling the input terminal 210 with respect to the ground potential. On the other hand, control of the upper arm IGBT is performed between the fixed power supply V1 and the drive power supply V2 higher than V1.
Input 217 of inverter composed of PMOS 215 and NMOS 216
By applying an “H” potential with respect to V1 as a reference, the PMOS 214 whose source is V2 is turned on and the upper arm IGBT212 is turned on. The drains of the PMOS 214 and the NMOS 209 are commonly connected, and when the PMOS 214 is on, the NMOS 209 is off by the input signal of 211. In the off operation, the "L" signal is input to the input terminal 217 to turn off the PMOS 214. "H" is applied to the input terminal of 211 in synchronization with this input signal.
By applying a signal, the NMOS209 is turned on and the IGBT is turned off. 21 so that PMOS 214 and NMOS 209 do not turn on at the same time
The timings of the input signals 1 and 2 are adjusted. 2
Reference numeral 08 is a gate protection circuit for the upper arm IGBT. PMOS
214 and NMOS 209 have high breakdown voltage.

In the present invention, for example, in the integrated circuit shown in FIG. 2, a control collector electrode is provided in the IGBT, and a circuit for short-circuiting the collector and the control collector when the IGBT is off is added to the IC. The operation will be described below. In the lower arm IGBT
The source of the PMOS 202 is the collector 3aL (= V of the IGBT)
o) and the drain is connected to the control collector 4bL. The PMOS 202 is controlled by turning on and off the NMOS 205. When the IGBT 201 is on, the NMOS 205 is off. At this time, the PMOS202 has resistors connected to the nodes VGP and VO, and VGP = VO, so that the PMOS202 is in the off state. Therefore, the control N-type substrate 1 becomes floating, and holes are injected into the N-type substrate 1 from the P emitter layer 3. The electron current is drawn to the collector electrode 3a through the control N-type substrate 1 (N base layer) -P emitter layer 3. At turn-off, the "H" signal is applied to the input terminal 210 to turn on the PMOS 202. Therefore, collector 3aL
(P emitter layer) and control collector 4bL (N type substrate 1)
Is shorted by PMOS 202. The electrons in the N base layer flow through the node 4bL-PMOS202. The electron current bypasses the P emitter layer 3 and the N-type substrate 1-control collector layer 4
Since there is no excess injection of holes from the P emitter layer 3, the IGBT is turned off at high speed.

Similarly, the upper arm IGBT is also provided with a short circuit between the collector electrode terminal 3aU and the control collector electrode terminal when it is off. FIG. 2 shows an example in which the NMOS 213 is arranged for short circuit. VG of NMOS213 when IBGT212 is on
The potential of N is equal to the potential of V1. Source potential 4bU is IGBT
When 212 is turned on, the junction between the P emitter layer 3 and the N type substrate 1 in FIG. 1 is in the forward bias state, and the collector 3aU
The value is lower than (= V1) by the diffusion potential (0.7v). Therefore, the gate voltage of the NMOS 213 is VGNS = (V1
-0.7). When the IGBT is off, the control collector layer potential needs to be open. Therefore, the threshold voltage Vth> VGNS of the NMOS 213 is required, but the threshold voltage Vth> VGNS can be easily formed by a normal integrated circuit process. At the time of turn-off, the input terminal 217 is set to V1 potential so that the NMOS21
The V2 potential is applied to the gate VGN of 3. The gate voltage VGNS of the NMOS 213 is VGNS = (V2- (V1-0.
7))> Vth is adjusted by the integrated circuit process. Therefore, the NMOS 213 is turned on and the collector layer 3
The turn-off can be speeded up by short-circuiting a and the control N-type substrate 1 and forming a bypass path for the electron current like the lower arm.

FIG. 3 shows another embodiment. As in FIG. 2, a lateral IGBT is connected to a totem pole,
The elements for driving the upper and lower IGBTs are integrated on one chip. The difference from FIG. 2 is that the upper arm IGBT
The power source of the inverter composed of the PMOS 222 and the NMOS 223 for driving the is connected to the floating power source V3 whose reference is VO. Since the driving power source for the upper arm IGBT is floating, it is not possible to use NMOS for short-circuiting as shown in FIG. IG of collector electrode 3aU and control collector electrode 4bU
For short-circuiting when the BT is off, the PMOS 227 is arranged as in the lower arm. For driving the PMOS 227, the input terminal 221 is controlled to control the NMOS2.
Do this by operating 26. By controlling the input terminal 220 in synchronization with this input signal, the collector electrode 3aU and the control collector electrode 4bU can be short-circuited when the IGBT is off, and tf can be speeded up. The short-circuit MOS of the upper arm IGBT in the embodiment of FIG. 2 is PMO as in the embodiment of FIG.
It can be S.

FIG. 4 shows another embodiment. The lower arm structure of FIGS. 2 and 3 is taken out, and the difference from FIGS. 2 and 3 is that
The point is that an input terminal 219 for controlling the MOS that short-circuits the collector of the IGBT and the control collector and an input terminal 218 for driving the IGBT are individually provided. According to this embodiment, P
A short circuit between the emitter layer and the N base layer can be set arbitrarily. t
In order to speed up f, the input signal for driving the IGBT and the signal for controlling the short-circuit MOS are individually controlled, so that after the short-circuit MOS is reliably operated, the IGBT can be off-controlled, so that tf can be speeded up. . The signals for obtaining these timings can be easily created by IC technology. Further, it is also possible to individually take out and control the control signal and the drive signal of the short circuit of the upper arm IGBT shown in FIGS.

It should be noted that the embodiment is an example in which the short circuit is composed of MOS, and the circuit can be composed of bipolar transistors to be integrated into an IC.

[0014]

According to the present invention, it is not necessary to control the lifetime by the electron beam, so that the characteristics of the IGBT are not deteriorated and the IGBT cell can have a simple structure provided with the control collector electrode. The output stage IGB can be easily implemented by using the conventional IC technology without complicating the manufacturing process of
It becomes possible to turn off T at a high speed.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a lateral IGBT that is an embodiment of the present invention.

FIG. 2 is an IC circuit diagram showing an embodiment of the present invention.

FIG. 3 is an IC circuit diagram showing a second embodiment of the present invention.

FIG. 4 is an IC circuit diagram showing a third embodiment of the present invention.

FIG. 5 is a sectional view of a conventional IC lateral IGBT.

[Explanation of symbols]

1 ... N type substrate, 3 ... P emitter layer, 4 ... control collector layer, 5 ... channel forming layer, 6 ... N emitter layer, 202,
213, 227 ... Short circuit MOS, 210, 212 ... Lateral IGBT, 211, 217, 218, 219, 22
0,221 ... Control input terminal.

Front Page Continuation (72) Inventor Hitoshi Oura, 3-10-2 Bentencho, Hitachi, Hitachi, Ibaraki Hitachi Haramachi Electronics Co., Ltd. (72) Inventor, Koji Kawamoto, 3-1-1, Saiwaicho, Hitachi, Ibaraki Stock Hitachi Works Hitachi Factory

Claims (7)

[Claims] 1. A lateral IGBT in which a collector electrode is taken out from a semiconductor surface, wherein a second conductivity type semiconductor layer including a collector region formed of a first conductivity type semiconductor layer is taken out as an electrode. 2. The lateral IGBT according to claim 1,
A semiconductor device in which a plurality of electrodes are housed into one chip, and the electrodes of the second conductivity type semiconductor layer are provided as terminals, respectively. 3. The semiconductor device according to claim 1, further comprising a circuit for taking out the first conductivity type semiconductor layer and the second conductivity type semiconductor layer as electrodes and controlling a short circuit between these electrodes. 4. The circuit according to claim 1, wherein the circuit for short-circuiting the first-conductivity-type semiconductor layer and the second-conductivity-type semiconductor layer is composed of a MOS, and the lateral IGBT and a circuit for driving the lateral IGBT are short-circuit controlled. I integrated circuit on one chip
C. 5. The IC according to claim 4, wherein the circuit for short-circuiting the first conductive type semiconductor layer and the second conductive type semiconductor layer is formed of a bipolar circuit. 6. The drive signal for the lateral IGBT according to claim 4, wherein a signal for controlling the short circuit between the semiconductor layer for the first conductivity type and the semiconductor layer for the second conductivity type is branched from a drive signal for the lateral IGBT. IC that operates in synchronization with off. 7. The signal according to claim 4 or 5, wherein a signal for controlling a short circuit between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer and a drive signal for the lateral IGBT are individually controlled.
An IC capable of arbitrarily setting a short circuit between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer.