JPH08167127A - Head testing device - Google Patents

Abstract

PURPOSE: To improve selective precision and to shorten a work time by automatically. left/right symmetric property of an isolated waveform regenerated by an MR head. CONSTITUTION: The time from the detection of the slice level of the isolated waveform by a slice circuit 22 to the detection of peak timing by a peak detection circuit 24 is obtained with a first counter 34 by counting a clock. Further, the time from the detection of the peak timing by the peak detection circuit 24 to the detection end of the slice level by the slice circuit 22 is obtained with a second counter 36 by counting the clock. Then, the left/right symmetric property is decided from a ratio between respective count values of the first, second counters 34, 36.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an MR head tester used in a magnetic disk drive, and more particularly to a head tester used for head evaluation by measuring the left-right symmetry of an isolated waveform reproduced by the MR head. Regarding

[0002]

2. Description of the Related Art In recent years, in magnetic disk devices, the recording density has been improved, the transfer speed has been increased, and the spindle rotational speed has been increased, so that it does not depend on the rotational speed (peripheral speed) of the disk medium. M that can obtain high output level playback signal
The R head (Magnet-Resistive Head) is beginning to be used.

In the manufacturing process of a disk device using such an MR head, the MR head incorporated in the head assembly is tested by a head tester to determine whether or not the expected reproduction performance can be obtained. Is going. In the head test for this selection, there is an operation of checking the left-right symmetry of the isolated waveform reproduced by the MR head and removing the MR head in which the left-right symmetry is broken.

[0004]

However, the left-right symmetry with respect to the conventional MR head is the same as that of the oscilloscope.
The reproduction signal of the R head is input and an isolated waveform is displayed, and the person visually checks whether or not there is left-right symmetry, and makes a selection, which may cause an artificial variation in the selection accuracy. There was a problem that the sorting work took too long.

The present invention has been made in view of the above conventional problems, and automatically detects the left-right symmetry of the isolated waveform reproduced by the MR head to improve the sorting accuracy and reduce the working time. It is an object of the present invention to provide a head test device designed to be shortened.

[0006]

To achieve this object, the present invention is constructed as follows. The present invention relates to a head test apparatus for measuring the left-right symmetry of an isolated waveform signal reproduced by an MR head, and a slice circuit for slicing the isolated waveform signal at a predetermined level, and a peak detection circuit for detecting the peak timing of the isolated waveform, A first counter that obtains the time from the detection of the slice level by the slice circuit to the detection of the peak timing by the peak detection circuit by counting the clock, and from the detection of the peak timing by the peak detection circuit to the end of the detection of the slice level by the slice circuit. A second counter for obtaining time by counting clocks is provided, and the MR head is evaluated from the left-right symmetry of the isolated waveform signal by comparing the count values of the first and second counters.

Further, according to another aspect of the present invention, a slice circuit for slicing an isolated waveform signal at a predetermined level, a peak detection circuit for detecting a peak timing of the isolated waveform, and a peak from a slice level detected by the slice circuit. A first integrator circuit that performs a constant slope integration operation until the detection of the peak timing by the detection circuit, and the constant slope over the time from the detection of the peak timing by the peak detection circuit to the end of the slice level detection by the slice circuit. The second integration circuit for performing the integration operation of 1) is provided, and the MR head is evaluated from the left-right symmetry of the isolated waveform signal by comparing the integrated values of the first and second integration circuits.

Further, a judgment display section is provided to calculate the ratio of the count values of the first and second counters or the ratio of the integral values of the first and second integrator circuits, and the ratio is centered at a predetermined value. When it is within the range, for example, 0.8 to 1.2, it is determined that there is symmetry, and when it is out of this range, it is determined that there is no symmetry, and this determination result is displayed.

[0009]

According to the head test apparatus of the present invention as described above,
Slice an isolated waveform at a predetermined level, find the time to reach the peak after reaching the slice level and the time to return to the slice level after reaching the peak, and compare the two to determine the symmetry and display the result. Therefore, the left-right symmetry of the MR head is automatically determined, the variation in the selection accuracy of the MR head can be reduced, the time required for the selection can be shortened, and the work efficiency of the head selection can be improved. You can

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the overall structure of a head test apparatus according to the present invention. In FIG. 1, the head test apparatus of the present invention comprises a head test section 10, a measurement section 18, and a judgment display section 20. A spindle motor 12 is provided in the head test unit 10, a magnetic disk 15 is mounted on the rotation shaft of the spindle motor 12, and a pattern required for reproducing an isolated waveform is recorded on the upper surface of the magnetic disk 15 and A servo pattern is recorded on the surface of.

The head actuator 14 is provided with a servo head 17 for the servo surface below the magnetic disk 15. An MR head 16 to be tested is provided on the data surface of the both sides of the magnetic disk 15 on which the reproduced pattern of the isolated waveform is recorded. The MR head 16 is manufactured as a head assembly and is attachable to and detachable from the head arm.

The measuring section 18 inputs a reproduction signal from the magnetic disk 15 by the MR head 16 provided in the head testing section 10 and detects information necessary for determining the left-right symmetry of the isolated waveform of the reproduction signal. The determination display unit 20 determines whether or not the coefficient indicating the left-right symmetry of the isolated waveform is within a predetermined range based on the measurement result of the measurement unit 18, and if it is within the predetermined range, displays a pass determination as symmetric. If it is out of the predetermined range, the display result of NG determination is displayed as a defective product.

FIG. 2 is a circuit block diagram showing a first embodiment of the measuring section 18 of FIG. In FIG. 2, the measurement circuit unit 18 includes a slice circuit 22 and a peak detection circuit 24. An isolated waveform signal E1 reproduced by the MR head 16 shown in FIG. 3A is input to the slice circuit 22 and the peak detection circuit 24. A predetermined slice level is set in the slice circuit 22, and while the input isolated waveform signal E1 exceeds the slice level, FIG.
The slice level detection signal E2 shown in is output.

The peak detection circuit 24 detects the timing of the peak value of the isolated waveform signal E1 of FIG.
The peak detection signal E3 of (C) is output. The first counter circuit 34 obtains the time T1 from when the isolated waveform signal E1 of FIG. 3A exceeds the slice level to when it reaches the peak by counting the clock CLK of FIG. 3D. The second counter 36 similarly obtains the time T2 from the peak value of the isolated signal waveform E1 of FIG. 3A to the return to the slice level by counting the clock CLK. The first counter 34 and the second counter 36 are AND circuits 26, 32, F based on the outputs of the slice circuit 22 and the peak detection circuit 24.
It is controlled by a logic circuit including F28 and an inverter 30.

First, the AND circuit 26 includes a slice circuit 22.
The slice level detection signal E2 from the FF28 is input, and the peak detection signal E3 from the peak detection circuit 24 is input to the FF28.
And input through the inverter 30. Further, the clock CLK is input. In the state before exceeding the slice level in the isolated signal waveform E1 of FIG. 3A, the slice level detection signal E2 is at the L level and the peak detection signal E3 is also at the L level as shown in FIGS. It is in.

In this state, when the isolated waveform signal E1 exceeds the slice level and the slice level detection signal E2 rises to the H level, the AND circuit 26 enters the permissible state and supplies the clock CLK to the first counter 34. Therefore, the counting operation must be started. Therefore, at this time, the input to the AND circuit 26 from the peak detection circuit 24 must be at the H level.

Initially, the peak detection signal E3 is at the L level and the FF 28 is also in the reset state, so that its Q output is at the L level. Therefore, the input level of the AND circuit 26 in the initial state is set to the H level by the inversion by the inverter 30. Slice level detection signal E
2 becomes H level and the AND circuit 26 outputs the clock CL
After K is supplied to the first counter 34 and the counting operation is started, when the peak detection signal E3 becomes H level by peak detection from the peak detection circuit 24, the FF 28 is set to Q = H level and the inverter 30 causes By inversion, the AND circuit 26 is disabled at this time, the supply of the clock CLK is stopped, and the counting operation of the first counter 34 is stopped.

As a result, the first counter 34 is shown in FIG.
The number of CLKs over T1 from when the isolated waveform signal E1 of (1) exceeds the slice level to when it reaches the peak is counted. The count value of the first counter 34 at this time is N1. The AND circuit 32 outputs the output of the slice circuit 22, F
The output of F28 and the clock CLK are input.
Before the isolated waveform signal E1 of FIG. 3A exceeds the slice level, the output of the FF 28 and the slice circuit 2
The outputs of 2 are both at the L level, and the AND circuit 32 is in the prohibited state.

Even if the isolated waveform signal E1 exceeds the slice level and the slice level detection signal E2 becomes H level,
Since the peak detection signal E3 of the peak detection circuit 24 is still at L level and the FF 28 is in the reset state, the AND circuit 32 is still in the disabled state when Q = L level. When the isolated waveform signal E1 reaches the peak, the peak detection signal E3 rises to the H level, the FF 28 is set, and the Q = H level is set.
The circuit 32 enters the permissible state and starts the counting operation by supplying the clock CLK to the second counter 36. After that, when the isolated waveform signal E1 falls below the slice level,
The slice level detection signal E2 returns to the L level, at which time the AND circuit 32 is disabled and the second counter 3
The counting of the clock CLK by 6 stops.

Therefore, the second counter 36 is shown in FIG.
The clock CLK is counted over the time T2 from the peak of the isolated signal waveform E1 in (A) to the return to the slice level. The count value obtained by counting the second counter 36 over the time T2 is set to N2. The slice circuit 22 and the peak detection circuit 24 output the slice level detection signal E2 and the peak detection signal E3 in synchronization with the clock CLK. Further, the FF 28 and the first counter 34
Each of the second counter 36 and the reset signal E
6, the reset is received at the start of measurement and after the end of measurement.

By the measuring unit 18 having the configuration of FIG. 2 as described above, the count value N1 of the first counter 34 and the count value N2 of the second counter 36 are given to the judgment display unit 20 of FIG. This is a value proportional to time T1 and T2 in FIG. In the determination display unit 20, the ratio of the count values N1 and N2 is calculated as K = N1 / N2 = T1 / T2 as the coefficient K indicating the symmetry of the isolated waveform. In the case of FIG. 3A, T1 <T2 is changed to N1 <N2, so that the coefficient K indicating the left-right symmetry is obtained as K = 0.7. Here, the judgment display unit 2
In the case of 0, the range of the coefficient K that determines the usable symmetry is predetermined to be 0.8 to 1.2, for example.

In the isolated waveform of FIG. 3A, K = 0.
Since it is 7, the judgment result is out of this range, and therefore there is no symmetry, and the MR head 16 under test displays NG for removing it as a defective product. Of course, if the value of the coefficient K is within the range of 0.8 to 1.2, the pass / fail judgment result is displayed. FIG. 4 shows a second embodiment of the measuring unit 18 of FIG. 1, and in the second embodiment, the first product circuit 42 and the second integrating circuit 44 are used to provide the structure shown in FIG.
The time T1 and T2 until the peak of the isolated signal waveform E1 reproduced by the MR head 16 with respect to the slice level is measured.

In FIG. 4, the slice circuit 22, the peak detection circuit 24, the FF 28, and the inverter 30 are the same as those in the embodiment of FIG. 2, and the AND circuits 38 and 40 are provided next, but the counting of the clock is trusted. Therefore, the AND circuit is a 2-input AND circuit, and the output of the slice circuit 22 and the output of the inverter 30 are input to the AND circuit 38.
The output of the slice circuit 22 and the output of the FF 28 are input to the ND circuit 40. The AND circuit 38 rises to the H level when the slice level is exceeded with respect to the isolated waveform signal E1 of FIG. 5A and rises to the H level when the slice level is exceeded, and falls to the L level when the peak is detected, as shown in FIG. To occur. Further, as shown in FIG. 5F, the AND circuit 40 outputs the gate signal E8 which rises to the H level when the isolated signal waveform E1 reaches the peak and falls to the L level when the isolated signal waveform E1 returns to the slice level.

The first integrating circuits 42 and 44 have an integrating function of charging the capacitor with a constant current, and the integration time is controlled by the gate signals E7 and E8. Therefore, the integration circuit 4
2, the integration operation is performed over the H level period of the gate signal E7 from the AND circuit 38, and the integration voltage V1 is output, as shown in FIG. In addition, the second integration circuit 44
As shown in FIG. 5 (H), performs an integration operation over the H level period of the gate signal E8 of the AND circuit 40, and outputs an integration voltage V2.

Here, the integration times of the first integration circuit 42 and the second integration circuit 44 are times T1 and T2 showing the left-right symmetry with respect to the peak of FIG. 5 (A), and the slope of the voltage rise during integration is Since both are constant, integrated voltages V1 and V2 that are proportional to the times T1 and T2 can be generated.
The integrated voltages V1 and V2 of the first integration circuit 42 and the second integration circuit 44 are converted into digital data by the AD converters 46 and 48, and are taken into the determination display unit 20 of FIG. When the embodiment of FIG. 4 is used in the measurement unit 18, the determination display unit 20 calculates K = V2 / V1 = T1 / T2 as the coefficient K indicating the symmetry of the isolated waveform. Since the isolated signal waveform E1 in FIG. 5A is the same as that in FIG.
Calculated a coefficient K = 0.7, and is out of the range 0.8 to 1.2 that determines symmetry.
Since the R head 16 has lost its symmetry and cannot be used, NG is displayed as the determination result.

In addition, in the above embodiment, FIG.
As described above, when the slice level of the isolated signal waveform is exceeded, the left and right time widths T1 and T2 around the peak value are obtained by clock counting or integration operation, and the presence or absence of symmetry is determined from the ratio of the two. , The isolated signal waveform E1 is A
It goes without saying that all the measurements and judgments may be performed by sampling with the D converter, loading them into the MPU, and performing program processing in the MPU.
Further, the present invention is not limited by the numerical values shown in the embodiments.

[0027]

As described above, according to the present invention, the presence or absence of symmetry can be evaluated by automatically measuring the symmetry of the reproduced isolated waveform in the test of the MR head. Since it is possible to reduce the variation in accuracy when performing the process and to shorten the time required for selection, it is possible to improve the efficiency of head selection work.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of the overall configuration of the present invention.

FIG. 2 is a circuit block diagram showing a first embodiment of the measuring section in FIG.

3 is a timing chart of FIG.

FIG. 4 is a circuit block diagram showing a second embodiment of the measuring section in FIG.

5 is a timing chart of FIG.

[Explanation of symbols]

 10: Head test unit 12: Spindle motor 14: Head actuator 15: Magnetic disk 16: MR head 17: Servo head 18: Measuring unit 20: Judgment display unit 22: Slice circuit 24: Peak detection circuit 26, 32, 38, 40 : AND circuit 28: FF 30: Inverter 34: First counter 36: Second counter 42: First integration circuit 44: Second integration circuit 46, 48: AD converter

Claims (3)

[Claims] 1. A head tester for measuring the left-right symmetry of an isolated waveform signal reproduced by an MR head, wherein a slice circuit for slicing the isolated waveform signal at a predetermined level and a peak timing of the isolated waveform are detected. A peak detection circuit; a first counter for obtaining a time from detection of a slice level by the slice circuit to detection of peak timing by the peak detection circuit by counting clocks; and detection of peak timing by the peak detection circuit to the slice circuit A second counter that obtains the time until the detection of the slice level by
A head testing apparatus comprising: a MR head that evaluates an MR head from the left-right symmetry of the isolated waveform signal by comparing the count values of the first and second counters. 2. A head tester for measuring the left-right symmetry of an isolated waveform signal reproduced by an MR head, wherein a slice circuit for slicing the isolated waveform signal at a predetermined level and a peak timing of the isolated waveform are detected. A peak detection circuit; a first integration circuit that performs a constant slope integration operation over the time from detection of the slice level by the slice circuit to detection of peak timing by the peak detection circuit; detection of peak timing by the peak detection circuit To the end of the detection of the slice level by the slice circuit, the second integrator circuit performing the integration operation of the constant gradient, and comparing the integrated values of the first and second integrator circuits with each other A head test apparatus characterized in that the MR head is evaluated from the left-right symmetry of a waveform signal. 3. The head test apparatus according to claim 1, wherein the ratio of the count values of the first and second counters or the ratio of the integral values of the first and second integrating circuits is calculated, When the ratio is within a predetermined range centered on 1, it is determined that there is symmetry, and when the ratio is out of the range, it is determined that there is no symmetry, and a determination display unit that displays the determination result is provided. Head test equipment.