JPH0816544A - Single chip microcomputer - Google Patents

Abstract

PURPOSE:To provide a single chip microcomputer where a system is started when an oscillator oscillating in a high frequency or a low frequency is mounted exteriorly. CONSTITUTION:In a right and left shift register 10, initial values '1', '0' and '1' are initilized. A main clock (or a time clock) is imparted to the right and left shift register 10 via an AND gate 21 (or 22) and the register 10 is stopped by shifting the register to the right (or to the left) by 1-bit. An AND gate 23 makes an AND gate 15 (or 13) conductive, lets the main clock (or the time clock) pass and imparts the clock to a CPU 1 and peripheral modules 2 and 3 via an OR gate 16. As for the priority shifting the register 10, the main clock of a high frequency is larger than the time clock of a low frequency.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a single chip microcomputer which selects and uses a system clock from a plurality of clocks having different frequencies.

[0002]

2. Description of the Related Art A single-chip microcomputer used in, for example, a portable device has a high-speed clock and a low-speed clock, and the high-speed clock is used as a main clock when an instruction is decoded and executed. Used as a clock clock supplied to a clock timer.

CP of single-chip microcomputer
A clock for operating the U or its peripheral modules is called a system clock, and the single-chip microcomputer can select and use one of a main clock and a clock clock as the system clock. This uses the main clock when high-speed operation is required, and high-speed operation is not required,
This is because the clock clock is used when it is desired to operate the entire system at low speed. The power consumption of the single-chip microcomputer is large when operating with the main clock and small when operating with the clock clock.

FIG. 11 is a block diagram of a conventional single-chip microcomputer. In the figure, 71 is a NAND gate, one input end of which is connected to the terminal 61, the other input end thereof is connected to the terminal 62, and the output end thereof is connected to the terminal 63 and the input end of the AND gate 13. The NAND gate 71 has an optimal drive capability for the frequency of the main clock.When a high-speed operation oscillator is externally connected to both terminals 62 and 63, the main clock oscillates and outputs the main clock. If it is not connected or the terminal 61 is grounded, the main clock does not oscillate.

One input end of the NAND gate 72 is connected to the terminal 64, the other input end is connected to the terminal 65, and the output end is the terminal.
66, connected to the input terminal of the AND gate 15 and the clock timer 4. When the clock clock is given, the clock timer 4 keeps time. The NAND gate 72 has a drive capability that is optimal for the frequency of the clock clock.
When an oscillator for low-speed operation is externally connected to, the clock clock is oscillated and output. When it is not externally connected or the terminal 64 is grounded, the clock clock is not oscillated.

FIG. 12 is a circuit diagram of an oscillator to be connected to the single chip microcomputer shown in FIG. A feedback resistor 83 and a crystal oscillator 84 are connected in parallel between both terminals 81 and 82, an input capacitance 85 is connected between the terminal 81 and ground, and an output capacitance 86 is connected between the terminal 82 and ground.

When the frequency of the crystal unit 84 is high, this oscillator can be connected by connecting the terminal 81 (or 82) of this oscillator to the terminal 62 (or 63) of the single-chip microcomputer shown in FIG. It constitutes the main clock oscillator. When the frequency of the crystal unit 84 is low, connect the terminal 81 (or 82) of the oscillator to the terminal 65 (or 66) of the single-chip microcomputer shown in Fig. 11 to make the oscillator oscillate the clock clock. Make up the department. Returning to FIG. 11, description will be made.

When a device including a single-chip microcomputer is powered on, a system reset signal RST generated by a power supply section (not shown) is applied to an OR gate 73 via a terminal 67. When the CPU 1 needs a high speed operation while executing a program, a negative pulse set signal is generated and given to the OR gate 73. The OR gate 73 outputs the logical sum of the system reset signal RST and the set signal and supplies it to the S terminal of the RS flip-flop 74. The RS flip-flop 74 is set by the rise of this logical sum, the terminal Q outputs “H”, and it is given to the AND gate 13 to make it conductive.
It is given to 15 to make it non-conductive.

Therefore, the main clock oscillated by the NAND gate 71 is given to the CPU 1, peripheral modules 2 and 3 as a system clock via the AND gate 13 and the OR gate 16, and the CPU 1 and the like operate at high speed. When the CPU 1 requires a low speed operation during execution of the program, a negative pulse reset signal is generated and given to the R terminal of the RS flip-flop 74. The RS flip-flop 74 is reset by the rise of this reset signal, the terminal Q outputs "L" to make the AND gate 13 non-conductive and the AND gate 15 conductive. Therefore, the clock clock oscillated by the NAND gate 72 is given to the CPU 1, peripheral modules 2 and 3 as a system clock via the AND gate 15 and the OR gate 16, and the CP clock
U 1 etc. operate at low speed.

That is, the OR gates 73 and 16, the RS flip-flop 74, the AND gates 13 and 15, and the inverter 14 are the selectors 5.
The selector 5 selects either the main clock or the clock clock as the system clock according to the set signal, the reset signal and the system reset signal bar RST.

[0011]

Since the conventional single-chip microcomputer is constructed as described above, even if the single-chip microcomputer is used only when operating at a low speed, the two single-frequency microcomputers oscillate a high frequency and a low frequency. It is necessary to attach an external oscillator, first start up the system at high speed to start the program, and then switch to low speed operation by the program.External oscillator that oscillates at high frequency to start up the system There was a problem that I had to do it.

The present invention has been made in order to solve such a problem, and provides a single-chip microcomputer in which a system starts up when an oscillator for oscillating at high frequency or low frequency is externally attached. With the goal.

[0013]

A single-chip microcomputer according to a first aspect of the present invention is a single-chip microcomputer in which a system clock is selected from two types of clocks having different frequencies and used by a CPU. A shift register that shifts to one side with one clock and shifts to the other side with another clock is provided, and the system clock is selected according to the contents of the shift register.

A single-chip microcomputer according to a second aspect of the present invention is characterized by including means for removing noise included in the system clock. The single-chip microcomputer according to the third aspect of the invention is designed to generate an interrupt request signal and supply it to the CPU when the system clock is switched from one clock to another clock.

A single-chip microcomputer according to a fourth aspect of the present invention includes a gate that receives the system reset signal and the one clock supplied when the power is turned on, and a gate that receives the system reset signal and the other clock. The present invention is characterized in that the system clock is selected after the system reset signal disappears.

[0016]

In the first aspect of the present invention, the register value of the shift register is set to the initial value when the power is turned on, and is shifted to one side by the given high frequency high speed clock and stopped, and the register value in that case is the high speed clock. A main clock is selected, a low-speed clock having a given low frequency is shifted to the other and stopped, and a clock clock whose register value is the low-speed clock is selected. When both clocks are given, the shift by the high speed clock has priority over the shift by the low speed clock. Therefore, when only a crystal oscillator with a small frequency is externally attached, the register value of the shift register shifts to the other and stops, the register value in that case selects the clock clock, and the CPU starts at the low speed clock.

In the second invention, noise contained in the system clock is removed. In the third invention, when the main clock, which is a high-speed clock, stops, the register value of the shift register shifts to the other at the low-speed clock and stops, and the register value in that case selects the low-speed clock, and the system clock is the low-speed clock. It switches to the clock clock. At that point, an interrupt signal is generated and given to the CPU.

In the fourth aspect of the present invention, the system clock is not selected during the period when the system reset signal is supplied when the power is turned on, and the system reset signal is stopped after the power supply voltage is stabilized and the system clock is selected.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings showing the embodiments. FIG. 1 is a block diagram of a single-chip microcomputer according to the present invention. In the figure, 71 is a NAND gate, one input end of which is connected to the terminal 61, the other input end thereof is connected to the terminal 62, and the output end thereof is connected to the terminal 63 and the input end of the AND gate 13. The NAND gate 71 has an optimal drive capability for the frequency of the main clock.When a high-speed operation oscillator is externally connected to both terminals 62 and 63, the main clock oscillates and outputs the main clock. If it is not connected or the terminal 61 is grounded, the main clock does not oscillate.

One input end of the NAND gate 72 is connected to the terminal 64, the other input end is connected to the terminal 65, and the output end is the terminal.
66, connected to the input terminal of the AND gate 15 and the clock timer 4. When the clock clock is given, the clock timer 4 keeps time. The NAND gate 72 has the optimum drive capability for the clock clock frequency, and when an oscillator for low speed operation is externally connected to both terminals 65 and 66, it oscillates and outputs the clock clock and outputs it externally. If not connected with
Alternatively, when the terminal 64 is grounded, the watch clock does not oscillate.

The selector 5 selects either one from the main clock given from the NAND gate 71 and the clock clock given from the NAND gate 72, and gives it to the CPU 1 and the peripheral modules 2 and 3. Left and right shift register of selector 5
Reference numeral 10 is a left / right shift register which is composed of 3 bits and shifts to the left and right. An initial value is set to the 1st bit, 2nd bit and 3rd bit counting from the left end by a circuit not shown, and the output of the 1st bit Q ₁ is applied to the AND gate 22, the output Q ₂ of the second bit is applied to the AND gate 23,
The output Q ₃ of the third bit is the AND gate 21 and the AND gate 23.
Given to.

The initial value is stored in advance in a memory (not shown) and is transferred from the memory to the left / right shift register 10 when the power is turned on. AND gate 21 is a left / right shift register
When "1" is given from the third bit of 10, the gate is opened, the given main clock is passed, and the right shift signal R is given to the left and right shift register 10 to shift each bit to the right.

When "1" is given from the first bit of the left / right shift register 10, the AND gate 22 opens the gate to allow the given clock clock to pass, and gives it to the left / right shift register 10 as a left shift signal L for each bit. Shift to the left.

FIG. 2 is a left-right shift register 10 shown in FIG.
It is a circuit diagram of. In the figure, 30 is a transmission gate, which is a P-channel MOS transistor and an N-channel.
The MOS transistors are connected in parallel, the left shift signal L is given to the gate of the N-channel MOS transistor, and the signal bar L in which the polarity of the left shift signal L is inverted is given to the gate of the P-channel MOS transistor. There is.

When the signal L is "1" and the signal bar L is "0", both transistors are simultaneously turned on, the transmission gate 30 becomes conductive, and the power source V _DD is applied to the point I through the transmission gate 30. To be Signal L
Is "0" and the signal bar L is "1", both transistors are turned off at the same time, and the transmission gate 30 cuts off the power supply V _DD .

Transmission gate 31,34,37,40,4
3,46,49,50,51,52,53,54,55,56 have the same structure as the transmission gate 30, and the signals of opposite polarities are given to the gates of both transistors, which is the same as the transmission gate 30. To work. Between the transmission gate 31 connected to the power source V _DD and the point M, a point A, an inverter 32,33, a point B, a transmission gate 34, a point C, an inverter 35,36, a point D, a transmission gate 37, a point E, Inverters 38, 39, point F, transmission gate 40, point G, inverters 41, 42, point H, transmission gate 43, point I, inverters 44, 45, point J, transmission gate 46, point K, inverter 4
7,48 are connected in series.

Then, the transmission gates 49, 50,
51,52,53,54,55,56 are both points E and M, both points A and H
, Both points A and B, both points C and D, both points E and F, both points G and H, both points I and J, and both points K and M.

The right shift signal R is applied to the OR gate 26,
Further, it is output as a signal bar R via the inverter 27. The left shift signal L is given to the OR gate 26 and also output as a signal bar L via the inverter 28. The OR gate 26 outputs the logical sum of the two signals R and L as the shift signal S, and also as the signal bar S via the inverter 29.

The signal R (or signal bar R) is applied to the gates of the N-channel transistors (or P-channel transistors) of the transmission gates 31,37,43. Signal L (or signal bar L) is the transmission gate 49,5
0 to the gate of an N-channel transistor (or P-channel transistor). The signal S (or signal bar S) is transmitted to the N-channel transistor (or P-channel transistor) gate of the transmission gate 52, 54, 56 and the transmission gate 51, 34, 53, 40, 55, 46.
Of the P-channel transistor (or N-channel transistor).

The potential at the point D is the potential of the first bit,
The output is Q ₁ , the potential at the point H is the potential of the second bit, the output is Q ₂ , the potential at the point M is the potential of the third bit, and the output is Q ₃ . is there.

Next, the operation will be described. In FIG. 3, 3 bits of the left and right shift register 10 shown in FIG. 2 are “0”,
6 is a time chart showing the operation of the left and right shift registers 10 when the clock clock is input and the main clock is not input, which are initially set to “1” and “0”. 3 (a), 3 (b) and 3 (c) show the right shift signal R, the left shift signal L and the shift signal S, respectively. The signal R is always "0" because the main clock is not input, the signal L repeats "0" and "1" alternately according to the clock clock, and the signal S is "0", "1" according to the signal L. Are repeated alternately. Therefore, the transmission gates 31, 37, 43 are always off.

In the initial state, the potential at the point D is "0", the potential at the point H is "1", and the potential at the point M is "0".
Is. At time t ₁ when the signal L rises, the signal S rises, the transmission gate 30 is turned on, and the power supply V _DD sets the potential at the point J to “1” via the inverters 44 and 45. Both transmission gates 55 and 46 are off. Further, the transmission gate 56 is turned on, and the potential “0” at the point M becomes the inverters 47, 48.
The voltage of the point F is set to "0" through the transmission gate 49 and the inverters 38 and 39 which are turned on and are held at "0".

Both transmission gates 53 and 40 are off. Further, the transmission gate 54 is turned on, the potential “1” at the point H is fed back through the inverters 41 and 42 and holds “1”, and is transmitted via the transmission gate 50 and the inverters 32 and 33 which are turned on. The potential at point B is "1". Both transmission gates
51 and 34 are off. Further, the transmission gate 52 is turned on, and the potential "0" at the point D is fed back through the inverters 35 and 36 and holds "0". Thus, the potentials at the points M, H and D are held by the respective feedback loops, the potentials at the points M and H are transmitted to the points F and B, and the power source potential is transmitted to the point J.

At time t ₂ when the signal L falls, the signal S falls, the transmission gate 30 is turned off, and the power source V _DD is cut off. The transmission gate 55 is turned on, the potential "1" at the point J is fed back through the inverters 44 and 45 and holds "1", and the transmission gate 46 and the inverter turned on.
The potential at the point M is set to "1" via 47 and 48. Both transmission gates 56 and 49 are off.

Further, the transmission gate 53 is turned on, the potential "0" at the point F is fed back through the inverters 38, 39 and holds "0", and the transmission gate 40 and the inverters 41, 41 turned on are turned on. The potential at the point H is set to “0” via 42. Both transmission gates 54 and 50 are off. Further, the transmission gate 51 is turned on, the potential "1" at the point B is fed back through the inverters 32 and 33 to hold "1", and the transmission gate 34 and the inverter 3 which are turned on are turned on.
The potential at the point D is set to "1" through 5,36. Both transmission gates 37 and 52 are off.

In this way, the potentials at the points J, F and B are held by the feedback loops respectively and further transmitted to the points M, H and D. After that, the left and right shift register 10 repeats the same operation as that at the time points t ₁ and t ₂ at the time points t ₃ , t ₄ , t ₅ , t ₆ ... Where the signal L rises and falls. The potentials at points J, M, F, H, B, and D are shown in FIGS. 3 (d), 3 (e), 3 (f), 3 (g), and 3 (h), respectively. ),
It is shown in Fig. 3 (i).

[0037] Thus, the first bit, second bit, the initial value set in the third bit "0", "1", "0" the time t ₂ by the left shift signal L, sequentially at time t ₄ The value after shifting to the left bit and the shifting of the third bit is filled with "1". After time t ₆ , the first,
The second and third bits are all "1".

FIG. 4 shows the operation of the left / right shift register 10 when the 3 bits of the left / right shift register 10 shown in FIG. 2 are initialized to "0", "1", "0" and the main clock and the clock clock are input. 2 is a time chart showing. The cycle of the main clock is 5 times the cycle of the clock clock.

4 (a), 4 (b) and 4 (c) show the right shift signal R, the left shift signal L and the shift signal S, respectively. The initial value of each signal R, L, S is "0". After the signal R repeats its rising and falling five times, the signal L
Stands up. Then, the signal R continues to rise and fall five times, and then the signal L falls. Transmission gate while signal L is falling
30,49,50 are off. In the initial state, the potentials at points D, H, and M are "0", "1", and "0", respectively.

At time t ₁₁ when the signal R rises, the signal S rises, the transmission gate 31 is turned on, and the power source V _DD sets the potential at the point B to "1" via the inverters 32 and 33. Both transmission gates 51,3
4 is off. Also transmission gate 52
Is turned on, and the potential "0" at the point D becomes the inverter 35,3.
It is fed back via 6 and holds "0", and the potential at the point F is set to "0" via the transmission gate 37 and the inverters 38, 39 which are turned on.

Both transmission gates 53 and 40 are off. Further, the transmission gate 54 is turned on, the potential “1” at the point H is fed back through the inverters 41 and 42 and holds “1”, and is turned on via the transmission gate 43 and the inverters 44 and 45 which are turned on. J
The potential of is set to "1". Both transmission gates 5
5,46 are off. Further, the transmission gate 56 is turned on, and the potential "0" at the point M is the inverter.
It is returned via 47 and 48 and holds "0". Thus, the potentials at points D, H and M are held by the respective feedback loops, and the potentials at points D and H are transmitted to points F and J,
The power supply potential is transmitted to point B.

At time t ₁₂ when the signal R falls, the signal S falls, the transmission gate 31 is turned off, and the power source V _DD is cut off. The transmission gate 51 is turned on, the potential "1" at the point B is fed back through the inverters 32 and 33 and holds "1", and the transmission gate 34 and the inverter turned on.
The electric potential at the point D is set to "1" via 35 and 36. Both transmission gates 52 and 37 are off. Further, the transmission gate 53 is turned on, the potential “0” at the point F is fed back through the inverters 38 and 39 and holds “0”, and the transmission gate 40 turned on.
And the potential at the point H is set to "0" via the inverters 41 and 42.

Both transmission gates 54 and 43 are off. Further, the transmission gate 55 is turned on, the potential at the point J is fed back through the inverters 44 and 45 and holds “1”, and the potential at the point M is turned on via the transmission gate 46 and the inverters 47 and 48 which are turned on. The electric potential is "1". The transmission gate 56 is off.

Thus, the potentials at the points B, F, and J are held by the feedback loops, respectively, and further transmitted to the points D, H, and M. After that, at the time points t ₁₃ , t ₁₄ , t ₁₅ , and t ₁₆ when the signal R rises and falls, the left and right shift register 10 repeats the same operation as that at the time points t ₁₁ and t ₁₂ . The potentials at points B, D, F, H, J, and M are shown in FIGS. 4 (d), 4 (e), 4 (f), 4 (g), and 4 (h), respectively. ), Fig. 4
i). The values “0”, “1”, and “0” initialized in the first bit, the second bit, and the third bit in this way are sequentially shifted to the right bit at time t ₁₂ and time t ₁₄ by the right shift signal R. The value after shifting to, and the shifting of the first bit is filled with "1". First at time t ₁₆ after the second, third each bit of all "1".

At time t ₁₇ when the signal L rises, the signal S rises and the three transmission gates 30, 4
Although 9,50 is turned on, the potentials at points B, F, and J are "1", and transmission gates 52, 54, 56 are turned on, but at points D, H, and M. The potential is "1". After that, when the signal R repeatedly rises and falls, the potentials at the points B, D, F, H, J, and M are "1". Thus, after the time point t ₁₇ , all of the first, second and third bits are "1". Since the period of the signal R is shorter than the period of the signal L, the right shift is prioritized.

Returning to FIG. 1, description will be made. Left and right shift register
AND gate given 10 2-bit outputs Q ₂ and Q ₃
The output of the logical product 23 is given to the AND gate 13 and is given to the AND gate 15 via the inverter 14. The clock clock is given to the AND gate 13 and the main clock is given to the AND gate 15. Both AND gates 13 and 15 give the logical product of their two inputs to the OR gate 16. The OR gate 16 outputs the given logical sum of the two inputs as a system clock,
It is given to the CPU (not shown).

Next, the operation when the initial values "1", "0" and "1" are set in the left and right shift register 10 will be described. AN because Q ₂ is “0” and Q ₃ is “1”
The D gate 23 outputs “0”, the AND gate 13 is turned off, the AND gate 15 is turned on, the clock clock is cut off, and the main clock is AND gate 15, OR gate.
It goes through 16 and is selected as the system clock and given to the CPU. Also, because Q ₁ is “1”, AND gate
22 is in the ON state, and since Q ₃ is “1”, the AND gate 21 is in the ON state.

When the main clock and the clock clock are given, the main clock is faster than the clock clock, so that the cycle is short and the left / right shift register 10 shifts to the right. Then, the 3-bit value of the left and right shift register 10 becomes "1", "1", "0", respectively. Therefore, Q ₃
Becomes "0", the AND gate 21 is turned off, the right shift is stopped, the AND gate 23 outputs "0", and the main clock is selected as the system clock as in the case of the initial value.

When the main clock is not supplied but the clock clock is supplied, the left / right shift register 10 shifts to the left, and its 3-bit value is "0", "1", "1".
Becomes Therefore, Q ₁ becomes “0”, the AND gate 22 is turned off, and the left shift is stopped. Both Q ₂ and Q ₃ become “1”, AND gate 23 outputs “1”, and
The gate 13 is turned on, the AND gate 15 is turned off, and the clock clock passes through the AND gate 13 and the OR gate 16 and is selected as the system clock and given to the CPU.

As described above, the clock clock is selected as the system clock only by supplying the clock clock without applying the main clock. Therefore, when high-speed operation is not required, the system can be started up without attaching an external oscillator for high speed.

FIG. 5 is a block diagram showing the single-chip microcomputer shown in FIG. 1 in which a high-speed main clock or a low-speed clock clock is selected as the system clock.
FIG. 7 is a circuit diagram of a selector including a shift register configured by bits. In the figure, 11 is configured as a 5-bit left / right shift register with the same configuration as the 3-bit left / right shift register shown in FIG. 2, and a first bit counted from the left end as an initial value by a circuit not shown,
Second bit third bit, respectively "1" to the fourth bit and the fifth bit, "1", "0", "1", "1" is set, the output to Q ₁ first bit AND gate 22 Given to
3rd bit output Q ₃ , 4th bit output Q ₄ and 5th
The output Q ₅ of the bit is provided to the 3-input AND gate 12 and the output Q ₅ is provided to the AND gate 21.

The main clock is given to the AND gate 21 and the AND gate 15, and the clock clock is given to the AND gate 22 and the AN.
Given to D Gate 13. When the AND gate 21 receives "1" from the fifth bit of the left / right shift register 11, the AND gate 21 opens the gate to allow the main clock to pass, and the right shift signal R
Is given to the left and right shift register 11 to shift each bit to the right. When "1" is given from the first bit of the left and right shift register 11, the AND gate 22 opens the gate to pass the clock clock and gives it to the left and right shift register 11 as the left shift signal L to shift each bit to the left. .

3-bit output Q of the left and right shift register 11
_{The 3-} input AND gate 12 provided with ₃ , Q ₄ and Q ₅ outputs the logical product and supplies it to the AND gate 13 and also the inverter.
It is given to AND gate 15 via 14. Both AND gates 13,15
Applies the logical product of the respective two inputs to the OR gate 16. OR gate 1
6 outputs the logical sum of the given two inputs as a system clock and gives it to a CPU (not shown).

Next, the operation when the initial values “1”, “1”, “0”, “1”, “1” are set in the left and right shift register 11 will be described. Since Q ₃ is “0”, Q ₄ is “1”, and Q ₅ is “1”, the 3-input AND gate 12 outputs “0”, the AND gate 13 is turned off, and the AND gate 15 is turned on. Then, the clock clock is cut off, the main clock passes through AND gate 15 and OR gate 16, is selected as the system clock, and is given to the CPU. Further, since Q ₁ is “1”, the AND gate 22 is on, and because Q ₅ is “1”, the AND gate 21 is on.

When the main clock and the clock clock are given, the main clock is faster than the clock clock, so that the cycle is short and the left / right shift register 11 shifts to the right. At the second shift, the 5-bit values of the left and right shift registers are "1", "1", "1",
It becomes "1" and "0". Therefore, Q ₅ becomes “0”,
AND gate 21 turns off, right shift stops, 3
The input AND gate 12 outputs "0", and the main clock is selected as the system clock as in the case of the initial value.

When the main clock is not supplied and the clock clock is supplied, the left and right shift register 11 shifts to the left, and the values of the 5 bits at the second shift are "0", "1" and "1", respectively. "," 1 "," 1 ". Therefore, Q ₁ becomes “0”, the AND gate 22 is turned off, and the left shift is stopped. Q ₃ , Q ₄ , and Q ₅ are all “1”, and the 3-input AND gate 12 outputs “1”,
The AND gate 13 is turned on, the AND gate 15 is turned off, and the clock clock passes through the AND gate 13 and the OR gate 16 and is selected as the system clock and given to the CPU.

As described above, the clock clock is selected as the system clock only by supplying the clock clock without applying the main clock. Therefore, when high-speed operation is not required, the system can be started up only by mounting the oscillator for the clock without mounting the oscillator for high speed.
In FIG. 1, the left and right shift registers 10 of the selector are shown.
Is composed of 3 bits, and the left and right shift register 11 of the selector is composed of 5 bits in FIG. 5, but it goes without saying that the bit structure of the left and right shift register is not limited to 3 bits or 5 bits. Also, the frequency is different 3
When selecting a system clock from more than one type of clock, by providing a plurality of selectors 5 shown in FIG. 1, it is not necessary to attach an oscillator that operates at high speed when a high-speed clock is not used.

FIG. 6 is a time chart showing the operation when the output of the 3-input AND gate 12 is changed from "H" to "L" by the circuit not shown in FIG. 5 and the system clock is switched from the clock clock to the main clock. .

In the figure, (a) shows the main clock,
(b) shows a clock clock. At time t ₂₀ when the main clock falls, the clock clock rises and 3
Since the output of the input AND gate 12 is “H”, the AND gate
13 is conducting, the rising clock clock passes through the AND gate 13 and the OR gate 16, and the system clock becomes "H".

A 3-input AND gate 12 is provided by a circuit (not shown).
At the time point t ₂₁ (see FIG. 6C) when the output of the AND gate falls, the AND gate 13 becomes non-conductive and the AND gate 15 becomes conductive. Therefore, the system clock output from the OR gate 16 becomes "L". This is shown in FIG. 6 (d). At time t ₂₂ the main clock rises, the main clock is passed through AND gate 15 and OR gate 16, the system clock becomes "H". After that, the main clock is output as the system clock.

Next time t ₂₃ when the main clock falls
, The system clock becomes "L". Thus, in the pulse of the period from time t ₂₀ to time t ₂₃ ,
Period from time t ₂₁ to time t _22, there is a case where recesses are formed. This recess is a short pulse. This short pulse may cause the CPU or peripheral modules of the single-chip microcomputer to malfunction.

FIG. 7 is a circuit diagram of a selector having a function of removing a noise such as a short pulse mixed in the system clock. In the figure, reference numeral 20 denotes a noise canceller, which removes the noise and outputs it when the system clock output from the OR gate 16 contains noise. Since other configurations are the same as those in FIG. 5, the same reference numerals are given to the same portions and the description thereof will be omitted. As described above, by providing the noise canceller, noise mixed in the system clock can be removed, and the range in which the single chip microcomputer can be used is widened.

FIG. 8 shows that when the high-speed main clock is stopped and switched to the clock clock, the main clock is stopped.
It is a circuit diagram of a selector having a function of notifying a CPU.
In the figure, reference numeral 18 is an RS flip-flop, the output Q ₅ of the left and right shift register 11 is given to the S terminal, the output of the OR gate 17 is given to the R terminal, and the output bar Q is given to the NOR gate 19. The NOR gate 19 to which the output Q ₁ of the left and right shift register 11 is given, generates an interrupt request signal IRQ and gives it to the OR gate 17 and a CPU (not shown). A system reset signal RST that resets the single-chip microcomputer at power-on is given to the RS flip-flop 18 via the OR gate 17 and resets the RS flip-flop 18 at power-on. Since other configurations are the same as those in FIG. 5, the same reference numerals are given to the same portions and the description thereof will be omitted.

Next, the operation will be described. When the main clock and the clock clock are given, the outputs Q ₁ ... Q ₅ of the left / right shift register 11 are “1”, “1”,
They are "1", "1", "0", and the 3-input AND gate 12 outputs "L" to make the AND gate 13 nonconductive and the AND gate 15 conductive. The main clock is AND gate 15 and
It passes through the OR gate 16 and is given to the CPU as the system clock. At the time of the output Q ₅ falling "0",
The RS flip-flop 18 is set and the output bar Q is "L". The "1" of the output Q ₁ is given to the NOR gate 19, and the output of the NOR gate is "L".

FIG. 9 is a time chart showing the operation when the main clock is stopped. In the figure (a)
Indicates the main clock, and (b) indicates the clock clock.
At the falling time t ₃₀ , the main clock stops due to any cause, and the system clock which is the output of the OR gate 16 also stops accordingly. This is shown in FIG. 9 (g).

After time t ₃₀ , the clock clock rises and falls. When this is repeated three times t ₃₁
, The outputs Q ₁ ... Q ₅ of the left / right shift register 11 are “1”, “0”, “1”, “1”, “1”, and the 3-input AND gate 12 outputs “H”, and AND The gate 13 is made conductive. This is shown in FIG. 7 (f). After that, the clock clock passes through the AND gate 13 and the OR gate 16 and is given to the CPU as the system clock.

At the next falling time t ₃₂ of the clock clock, the outputs Q ₁ ... Q ₅ of the left and right shift registers 11 are "0", "1", "1", "1", "1", Q ₁ becomes “0”. This is shown in FIG. 9 (c). Therefore, the output of the NOR gate 19 becomes "H". This "H" is OR
The RS flip-flop 18 is reset via the gate 17, and the output bar Q becomes "H". This "H" is given to the NOR gate 19 and its output is set to "L". This is Figure 9
It is shown in (d) and FIG. 9 (e). Therefore, the interrupt request signal IRQ which is the output of the NOR gate 19 is a rising pulse.

In this way, when the main clock is stopped due to a failure or the like, the left and right shift registers are driven by the clock clock.
"0" at the right end of 11 moves to the left end. During the movement process, the clock clock is output as the system clock, and at the end of the movement, the interrupt request signal IRQ is generated to notify the CPU of the system clock switching.

FIG. 10 is a circuit diagram of a selector that operates stably when the power is turned on. First of the left and right shift register 11
Bit output Q ₁ , system reset signal (bar RST)
And clock clock are given to the 3-input AND gate 25,
The input AND gate 25 gives the logical product as a left shift signal L to the left and right shift register 11. The fifth bit of the output Q ₅ of the left and right shift registers, the system reset signal (Bar
RST) and the main clock are given to the 3-input AND gate 24, and the 3-input AND gate 24 gives the logical product to the left / right shift register 11 as the right shift signal R. The system reset signal RST is "L" when the power is turned on, that is, while the power supply voltage is unstable, and becomes "H" when the power supply voltage is stable, and is generated in the power supply unit (not shown). And is given to the selector of the one-chip microcomputer. Since other configurations are the same as those in FIG. 5, the same reference numerals are given to the same portions and the description thereof will be omitted.

Next, the operation will be described. Both inputs 3 inputs while system reset signal (bar RST) is given
The D gates 24 and 25 are closed, and the right shift signal R and the left shift signal L are not input to the left and right shift register 11.
When the power supply potential is stable and the system reset signal bar RST becomes "H", the left / right shift register 11 is set to "1",
Initialized as "1", "0", "1", "1", both signals R, L become valid, and the desired clock is selected as the system clock. That is, when the main clock and the clock clock are given, the main clock is selected as the system clock, and when the main clock is not given and the clock clock is given, the clock clock is selected as the system clock. When the main clock or the clock clock is unstable when the power is turned on, the system clock does not switch and the operation becomes stable.

[0071]

As described above, according to the first aspect of the invention, the shift register determines whether the main clock or the clock clock is given, and when the main clock is given, the main clock is selected, If only clock clock is given, select clock clock. Therefore, when the main clock is not used, the oscillator that operates at high speed does not have to be externally attached, and the system starts up by attaching the oscillator that operates at low speed.

According to the second invention, the noise contained in the system clock is removed, so that the range in which the single chip microcomputer can be used is widened. According to the third aspect of the invention, when the main clock is stopped and automatically switched to the clock clock, an interrupt request signal is generated and the CPU is notified of the clock switching. According to the fourth aspect of the present invention, when the power supply voltage is unstable when the power is turned on, the system clock is not selected, and the system clock is selected after the power supply voltage is stabilized, so that the operation is stable.

[Brief description of drawings]

FIG. 1 is a block diagram of a single-chip microcomputer according to the present invention.

FIG. 2 is a circuit diagram of the left-right shift register shown in FIG.

FIG. 3 is a time chart showing the operation of the left and right shift registers shown in FIG.

FIG. 4 is another time chart showing the operation of the left and right shift registers shown in FIG.

5 is a circuit diagram when the selector shown in FIG. 1 is configured with 5 bits.

FIG. 6 is a flowchart showing the operation of the selector shown in FIG.

FIG. 7 is a circuit diagram in the case where the selector shown in FIG. 5 has a noise removing function.

FIG. 8 is a circuit diagram when an interrupt request signal is generated in the selector shown in FIG.

9 is a time chart showing the operation of the selector shown in FIG.

FIG. 10 is a circuit diagram for allowing the selector shown in FIG. 5 to operate stably when the power is turned on.

FIG. 11 is a block diagram of a conventional single-chip microcomputer.

FIG. 12 is a circuit diagram of an oscillator to be externally attached to a single chip microcomputer.

[Explanation of symbols]

1 CPU, 2, 3 peripheral modules, 4 clock timer, 5 selectors, 10 and 11 left and right shift registers, 20
Noise canceller.

Claims (4)

[Claims] 1. A single-chip microcomputer in which a system clock is selected from two types of clocks having different frequencies and used in a CPU, wherein one of the plurality of clocks shifts to one and the other clocks shifts to the other. A single-chip microcomputer characterized by comprising a shift register for shifting to, and selecting a system clock according to the contents of the shift register. 2. The single-chip microcomputer according to claim 1, further comprising means for removing noise included in the system clock. 3. The single chip microcomputer according to claim 1, wherein when the system clock is switched from one clock to another clock, an interrupt request signal is generated and supplied to the CPU. 4. An AND circuit which receives a system reset signal given at power-on and the one clock, and
4. The single-chip microcomputer according to claim 1, further comprising an AND circuit having the system reset signal and the other clock as inputs, and selecting the system clock after the system reset signal disappears.