JP2001209560A - Single-chip microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To select the overflow signal of the watchdog timer as the system reset signal or interrupt signal of CPU(central processing unit), to give flexibility, and to reduce peripheral devices when a single-chip microcomputer is applied. SOLUTION: This invention is provided with the switch to select the supply point of the overflow signal which the watchdog timer 2 outputs. When users use the overflow signal of the watchdog timer 2 as the system reset signal SR of CPU 6, the change-over contact of switch 3 is fixed to the terminal on the side (a) when manufactured the single-chip microcomputer 1. Concurrently, the change-over contact of switch 5 is fixed to the terminal on the side (b).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a single-chip microcomputer having a watchdog timer, a CPU (Central Processing Unit), and the like.

[0002]

2. Description of the Related Art Conventionally, the following is known as this kind of single-chip microcomputer.

(1) Since the watchdog timer is not preset even after a certain period of time has elapsed due to runaway of the CPU, when an overflow signal is output, a circuit in a single-chip microcomputer is used based on the signal to generate hardware. System reset, for example, the CPU or the entire single-chip microcomputer is reset.

(2) When the watchdog timer outputs an overflow signal, a non-maskable interrupt is hardly interrupted to the CPU by a circuit in the single-chip microcomputer based on the overflow signal, and the CPU has an abnormality in the system. To the outside,
The processing at the time of abnormality is performed by software.

[0005]

By the way, the following two applications are conceivable for applications in which a single-chip microcomputer is used.

(A) A case where some processing such as initialization is required not only for a single-chip microcomputer but also for peripheral devices at the time of CPU runaway.

(B) When only a single-chip microcomputer needs to be initialized when the CPU goes out of control.

For this reason, when it is desired to perform the process (A) by the above (1), a flexible process up to initialization, for example, after resetting a peripheral device,
Reset of the single-chip microcomputer could not be realized.

On the other hand, when the processing of (B) is desired to be performed by the method of (2), a system reset signal is output from an output port to the outside, and thereby a single chip microcontroller is connected via a peripheral device. Extra circuitry (devices) because the computer needs to be reset
Is required.

By the way, in the above (2), the CP
Depending on the situation at the time of abnormality, such as when the system clock of U is stopped, the processing by software may not be performed reliably after the occurrence of the non-maskable interrupt by the watchdog timer. For example, the CPU freezes and the output signal of the output terminal in the single-chip microcomputer is not cleared, or the output data of the display circuit (LDC driver) included in the single-chip microcomputer is not cleared. A situation occurred, and in such a case, it was sometimes difficult for the system to determine the abnormality of the single-chip microcomputer. For example, the display on the LCD panel may remain as it is even if the CPU runs away or stops.

In view of the above, a first object of the present invention is to provide an overflow signal of a watchdog timer with a C signal.
Allows the user to select as a PU system reset signal or interrupt signal, giving flexibility when applying a single-chip microcomputer to an application, and, depending on the application, reducing unnecessary peripheral devices. An object of the present invention is to provide a single-chip microcomputer.

In view of the above, a second object of the present invention is to provide a peripheral circuit in a single-chip microcomputer even when an overflow signal of a watchdog timer is generated and abnormal processing cannot be performed by software. SUMMARY OF THE INVENTION It is an object of the present invention to provide a single-chip microcomputer capable of reliably performing necessary processing when an abnormality occurs.

[0013]

In order to solve the above problems and to achieve the first object of the present invention, claims 1 to 3 are provided.
Each invention described in (1) was configured as follows.

According to a first aspect of the present invention, in a single-chip microcomputer having at least a watchdog timer and a CPU, a selection of selecting an overflow signal of the watchdog timer as a system reset signal or an interrupt signal of the CPU. Means are provided.

According to a second aspect of the present invention, in a single chip microcomputer having at least a watchdog timer and a CPU, a first switch for arbitrarily selecting an output destination of an overflow signal of the watchdog timer, An OR gate which receives the overflow signal selected by the first switch and a system reset signal from the outside and uses the output thereof as a system reset signal of the CPU; and an overflow signal selected by the first switch. A non-maskable interrupt signal from the outside is selected, and the selected signal is transmitted to the CPU.
And a second switch for a non-maskable interrupt signal.

According to a third aspect of the present invention, in the single-chip microcomputer according to the second aspect, the respective contacts of the first switch and the second switch remain fixed after the selection. Alternatively, it is characterized in that it is selected when the power is turned on and is fixed each time the selection is made.

In each of the first to third aspects of the present invention, the overflow signal of the watchdog timer can be selected as a system reset signal or an interrupt signal (non-maskable interrupt signal) of the CPU. Therefore, it is possible to flexibly cope with the application of the single-chip microcomputer by the user, and it is possible to reduce a surplus peripheral device depending on the application.

In order to achieve the second object of the present invention, the invention according to claim 4 is configured as follows.

According to a fourth aspect of the present invention, in the single-chip microcomputer including at least a watchdog timer and a CPU, the overflow signal of the watchdog timer is used as an interrupt signal for the CP.
U and supplied to peripheral circuits in the single-chip microcomputer as a reset signal.

According to the fourth aspect of the present invention, when an overflow signal of the watchdog timer is generated, not only is the CPU interrupted, but also peripheral circuits in the single-chip microcomputer are initialized. Can be For this reason, even when an overflow signal of the watchdog timer is generated and abnormal processing cannot be performed by software, necessary processing can be reliably performed for peripheral circuits in the single-chip microcomputer in the event of an abnormality.

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

First, a first embodiment of a single-chip microcomputer according to the present invention will be described with reference to FIG.

As shown in FIG. 1, the single-chip microcomputer 1 according to the first embodiment has a watchdog timer 2, a changeover switch 3 as a first switch, an OR gate 4, and a changeover switch as a second switch. 5, a CPU (Central Processing Unit) 6, etc., which are integrated into one chip.

The watchdog timer 2 operates based on an instruction from the CPU 6, and outputs an overflow signal assuming that an abnormality has occurred in the CPU 6 or the like when the preset is not performed even after a predetermined time has elapsed. The changeover switch 3 is a switch that arbitrarily selects a supply destination of the overflow signal output from the watchdog timer 2 by switching a changeover contact.

The OR gate 4 receives an external system reset signal SR at one input terminal,
Its input terminal is grounded via a resistor R1. The other input terminal of the OR gate 4 is grounded via the switch 7 and the resistor R2, and switches the overflow signal from the watchdog timer 2 to the switch 3.
Is to be entered via Further, the output of the OR gate 4 is supplied to the CPU 6 as a system reset signal.

The changeover switch 5 is provided with a non-maskable interrupt signal NMI from the outside by switching the changeover contact.
And a switch for selecting an overflow signal output from the watchdog timer 2, and the selected signal is input to the CPU 6 as a non-maskable interrupt signal NMI. For this reason, the changeover switch 5 has its a-side terminal connected to the b-side terminal of the changeover switch 3, its b-side terminal grounded via the resistor R3, and the non-maskable interrupt signal NMI from the outside. Is to be entered.

The CPU 6 receives a system reset signal SR and a non-maskable interrupt signal NMI.
When the PU 6 and the like are reset and the non-maskable interrupt signal NMI is input, predetermined processing is performed.

Next, a method of using the single-chip microcomputer having the above-described structure according to the first embodiment will be described with reference to FIGS.

First, the user sets the watch dog timer 2
Is used as the system reset signal SR of the CPU 6 when the single chip microcomputer is manufactured, the switching contact of the changeover switch 3 is fixed to the terminal on the a side as shown in FIG. And changeover contact of the changeover switch 5 to b
To the terminal on the side. R2 is OR gate 4
The switch 7 may be provided as shown in FIG. 1, and in this case, it may be opened.

In the case of using a single-chip microcomputer in which the changeover contacts of the changeover switches 3, 5, and 7 are set (fixed), when an overflow signal is output from the watchdog timer 2, the overflow signal is output. Is supplied as a system reset signal SR to the CPU 6 via the changeover switch 3 and the OR gate 4. Therefore, the overflow signal causes the CPU
6 or the entire single-chip microcomputer 1 is reset by hardware. Further, when a non-maskable interrupt signal NMI from the outside is supplied to the CPU 6 via the changeover switch 5, the CPU 6 performs a process corresponding thereto.

On the other hand, when the user uses the overflow signal of the watchdog timer 2 as the non-maskable interrupt signal NMI of the CPU 6, the process shown in FIG. Then, the changeover contact of the changeover switch 3 is fixed to the terminal on the side b, and the changeover switch 5
Is fixed to the terminal on the a side. further,
The switch 7 is fixed to the closed side, and the input terminal of the OR gate 4 is fixed to the ground level by the pull-down resistor R2.

When using a single-chip microcomputer in which the changeover contacts of the changeover switches 3, 5, and 7 are set, when the overflow signal is output from the watchdog timer 2, the overflow signal is changed to the changeover switch. The non-maskable interrupt signal NMI is supplied to the CPU 6 via 3 and 5. Therefore, when the overflow signal is supplied, the CPU 6 performs an abnormality process according to the overflow signal. When an external system reset signal SR is supplied to the CPU 6 via the OR gate 4, the CPU 6 or the entire single-chip microcomputer 1 is reset by hardware.

As described above, according to the single-chip microcomputer according to the first embodiment,
The watchdog timer 2 overflow signal is sent to the CPU
6 can be arbitrarily selected as the system reset signal SR or the non-maskable interrupt signal NMI.
For this reason, the user can flexibly cope with the application of the single-chip microcomputer, and can reduce excess peripheral devices depending on the application.

In the above example, the changeover switch 3,
The positions of the switching contacts 5 and 7 are set (fixed) at the time of manufacture as required by the user.
By using a writable nonvolatile memory, for example, an EPROM or the like, the selected switch setting is written in the application assembling process, or the position is set by software each time the user turns on the power. May be used.

Next, a second embodiment of the single-chip microcomputer of the present invention will be described with reference to FIG.

As shown in FIG. 3, the single-chip microcomputer 11 according to the second embodiment has an OR gate 12, a watchdog timer 13, an interrupt control circuit 14, a CPU (central processing unit) 15, and an OR gate 1.
6 and the like, a display circuit 17 as a peripheral circuit (peripheral device) and the like are provided, and these are integrated into one chip.

The OR gate 12 receives the watchdog timer / reset signal WDRST and the sleep signal SLEEP output from the CPU 15, and receives the watchdog timer / reset signal W based on these inputs.
DRST is output to the watchdog timer 13.

The watchdog timer 13 outputs a watchdog timer reset signal WDRS from the OR gate 12.
Each time T is output, the counter is reset. After the reset, counting of the clock CLK is started, and when there is no reset within a predetermined time, an overflow signal is output. It is being supplied. A watchdog timer enable signal WDEN is input to the watchdog timer 13, and the watchdog timer 13 operates when this signal is at “H” level.

The interrupt control circuit 14 receives an interrupt signal in addition to the overflow signal from the watch timer 13 and outputs an interrupt signal to the CPU 15 and the OR gate 16 in accordance with the priority.

When the CPU 15 receives the non-maskable interrupt signal NMI from the interrupt control signal 14, the CPU 15 performs an abnormal process according to the signal. When the interrupt signal from the interrupt control signal 14 or the reset signal RST is input, the OR gate 16 receives the interrupt signal or the reset signal RST, thereby the data register 171-1 of the display circuit 17 which is a part of the peripheral circuit built in the single-chip microcomputer 1.
1 to 171-n are reset.

The display circuit 17 includes data registers 171-1 to 171- which store display data of an LCD (not shown).
n and an LCD driver 17 connected to the output side of the data registers 171-1 to 171-n to drive the LCD.
2-1 to 172-n.

Next, the operation of the second embodiment having such a configuration will be described with reference to FIG.

Now, when the watchdog timer 13 outputs an overflow signal, the overflow signal passes through the interrupt control circuit 14 and is input to the CPU 15 as a non-maskable interrupt signal NMI and the data register 171-1 of the display circuit 17 171-n are supplied as a reset signal via the OR gate 16.

For this reason, the CPU 15 can perform a predetermined abnormal process in accordance with the non-maskable interrupt signal NMI, and can also execute the data register 171-1 to 17-17 of the display circuit 17.
1-n are forcibly reset based on the overflow signal.

Therefore, according to the second embodiment, even after the non-maskable interrupt signal NMI is generated, even if abnormal processing by the CPU 15 is not performed for some reason and initialization of peripheral circuits cannot be performed, the single-chip microcontroller can be used. Necessary resetting of the display circuit 17, which is a peripheral circuit in the computer 11, can be reliably performed, and as a result, the display on the LCD can be turned off.

In the second embodiment, the case where the display circuit 17 is a peripheral circuit in the single-chip microcomputer 11 has been described.
Instead, for example, a sound source circuit for driving a buzzer or the like of a peripheral device, a driving circuit for a motor, or the like may be used, and a data register included in such a peripheral circuit may be reset or set.

[0047]

As described above, in each of the first to third aspects of the present invention, the overflow signal of the watchdog timer can be selected as a system reset signal or an interrupt signal of the CPU. In addition to being able to flexibly cope with the application of a single-chip microcomputer according to the application, it is possible to reduce excess peripheral devices depending on the application.

In the invention according to claim 4, when an overflow signal of the watchdog timer is generated,
In addition to interrupt processing to the CPU, peripheral circuits in the single-chip microcomputer can be initialized, so that after a watchdog timer overflow signal occurs, abnormal processing by software cannot be performed for any reason. Even in such a case, the necessary processing can be reliably performed for the peripheral circuits in the single-chip microcomputer in the event of an abnormality.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a single-chip microcomputer according to a first embodiment of the present invention, in which an overflow signal of a watchdog timer is used as a system clock.

FIG. 2 is a block diagram showing the configuration of the first embodiment, in which an overflow signal of a watchdog timer is used as a non-maskable interrupt signal.

FIG. 3 is a block diagram showing a configuration of a second embodiment of the single-chip microcomputer of the present invention.

[Explanation of symbols]

 1, 11 Single-chip microcomputer 2, 13 Watchdog timer 3 Changeover switch (first switch) 4, OR gate 5 Changeover switch (secondary switch) 6, 15 CPU 7 Switch 12, 16 OR gate 14 Interrupt control circuit 17 Display Circuit (peripheral circuit) 171-1 to 171-n Data register 172-1 to 172-n LCD driver R1 to R3 Pulldown resistor

Claims (4)

[Claims] 1. A single-chip microcomputer comprising at least a watchdog timer and a CPU, comprising: a selection means for selecting an overflow signal of the watchdog timer as a system reset signal or an interrupt signal of the CPU. Features a single-chip microcomputer. 2. A single-chip microcomputer having at least a watchdog timer and a CPU, a first switch for arbitrarily selecting an output destination of an overflow signal of the watchdog timer, and a first switch selected by the first switch. An OR gate for receiving the overflow signal and an external system reset signal and using the output as a system reset signal of the CPU; an overflow signal selected by the first switch and an external non-maskable interrupt signal; And a second switch for making the selected signal, and using the selected signal as a non-maskable interrupt signal for the CPU. 3. The contacts of the first switch and the second switch remain fixed after selection.
3. The single-chip microcomputer according to claim 2, wherein the single-chip microcomputer is selected at power-on and is fixed each time the selection is made. 4. A single-chip microcomputer including at least a watchdog timer and a CPU, wherein an overflow signal of the watchdog timer is supplied to the CPU as an interrupt signal, and a reset signal in the single-chip microcomputer is provided. A single-chip microcomputer adapted to supply peripheral circuits.