JPH08162664A - Semiconductor photodetector - Google Patents

Semiconductor photodetector

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Publication number
JPH08162664A
JPH08162664A JP6321178A JP32117894A JPH08162664A JP H08162664 A JPH08162664 A JP H08162664A JP 6321178 A JP6321178 A JP 6321178A JP 32117894 A JP32117894 A JP 32117894A JP H08162664 A JPH08162664 A JP H08162664A
Authority
JP
Japan
Prior art keywords
layer
type
barrier layer
well layer
well
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6321178A
Other languages
Japanese (ja)
Inventor
Shigeo Sugao
繁男 菅生
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP6321178A priority Critical patent/JPH08162664A/en
Publication of JPH08162664A publication Critical patent/JPH08162664A/en
Pending legal-status Critical Current

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  • Light Receiving Elements (AREA)

Abstract

PURPOSE: To improve high speed response characteristics of an APD by reducing a valence band discontinuity and decreasing the trap of holes in a superlattice multiplying layer. CONSTITUTION: An n-type InP buffer layer 2, an n<-> type superlattice avalanche multiplying layer 3 [In0.52 Al0.48 As (barrier layer)/InAs0.30 P0.70 (well layer)], a p--type wide gap field drop layer 4, a p<-> type Inlays light absorbing layer 5, and a p<+> type InP cap layer 6 are grown on an n<+> type InP substrate 1, an insulating protective film 7 is formed, and then a p-type side electrode 8 and an n-type side electrode 9 are formed. The type II superlattice avalanche multiplying layer lattice-matched to the substrate becomes In0.52 Al0.48 As (barrier layer)/InP (well layer). However, in this example, the part of the P of the well layer lattice-matched to the substrate is replaced with As to realize the multiplying layer in which valence band discontinuity is small.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体受光素子に関
し、特に光通信システム等において用いられるアバラン
シェ増倍型の半導体受光素子に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor photodetector, and more particularly to an avalanche multiplication type semiconductor photodetector used in optical communication systems.

【0002】[0002]

【従来の技術】高速・大容量の光通信システムを構成す
るには、高速、かつ、低雑音・高感度特性を有する受光
素子が不可欠である。このような受光素子としてpin
型受光素子(エレクトロニクス・レターズ誌、1984
年,20巻,653−654頁に記載)、及び、アバラ
ンシェ増倍型受光素子(以下、APDと記す)(アイイ
ーイーイー・エレクトロンデバイス・レターズ誌、19
86年、7巻、257−258頁に記載)が知られてい
る。特に、後者は内部利得効果を利用することができま
た高速応答性に優れているため高い利得帯域幅積(GB
積)を得ることができ、例えばInP/InGaAs系
のAPDでは75GHzのGB積が実現されている。
2. Description of the Related Art In order to construct a high-speed, large-capacity optical communication system, a high-speed, low-noise, high-sensitivity photodetector is indispensable. As such a light receiving element, a pin
Type light receiving element (Electronics Letters magazine, 1984
, Vol. 20, p. 653-654), and avalanche multiplication photodetector (hereinafter referred to as APD) (IEEE Electronic Device Letters, 19
1986, Volume 7, pp. 257-258) is known. In particular, the latter can utilize the internal gain effect and is excellent in high-speed response, so that the high gain bandwidth product (GB
The product) can be obtained, and for example, a GB product of 75 GHz is realized in the InP / InGaAs APD.

【0003】しかしながら、ここでは増倍層であるIn
Pのイオン化率比が約2と小さいため低雑音化のために
は高感度化には限界がある。さらに特性を向上させるに
は人工的にイオン化率比を増大させる必要があった。
However, In, which is a multiplication layer here,
Since the ionization rate ratio of P is as small as about 2, there is a limit to high sensitivity for low noise. To further improve the characteristics, it was necessary to artificially increase the ionization ratio.

【0004】そこで、カパッソ(F.Capasso)
らは伝導帯に人工的にバンド不連続をもうけた増倍層を
用いて電子のイオン化促進に利用し、AlGaAs/G
aAs系で特性の向上を実証した。さらに、香川らは、
アプライド・フィジクス・レター誌、1989年、55
(10)巻、993−959頁にてInGaAs/In
AlAs系超格子を用いて光通信用波長帯に感度を有す
るAPDにおいてイオン化率比の増大を確認した。
Therefore, F. Capasso
Et al. Used AlGaAs / G to accelerate electron ionization by using a multiplication layer with artificial band discontinuity in the conduction band.
It has been demonstrated that the aAs system improves the characteristics. Furthermore, Kagawa et al.
Applied Physics Letter Magazine, 1989, 55.
(10), pp. 993-959, InGaAs / In
It was confirmed that the ionization rate ratio was increased in the APD having sensitivity in the wavelength band for optical communication using the AlAs superlattice.

【0005】しかしながら、この構造の受光素子は、超
格子アバランシェ増倍層内に多数のバンド不連続が存在
し、特に価電子帯のバンド不連続は増倍キャリアのうち
エネルギー障壁にトラップされ易い正孔をトラップし2
−3GHz以上の周波数応答を劣化させるという問題を
生じる。
However, in the light-receiving element having this structure, a large number of band discontinuities exist in the superlattice avalanche multiplication layer, and especially the band discontinuity in the valence band is easily trapped by the energy barrier of the multiplied carriers. Trap the hole 2
A problem occurs that the frequency response of -3 GHz or higher is deteriorated.

【0006】この点に対処するものとして、特開平4−
61174号公報、特開平4−355976号公報にて
提案された素子構造がある。前者は、増倍層の井戸層の
一部を半導体歪み層で構成するものである。この半導体
歪み層では、価電子帯のバンドの縮退が解消されて軽い
正孔と重い正孔の2つのバンドが生じ、このうち軽い正
孔のバンドは障壁層の価電子帯端に近づく。これにより
正孔のヘテロ障壁へのトラップは抑制される。また、後
者のAPDでは、増倍層の井戸層に引っ張り応力が負荷
される。これにより、井戸層中の正孔の質量はバルクの
時より軽くなり、パイルアップ現象は緩和される。
As a measure against this point, Japanese Unexamined Patent Publication No.
There are element structures proposed in Japanese Patent No. 61174 and Japanese Patent Application Laid-Open No. 4-3595796. In the former, a part of the well layer of the multiplication layer is composed of a semiconductor strained layer. In this semiconductor strained layer, degeneracy of the band of the valence band is resolved to generate two bands, a light hole and a heavy hole, of which the light hole band approaches the valence band edge of the barrier layer. This suppresses the trapping of holes into the hetero barrier. Further, in the latter APD, tensile stress is applied to the well layer of the multiplication layer. As a result, the mass of holes in the well layer becomes lighter than that in the case of bulk, and the pile-up phenomenon is alleviated.

【0007】[0007]

【発明が解決しようとする課題】従来の典型的なAPD
では、超格子アバランシェ増倍層内に多数存在する価電
子帯のバンド不連続に正孔がトラップされるため、高周
波特性が劣化するという問題点があった。この問題を解
決すべく提案された上記公報による素子構造はいずれも
井戸層内に歪みを導入することによって正孔のトラップ
を抑制しようとするものであるため次のような欠点があ
る。
DISCLOSURE OF THE INVENTION Conventional typical APD
However, since holes are trapped in band discontinuities in the valence band that are present in a large number in the superlattice avalanche multiplication layer, there is a problem that high frequency characteristics are deteriorated. The device structures according to the above publications proposed to solve this problem all attempt to suppress the trapping of holes by introducing strain into the well layer, and therefore have the following drawbacks.

【0008】井戸層内に導入された歪みは価電子帯のバ
ンドの縮退を解消させ軽い正孔のバンドと重い正孔のバ
ンドの2つのバンドを生じさせる。歪みが圧縮性であれ
ば軽い正孔のバンドが障壁層の価電子帯端に近づき、引
っ張り性であれば重い正孔のバンドが近づく。しかし、
バンド不連続が解消された訳ではないので正孔は依然と
してトラップされる。しかも、歪みが圧縮性であれば重
い正孔のバンドが、また、引っ張り性であれば軽い正孔
のバンドが障壁層の価電子帯端から遠ざかり、逆に障壁
が高くなるため、このような解決手段では十分な高周波
特性の改善効果を期待することはできない。
The strain introduced in the well layer eliminates the degeneracy of the band of the valence band and produces two bands, a band of light holes and a band of heavy holes. If the strain is compressible, the band of light holes approaches the edge of the valence band of the barrier layer, and if the strain is tensile, the band of heavy holes approaches. But,
Holes are still trapped because the band discontinuity has not been resolved. Moreover, if the strain is compressible, the band of heavy holes is pulled, and if the strain is tensile, the band of light holes is moved away from the valence band edge of the barrier layer. It is not possible to expect a sufficient effect of improving the high-frequency characteristics with the solution.

【0009】本発明は、従来技術の上記問題点に鑑みて
なされたものであって、その目的は、超格子構造アバラ
ンシェ増倍層のV族元素の組成を変えて障壁層と井戸層
の禁制帯幅の差を主に伝導帯のバンド不連続に反映さ
せ、価電子帯のバンド不連続量を極力小さくすることに
より、イオン化率比を高め、低雑音、高増倍、高速応答
が同時に成立するAPDを提供することにある。
The present invention has been made in view of the above problems of the prior art, and its object is to inhibit the barrier layer and the well layer by changing the composition of the V group element of the superlattice structure avalanche multiplication layer. The difference in band width is mainly reflected in the band discontinuity in the conduction band, and the band discontinuity in the valence band is minimized to improve the ionization ratio and simultaneously achieve low noise, high multiplication, and high-speed response. To provide APD to do.

【0010】[0010]

【課題を解決するための手段】上記目的を達成するた
め、本発明によれば、半導体基板上にIII −V族半導体
からなる超格子構造アバランシェ増倍層と光吸収層とを
備えるものであって、前記超格子構造アバランシェ増倍
層を構成する障壁層と井戸層が前記半導体基板と格子整
合する組成においてはタイプII超格子となるエネルギー
バンド構造をとる半導体であり、かつ、前記障壁層およ
び/または前記井戸層を構成するV族元素の組成を変え
て価電子帯不連続量を小さくしたことを特徴とする半導
体受光素子、が提供される。
To achieve the above object, according to the present invention, a superlattice structure avalanche multiplication layer made of a III-V group semiconductor and a light absorption layer are provided on a semiconductor substrate. A barrier layer and a well layer constituting the superlattice structure avalanche multiplication layer is a semiconductor having an energy band structure of a type II superlattice in a composition lattice-matched with the semiconductor substrate, and the barrier layer and And / or a semiconductor light receiving element characterized in that the composition of the group V element constituting the well layer is changed to reduce the amount of valence band discontinuity.

【0011】また、本発明によれば、上記した半導体受
光素子において、V族元素の組成を変えたことにより前
記障壁層または前記井戸層の格子定数と前記半導体基板
の格子定数との間に差が生じたとき、この差と逆方向の
差が前記井戸層または前記障壁層の格子定数と前記半導
体基板の格子定数との間に生じるように前記井戸層また
は前記障壁層を構成するIII 族元素の組成を変え、前記
障壁層または前記井戸層に生じた歪みを補償する量の歪
みを前記井戸層または前記障壁層に導入した半導体受光
素子、が提供される。
Further, according to the present invention, in the above-described semiconductor light receiving element, the composition of the group V element is changed so that the difference between the lattice constant of the barrier layer or the well layer and the lattice constant of the semiconductor substrate is different. When this occurs, a difference in the direction opposite to this difference occurs between the lattice constant of the well layer or the barrier layer and the lattice constant of the semiconductor substrate, and the group III element forming the well layer or the barrier layer. There is provided a semiconductor light receiving device, wherein the composition is changed to introduce an amount of strain into the well layer or the barrier layer to compensate the strain generated in the barrier layer or the well layer.

【0012】[0012]

【作用】図1(a)、(b)は、本発明による半導体受
光素子のバンド構造を説明するための図であって、超格
子構造アバランシェ増倍層を構成する障壁層と井戸層の
一周期分のバンド構造が模式的に示されている。図1
(a)は、半導体基板と格子整合する組成においてタイ
プII超格子となるエネルギーバンド構造をとる半導体を
障壁層と井戸層に用いた場合のバンド構造図である。ま
た、図1(b)は、井戸層を構成するV族元素の組成を
変えて価電子帯不連続量を小さくした場合のバンド構造
図であり、本発明の第1の実施例のバンド構造に相当す
る。さらに、図1(c)は、典型的従来例の超格子構造
(タイプI超格子構造)アバランシェ増倍層の障壁層と
井戸層のバンド構造図である。
1 (a) and 1 (b) are views for explaining the band structure of a semiconductor light receiving element according to the present invention, which shows one of a barrier layer and a well layer constituting a superlattice avalanche multiplication layer. A band structure for a period is schematically shown. FIG.
(A) is a band structure diagram when a semiconductor having an energy band structure that becomes a type II superlattice in a composition lattice-matched with a semiconductor substrate is used for a barrier layer and a well layer. FIG. 1B is a band structure diagram in the case where the composition of the group V element forming the well layer is changed to reduce the valence band discontinuity, and the band structure of the first embodiment of the present invention. Equivalent to. Further, FIG. 1C is a band structure diagram of a barrier layer and a well layer of a typical conventional superlattice structure (type I superlattice structure) avalanche multiplication layer.

【0013】図1(c)に示す従来構造では、障壁層と
井戸層の価電子帯端の不連続量が波長1〜1.6μmに
感度を有する材料系であるIn0.52Al0.48As/In
0.53Ga0.47Asを用いた場合0.2eVあり、このエ
ネルギー障壁が多数存在する超格子中をアバランシェ増
倍により生成した正孔が走行するときにこの障壁にトラ
ップされて応答速度が3GHz程度以下に劣化する。
In the conventional structure shown in FIG. 1C, In 0.52 Al 0.48 As / In is a material system in which the discontinuity amount of the valence band edge of the barrier layer and the well layer is sensitive to a wavelength of 1 to 1.6 μm.
When 0.53 Ga 0.47 As is used, it is 0.2 eV, and when holes generated by avalanche multiplication travel in a superlattice with many energy barriers, they are trapped by this barrier and the response speed becomes about 3 GHz or less. to degrade.

【0014】一方、基板に格子整合した組成でタイプII
超格子となるエネルギーバンド構造をとる半導体を障壁
層と井戸層に用いた場合、図1(a)に示す伝導帯不連
続と価電子帯不連続を生じる。本発明に従って、ここ
で、例えば、井戸層においてV族元素の組成を変化させ
る。一般に、III −V族化合物半導体では、価電子帯端
エネルギーの値は主にV族原子によって決まっている。
そのため、V族元素の組成を変化させることにより価電
子帯端エネルギーの値を調整できる。
On the other hand, a type II composition with a lattice-matched substrate
When a semiconductor having an energy band structure that becomes a superlattice is used for the barrier layer and the well layer, the conduction band discontinuity and the valence band discontinuity shown in FIG. According to the invention, here, for example, the composition of the group V element is changed in the well layer. Generally, in a III-V group compound semiconductor, the value of the valence band edge energy is mainly determined by the V group atom.
Therefore, the value of the valence band edge energy can be adjusted by changing the composition of the V group element.

【0015】具体的には、格子整合時の井戸層のV族元
素組成の一部をより質量数の大きい元素により置き換え
る。例えば、InAlAsとInPからなるタイプII超
格子を増倍層に用いた場合、図1(a)のバンド構造と
なり、価電子帯不連続量は0.3eVとなる。ここで、
井戸層のInPに対してV族元素のPの一部をPより質
量数の大きいAsに置き換える。図1(b)は、30%
のPをAsに置き換えた場合のバンド図であり、価電子
帯不連続は0.1eV以内となる。この場合、伝導帯不
連続はAsの添加による禁制帯幅の減少を反映して拡大
し0.5eVとなる。このように、価電子帯不連続を極
めて小さくすることができ、かつ、伝導帯不連続を大き
くすることができるため、バンド不連続によりトラップ
される正孔を少なくして高速応答性を改善することがで
きるとともに、イオン化率比を向上させることができ
る。
Specifically, part of the group V element composition of the well layer at the time of lattice matching is replaced with an element having a larger mass number. For example, when a type II superlattice composed of InAlAs and InP is used for the multiplication layer, the band structure shown in FIG. 1A is obtained, and the valence band discontinuity is 0.3 eV. here,
For InP in the well layer, a part of P of the V group element is replaced with As having a larger mass number than P. Figure 1 (b) shows 30%
7 is a band diagram in which P is replaced with As, and the valence band discontinuity is within 0.1 eV. In this case, the conduction band discontinuity expands to 0.5 eV, reflecting the decrease in the forbidden band width due to the addition of As. Thus, the valence band discontinuity can be made extremely small and the conduction band discontinuity can be made large, so that holes trapped by the band discontinuity are reduced and the high speed response is improved. It is possible to improve the ionization ratio.

【0016】逆に、基板に格子整合したタイプII超格子
バンド構造の増倍層を構成した後、障壁層側のV族元素
の組成を変えて(この場合はV族元素の一部をより質量
数の小さい元素に置き換える)、価電子帯不連続量を小
さくすることもでき、この場合にも、上記の場合と同様
にイオン化率の向上と高速応答性の改善を同時に実現す
ることができる。
On the contrary, after forming the multiplication layer of the type II superlattice band structure lattice-matched to the substrate, the composition of the group V element on the barrier layer side is changed (in this case, part of the group V element is It is also possible to reduce the discontinuity of the valence band by replacing the element with a smaller mass number), and in this case as well, it is possible to improve the ionization rate and the high-speed response at the same time as in the above case. .

【0017】ところで、基板に格子整合した井戸層(障
壁層)のV族元素の一部をより質量数の大きい(小さ
い)元素に置き換えた場合には格子定数が基板よりも大
きく(小さく)なるため、井戸層(障壁層)は圧縮歪み
(引っ張り歪み)を受け、増倍層全体でも圧縮歪み(引
っ張り歪み)を受ける。
When part of the group V element of the well layer (barrier layer) lattice-matched with the substrate is replaced with an element having a larger (smaller) mass number, the lattice constant becomes larger (smaller) than that of the substrate. Therefore, the well layer (barrier layer) receives compressive strain (tensile strain), and the entire multiplication layer also receives compressive strain (tensile strain).

【0018】本発明においては、この歪みを緩和するた
めに、障壁層(井戸層)を構成するIII 族の元素の組成
を調整して障壁層(井戸層)の格子定数を基板のそれよ
りも小さく(大きく)なるようにして井戸層(障壁層)
において生じた歪み補償する歪みを故意に障壁層(井戸
層)に導入する。具体的には、基板と格子整合していた
障壁層(井戸層)のIII 族元素組成の一部をより質量数
の小さい(大きい)元素と置き換える。このことによ
り、増倍層全体の歪みは緩和され増倍層の結晶上の品質
を向上させることができる。
In the present invention, in order to relax this strain, the composition of the group III element constituting the barrier layer (well layer) is adjusted so that the lattice constant of the barrier layer (well layer) is smaller than that of the substrate. Well layer (barrier layer) so that it becomes smaller (larger)
The strain for compensating for the strain generated in 1) is intentionally introduced into the barrier layer (well layer). Specifically, part of the group III element composition of the barrier layer (well layer) that was lattice-matched with the substrate is replaced with an element having a smaller (larger) mass number. As a result, the strain of the entire multiplication layer is relaxed, and the crystalline quality of the multiplication layer can be improved.

【0019】[0019]

【実施例】次に、本発明の実施例について図面を参照し
て説明する。 [第1の実施例]図2は、本発明の第1の実施例のアバ
ランシェ増倍型半導体受光素子の断面図である。この受
光素子は以下のように作製される。すなわち、ガスソー
スMBE装置を用いて、n+ 型InP基板1上に、以下
の各層を順次成長させる。 n型InPバッファ層2: 層厚:1μm n- 型超格子アバランシェ増倍層3: 組成:In0.52Al0.48As(障壁層)/InAs0.30
0.70(井戸層) キャリア濃度:2E15cm-3 層厚:0.3μm(各々10nmずつで15周期) p型ワイドギャップ電界降下層4: 組成:InAlAs キャリア濃度:8E17cm-3、 層厚:0.1μm p- 型InGaAs光吸収層5 キャリア濃度:1E15cm-3、 層厚:1.3μm p+ 型InPキャップ層6 キャリア濃度:5E18cm-3、 層厚:0.2μm
Embodiments of the present invention will now be described with reference to the drawings. [First Embodiment] FIG. 2 is a sectional view of an avalanche multiplication type semiconductor light receiving device according to the first embodiment of the present invention. This light receiving element is manufactured as follows. That is, the following layers are sequentially grown on the n + type InP substrate 1 using the gas source MBE device. n-type InP buffer layer 2: Layer thickness: 1 μm n - type superlattice avalanche multiplication layer 3: Composition: In 0.52 Al 0.48 As (barrier layer) / InAs 0.30
P 0.70 (well layer) Carrier concentration: 2E15 cm −3 Layer thickness: 0.3 μm (15 cycles of 10 nm each) p-type wide-gap electric field drop layer 4: Composition: InAlAs Carrier concentration: 8E17 cm −3 , Layer thickness: 0. 1 μm p type InGaAs light absorption layer 5 carrier concentration: 1E15 cm −3 , layer thickness: 1.3 μm p + type InP cap layer 6 carrier concentration: 5E18 cm −3 , layer thickness: 0.2 μm

【0020】次に、通常のフォトリソグラフィ技術とウ
エットエッチングによって直径50μmの円形メサを形
成し、絶縁保護膜7を形成する。最後に、p+ 型InP
キャップ層6とn+ 型InP基板1にそれぞれオーミッ
クに接触するp側電極8とn側電極9を形成する。
Next, a circular mesa having a diameter of 50 μm is formed by a normal photolithography technique and wet etching to form an insulating protective film 7. Finally, p + type InP
A p-side electrode 8 and an n-side electrode 9 which are in ohmic contact with the cap layer 6 and the n + type InP substrate 1 are formed.

【0021】InP基板に格子整合したタイプII超格子
アバランシェ増倍層では、In0.52Al0.48As(障壁
層)/InP(井戸層)となるが、この実施例において
は、井戸層のPの30%をAsに置き換えて、超格子
を、In0.52Al0.48As(障壁層3a)/InAs
0.300.70(井戸層3b)とし、これにより、価電子帯
不連続が小さく、かつ伝導帯不連続の大きい増倍層を実
現している。
In the type II superlattice avalanche multiplication layer lattice-matched to the InP substrate, In 0.52 Al 0.48 As (barrier layer) / InP (well layer) is obtained. % As As, and the superlattice is made of In 0.52 Al 0.48 As (barrier layer 3a) / InAs.
0.30 P 0.70 (well layer 3b), thereby realizing a multiplication layer with small valence band discontinuity and large conduction band discontinuity.

【0022】[第2の実施例]図3は、本発明の第2の
実施例を示す断面図である。同図において、図2に示し
た第1の実施例の部分と同等の部分には同一の参照番号
が付せられているので重複する説明は省略するが、本実
施例においては、n- 型超格子アバランシェ増倍層の構
造が以下のように構成されている。 組成:In0.52Al0.48As0.80.2 (障壁層)/I
nP(井戸層) キャリア濃度:2E15cm-3 層厚:0.3μm(各々10nmずつで15周期)
[Second Embodiment] FIG. 3 is a sectional view showing a second embodiment of the present invention. In the figure, it omitted the duplicated description because it is face down with the same reference numerals portion equivalent to parts of the first embodiment shown in FIG. 2, in this embodiment, n - -type The structure of the superlattice avalanche multiplication layer is configured as follows. Composition: In 0.52 Al 0.48 As 0.8 P 0.2 (barrier layer) / I
nP (well layer) Carrier concentration: 2E15 cm -3 Layer thickness: 0.3 μm (15 cycles of 10 nm each)

【0023】InP基板に格子整合したタイプII超格子
In0.52Al0.48As(障壁層)/InP(井戸層)に
対し、この実施例においては、障壁層のAsの20%を
Pに置き換えて、超格子を、In0.52Al0.48As0.8
0.2 (障壁層3c)/InP(井戸層3d)とし、こ
れにより、価電子帯不連続が小さく、かつ伝導帯不連続
の大きい増倍層を実現している。
In contrast to the type II superlattice In 0.52 Al 0.48 As (barrier layer) / InP (well layer) lattice-matched to the InP substrate, 20% of As in the barrier layer is replaced with P in this embodiment, The superlattice is In 0.52 Al 0.48 As 0.8
Since P 0.2 (barrier layer 3c) / InP (well layer 3d) is used, a multiplication layer having a small valence band discontinuity and a large conduction band discontinuity is realized.

【0024】[第3の実施例]図4は、本発明の第3の
実施例を示す断面図である。本実施例においては、n-
型超格子アバランシェ増倍層3が次のように構成されて
いる。 組成:In0.45Al0.55As(障壁層)/InAs0.30
0.70(井戸層) キャリア濃度:2E15cm-3 層厚:0.3μm(各々10nmずつで15周期)
[Third Embodiment] FIG. 4 is a sectional view showing a third embodiment of the present invention. In the present embodiment, n
The type superlattice avalanche multiplication layer 3 is configured as follows. Composition: In 0.45 Al 0.55 As (barrier layer) / InAs 0.30
P 0.70 (well layer) Carrier concentration: 2E15 cm -3 Layer thickness: 0.3 μm (15 cycles of 10 nm each)

【0025】第1の実施例では、井戸層を格子定数がI
nPより大きいInAs0.300.70としたため、増倍層
内に歪みが導入される。本実施例においては、基板(I
nP)に格子整合しているIn0.52Al0.48Asに対
し、III 族元素の組成を質量数の小さい元素の比率を高
めるように変化させ、格子定数のより小さいIn0.45
0.55As障壁層3eとして、InAs0.300.70井戸
層3bにより導入された歪みを補償している。これによ
り、増倍層での歪みが緩和され、結晶上転位が入りにく
くなり高品質のエピタキシャル成長が可能になる。
In the first embodiment, the well layer has a lattice constant of I.
Since InAs 0.30 P 0.70 larger than nP is set, strain is introduced into the multiplication layer. In this embodiment, the substrate (I
nP) is lattice-matched to In 0.52 Al 0.48 As, the composition of the group III element is changed so as to increase the ratio of elements having a small mass number, and In 0.45 A having a smaller lattice constant is used.
The 0.55 As barrier layer 3e compensates for the strain introduced by the InAs 0.30 P 0.70 well layer 3b. As a result, strain in the multiplication layer is relaxed, dislocations on the crystal are hard to enter, and high-quality epitaxial growth is possible.

【0026】[第4の実施例]図5は、本発明の第4の
実施例を示す断面図である。本実施例においては、n-
型超格子アバランシェ増倍層3が次のように構成されて
いる。 組成:In0.52Al0.48As0.80.2 (障壁層)/I
nAsP(井戸層) キャリア濃度:2E15cm-3 層厚:0.3μm(各々10nmずつで15周期)
[Fourth Embodiment] FIG. 5 is a sectional view showing a fourth embodiment of the present invention. In the present embodiment, n
The type superlattice avalanche multiplication layer 3 is configured as follows. Composition: In 0.52 Al 0.48 As 0.8 P 0.2 (barrier layer) / I
nAsP (well layer) Carrier concentration: 2E15 cm -3 Layer thickness: 0.3 μm (15 cycles of 10 nm each)

【0027】第2の実施例では、障壁層を格子定数がI
nPより小さいIn0.52Al0.48As0.80.2 とした
ため、増倍層内に歪みが導入される。本実施例において
は、InP井戸層におけるPの一部を他のV族元素置き
換えるようにして、格子定数がInPより大きいInA
sP井戸層3fとして、In0.52Al0.48As0.8
0.2 障壁層3cにより導入された歪みを補償している。
これにより、増倍層での歪みが緩和され、結晶上転位が
入りにくくなり高品質のエピタキシャル成長が可能にな
る。
In the second embodiment, the barrier layer has a lattice constant of I.
Since In 0.52 Al 0.48 As 0.8 P 0.2 is smaller than nP, strain is introduced into the multiplication layer. In the present embodiment, a part of P in the InP well layer is replaced with another V group element so that InA having a lattice constant larger than InP.
As the sP well layer 3f, In 0.52 Al 0.48 As 0.8 P
0.2 compensates for the strain introduced by the barrier layer 3c.
As a result, strain in the multiplication layer is relaxed, dislocations on the crystal are hard to enter, and high-quality epitaxial growth is possible.

【0028】上記のいずれの実施例においても、価電子
帯不連続を極力小さくでき、かつ、伝導帯不連続を大き
くすることができるため、正孔のトラップを抑制しつつ
イオン化率比を高くすることができ、低雑音、高増倍、
高速応答特性を同時に満たすAPDを実現することが可
能になる。
In any of the above embodiments, the valence band discontinuity can be minimized and the conduction band discontinuity can be increased, so that the ionization ratio is increased while suppressing the trapping of holes. Can be low noise, high multiplication,
It becomes possible to realize an APD that simultaneously satisfies high-speed response characteristics.

【0029】なお、上記第1および第2の実施例を併用
することもできる。すなわち、半導体基板に格子整合し
た組成でタイプII超格子となるエネルギーバンド構造を
とる半導体を障壁層と井戸層に選択した後、障壁層と井
戸層の両者のV族元素の組成を変えて価電子帯不連続量
を小さくするようにしても同様の効果を得ることができ
る。
The first and second embodiments can be used together. That is, a semiconductor having an energy band structure of a type II superlattice having a composition lattice-matched with a semiconductor substrate is selected for the barrier layer and the well layer, and then the composition of the group V element of both the barrier layer and the well layer is changed to change the valence. The same effect can be obtained even when the electron band discontinuity is reduced.

【0030】[0030]

【発明の効果】以上説明したように、本発明の半導体受
光素子は、増倍層における障壁層と井戸層の禁制帯幅の
差を主に伝導帯のバンド不連続に反映させ価電子帯のバ
ンド不連続量を極力小さくしたものであるので、イオン
化率比を高く維持しつつバンド不連続部にトラップされ
る正孔を少なくして応答特性の劣化を防止することがで
きる。したがって、本発明によれば、低雑音で高感度・
高速応答特性を有する、すなわち高GB積のAPDを実
現することができる。
As described above, in the semiconductor light receiving element of the present invention, the difference in the forbidden band width between the barrier layer and the well layer in the multiplication layer is mainly reflected in the band discontinuity of the conduction band, and the valence band Since the amount of band discontinuity is made as small as possible, it is possible to prevent degradation of response characteristics by keeping the ionization ratio high and reducing the number of holes trapped in the band discontinuity. Therefore, according to the present invention, low noise and high sensitivity
It is possible to realize an APD having a high-speed response characteristic, that is, a high GB product.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の作用を説明するための、本発明および
従来の受光素子のバンド構造の説明図。
FIG. 1 is an explanatory view of a band structure of a light receiving element of the present invention and a conventional light receiving element for explaining the operation of the present invention.

【図2】本発明の第1の実施例の断面図。FIG. 2 is a sectional view of the first embodiment of the present invention.

【図3】本発明の第2の実施例の断面図。FIG. 3 is a sectional view of a second embodiment of the present invention.

【図4】本発明の第3の実施例の断面図。FIG. 4 is a sectional view of a third embodiment of the present invention.

【図5】本発明の第4の実施例の断面図。FIG. 5 is a sectional view of a fourth embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 n+ 型InP基板 2 n型InPバッファ層 3 n- 型超格子アバランシェ増倍層 3a In0.52Al0.48As障壁層 3b InAs0.30.7 井戸層 3c In0.52Al0.48As0.80.2 障壁層 3d InP井戸層 3e In0.45Al0.55As障壁層 3f InAsP井戸層 4 p型ワイドギャップ電界降下層 5 p- 型InGaAs光吸収層 6 p+ 型InPキャップ層 7 絶縁保護膜 8 p側電極 9 n側電極1 n + type InP substrate 2 n type InP buffer layer 3 n type superlattice avalanche multiplication layer 3a In 0.52 Al 0.48 As barrier layer 3b InAs 0.3 P 0.7 well layer 3c In 0.52 Al 0.48 As 0.8 P 0.2 barrier layer 3d InP Well layer 3e In 0.45 Al 0.55 As barrier layer 3f InAsP well layer 4 p-type wide-gap field drop layer 5 p type InGaAs light absorption layer 6 p + type InP cap layer 7 insulating protection film 8 p-side electrode 9 n-side electrode

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板上にIII −V族半導体からな
る超格子構造アバランシェ増倍層と光吸収層とを備える
半導体受光素子において、前記超格子構造アバランシェ
増倍層を構成する障壁層と井戸層が前記半導体基板と格
子整合する組成においてはタイプII超格子となるエネル
ギーバンド構造をとる半導体であり、かつ、前記障壁層
および/または前記井戸層を構成するV族元素の組成を
変えて価電子帯不連続量を小さくしたことを特徴とする
半導体受光素子。
1. A semiconductor light-receiving element comprising a superlattice structure avalanche multiplication layer made of a III-V group semiconductor and a light absorption layer on a semiconductor substrate, wherein a barrier layer and a well constituting the superlattice structure avalanche multiplication layer. The layer is a semiconductor having an energy band structure that is a type II superlattice in a composition that lattice-matches the semiconductor substrate, and the composition of the group V element forming the barrier layer and / or the well layer is changed to change the valence. A semiconductor light-receiving element characterized by reducing the amount of discontinuity in the electron band.
【請求項2】 V族元素の組成を変えたことにより前記
障壁層または前記井戸層の格子定数と前記半導体基板の
格子定数との間に差が生じたとき、この差と逆方向の差
が前記井戸層または前記障壁層の格子定数と前記半導体
基板の格子定数との間に生じるように前記井戸層または
前記障壁層を構成するIII 族元素の組成を変え、前記障
壁層または前記井戸層に生じた歪みを補償する量の歪み
を前記井戸層または前記障壁層に導入したことを特徴と
する請求項1記載の半導体受光素子。
2. When a difference occurs between the lattice constant of the barrier layer or the well layer and the lattice constant of the semiconductor substrate due to the change in the composition of the group V element, the difference in the opposite direction to this difference is generated. The composition of the group III element constituting the well layer or the barrier layer is changed so that it occurs between the lattice constant of the well layer or the barrier layer and the lattice constant of the semiconductor substrate. 2. The semiconductor light receiving element according to claim 1, wherein an amount of strain that compensates for the generated strain is introduced into the well layer or the barrier layer.
【請求項3】 半導体基板と格子整合する前記障壁層と
前記井戸層がそれぞれInAlAsとInPであり、V
族元素の組成を変えることが前記障壁層のAsの一部を
Pに置き換えることと前記井戸層のPの一部をAsと置
き換えることである請求項1記載の半導体受光素子。
3. The barrier layer and the well layer lattice-matched with a semiconductor substrate are InAlAs and InP, respectively, and V
2. The semiconductor light receiving element according to claim 1, wherein changing the composition of the group element is replacing part of As in the barrier layer with P and replacing part of P in the well layer with As.
JP6321178A 1994-12-01 1994-12-01 Semiconductor photodetector Pending JPH08162664A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6321178A JPH08162664A (en) 1994-12-01 1994-12-01 Semiconductor photodetector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6321178A JPH08162664A (en) 1994-12-01 1994-12-01 Semiconductor photodetector

Publications (1)

Publication Number Publication Date
JPH08162664A true JPH08162664A (en) 1996-06-21

Family

ID=18129669

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6321178A Pending JPH08162664A (en) 1994-12-01 1994-12-01 Semiconductor photodetector

Country Status (1)

Country Link
JP (1) JPH08162664A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022004292A1 (en) * 2020-07-03 2022-01-06 信越半導体株式会社 Junction semiconductor light-receiving element and production method for junction semiconductor light-receiving element

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03270179A (en) * 1990-03-20 1991-12-02 Fujitsu Ltd Light detector
JPH06291357A (en) * 1993-03-31 1994-10-18 Nec Corp Semiconductor light receiving device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03270179A (en) * 1990-03-20 1991-12-02 Fujitsu Ltd Light detector
JPH06291357A (en) * 1993-03-31 1994-10-18 Nec Corp Semiconductor light receiving device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022004292A1 (en) * 2020-07-03 2022-01-06 信越半導体株式会社 Junction semiconductor light-receiving element and production method for junction semiconductor light-receiving element
JP2022013244A (en) * 2020-07-03 2022-01-18 信越半導体株式会社 Junction type semiconductor light-receiving element, and manufacturing method for junction type semiconductor light-receiving element

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