JPH08162613A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PURPOSE: To provide a high performance semiconductor integrated circuit device of high reliability, and a manufacturing method capable of manufacturing said device in a small area by a simple manufacturing process. CONSTITUTION: A semiconductor integrated circuit device has a transistor constituted in the following manner. A base region 8 formed in a part of the surface of a semiconductor substrate 6 where a plurality of semiconductor elements are three-dimensionally formed surrounding an emitter region 7. Collector regions 9, 10 are three-dimensionally formed on the peripheral part of the base region 8, surrounding it. Thereby a transistor of sufficiently high breakdown voltage structure can be formed in a small region, and the emitter region is made as small as possible, so that the input capacitance can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and more particularly to a technique effectively applied to a semiconductor integrated circuit device requiring a high performance protection circuit.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit device, abnormal static electricity may be accidentally applied from the outside. Therefore, it is conceivable that a protection circuit is provided to protect the semiconductor elements and the like that form the internal circuit of the semiconductor integrated circuit device from the above-mentioned abnormal static electricity.

The protection circuit is provided by being inserted between a pad electrode to which abnormal static electricity can be input and an internal circuit connected to the pad electrode, and when abnormal static electricity is applied to the pad electrode at any time. In addition, the protection circuit controls so that abnormal static electricity is not applied to the internal circuit of the semiconductor integrated circuit device, and it is possible to obtain a high-performance product that can prevent the occurrence of defects due to abnormal static electricity. .

As the protection circuit, a circuit using a resistor, an npn type bipolar transistor and a field effect transistor (FET) can be considered.

When the protection circuit is incorporated in a MOS type semiconductor integrated circuit device, as shown in FIG. 10, an npn type lateral (horizontal type) structure in which a p type semiconductor substrate 20 is formed as a base region of an npn type bipolar transistor is used. It is considered that adopting a bipolar transistor is more effective than the simplicity of the manufacturing process. In FIG. 10, 21 is an emitter region electrically connected to the pad electrode, and 22 is a collector region.

[0006] Documents describing a semiconductor device having a protection circuit include, for example, Japanese Patent Laid-Open No. 56-6.
Some are described in Japanese Patent Publication No. 7962.

[0007]

However, the current path of the npn lateral bipolar transistor described above, that is, the current path, flows into the emitter region 21 electrically connected to the pad electrode to which abnormal static electricity can be input. After that, it is formed so as to flow to the collector region 22 around the base width in the lateral direction.

Therefore, in order to increase the electrostatic withstand voltage, it is necessary to secure a sufficient current path region. In that case,
The present inventor has found that there is a problem that the base width region of the base region in the semiconductor substrate 20 needs to have a wide area, which leads to a wide area of the npn lateral bipolar transistor.

When an npn-type bipolar transistor is used in the protection circuit, it is necessary to increase the withstand voltage of the npn-type bipolar transistor in order to increase the electrostatic withstand voltage. There is a problem that the base width region of the region needs to have a large area, which leads to an increase in the area of the npn lateral bipolar transistor.

Further, when an npn type bipolar transistor is used for the protection circuit, in order to reduce the area, it is necessary to make the base width region of the base region narrow correspondingly. That leads to a decrease in the breakdown voltage of the npn lateral bipolar transistor,
There is a problem that the electrostatic breakdown voltage of the protection circuit is lowered.

On the other hand, current semiconductor integrated circuit devices are required to have high performance and high integration. In that case,
Providing a large area for forming a protection circuit is inefficient, and it is necessary to obtain high reliability by increasing electrostatic withstand voltage of the protection circuit. However, when the area of the npn-type lateral bipolar transistor described above is reduced, the electrostatic breakdown voltage of the protection circuit decreases, and conversely, in order to obtain a high-performance protection circuit by increasing the electrostatic breakdown voltage, the npn-type bipolar transistor should be Since it is necessary to increase the breakdown voltage, the area becomes large, and it is extremely difficult to manufacture a high-performance and highly-integrated semiconductor integrated circuit device with the structure of the npn lateral bipolar transistor. The present inventor has found that

An object of the present invention is to provide a semiconductor integrated circuit device having high reliability and high performance.

Another object of the present invention is to provide a manufacturing technique capable of manufacturing a highly reliable and high performance semiconductor integrated circuit device in a small area by a simple manufacturing process.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0015]

The typical ones of the inventions disclosed in the present application will be outlined below.

In the semiconductor integrated circuit device of the present invention, the base region formed on a part of the surface of the semiconductor substrate on which a plurality of semiconductor elements are formed surrounds the emitter region and is formed three-dimensionally. It is assumed that a bipolar transistor having a collector region which is three-dimensionally formed around the base region and has a shape surrounding the base region is provided.

[0017]

According to the above-described semiconductor integrated circuit device of the present invention, the base-emitter junction region between the base region and the emitter region and the base-collector junction region between the base region and the collector region in the bipolar transistor are: Since it consists of a region facing the collector region in the lateral direction of the emitter region and a region facing the collector region in the bottom direction of the emitter region, it serves as a current path without increasing the occupied area of the emitter region. Since the area of the facing surface can be increased, a transistor having a sufficiently high breakdown voltage structure can be provided in a small area, and the input area can be reduced because the emitter area can be made as small as possible.

[0018]

Embodiments of the present invention will now be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numerals, and a duplicate description will be omitted.

1 and 2 are views showing a semiconductor integrated circuit device which is an embodiment of the present invention. FIG. 1 is a plan view,
FIG. 2 is a perspective view including a cross section taken along the line AA in FIG. The semiconductor integrated circuit device of the present invention will be described with reference to FIG.

1 and 2 show a region of an npn-type bipolar transistor which constitutes a protection circuit of a MOS type semiconductor integrated circuit device, and a semiconductor substrate 6 has a MOSFET (not shown) or the like. A plurality of semiconductor elements are formed.

In the protection circuit, as shown in FIG. 9, an npn-type bipolar transistor 3 is electrically connected to a pad electrode 1 to which abnormal static electricity may be input, via a resistor 2. A field effect transistor (FET) 4 is electrically connected to it. The protection circuit composed of these constituent elements is electrically connected to the internal circuit 5 of the semiconductor integrated circuit device.

The protection circuit includes a resistor 2, an npn-type bipolar transistor 3 and a field effect transistor (FET) 4 as constituent elements, and includes a pad electrode 1 and an internal circuit 5 to which abnormal static electricity can be input. The protective circuit is provided so as to prevent abnormal static electricity from being applied to the internal circuit 5 of the semiconductor integrated circuit device even if abnormal static electricity is applied to the pad electrode 1 at any time. It controls. As a result, it is possible to obtain a high-performance product that can prevent the occurrence of defects due to abnormal static electricity.

As shown in FIGS. 1 and 2, the npn-type bipolar transistor 3 constituting the protection circuit of the MOS semiconductor integrated circuit device is formed on the surface of the semiconductor substrate 6.
An emitter region 7 electrically connected to the pad electrode 1,
A base region 8 having a three-dimensional shape around the base region 8 and a collector region 9 that is three-dimensionally configured to surround the base region 8;
It consists of 10. As shown in FIG. 1, the base region 8 is connected to the semiconductor substrate 6 through a region where the collector regions 9 and 10 are partly isolated from each other. The base electrode of the base region 8 is provided on the surface of a certain semiconductor substrate 6.

3 to 8 are sectional views showing a method of manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention described above. A method of manufacturing the semiconductor integrated circuit device of the present invention will be described with reference to FIG.

First, as shown in FIG. 3, the protection circuit described above is formed in an active region of a semiconductor substrate 6 made of, for example, p-type silicon single crystal, and a plurality of field effect transistors (FETs) are formed in other active regions. 2), a field insulating film 11 made of silicon oxide for element isolation is formed on the surface of the semiconductor substrate 6. Although not shown, a channel stopper layer for preventing inversion is formed under the field insulating film 11.

Next, as shown in FIG. 4, a photoresist film 12 serving as a mask for photoetching is formed on the surface of the semiconductor substrate 6 including the active region surrounded by the field insulating film 11.

Next, using the photoresist film 12 as a mask for photo-etching, the semiconductor substrate 6 is selectively etched by dry etching such as sputter etching to form the groove 13.

Next, an n-type region to be the collector region 9 of the npn-type bipolar transistor is formed at the bottom of the groove 13 by diffusing impurities such as phosphorus (P) into the semiconductor substrate 6.

Next, the p-type base region 8 is formed in the groove 13 by using a selective epitaxial technique. In this case, the impurity concentration of the p-type base region 8 can be formed to have a peculiar concentration, or it can be the same as the semiconductor substrate 6.

Next, as shown in FIG. 6, after removing the photoresist film 12, a diffusion mask formed on the surface of the semiconductor substrate 6 is formed of, for example, a multi-layer film of a silicon nitride film and a silicon oxide film. The mask film 14 is formed, the region of the diffusion mask film 14 on the region to be the collector region is selectively removed, and the diffusion mask film 14 is used as a diffusion mask to remove n-type impurities such as phosphorus (P). A collector region 10 is formed so as to be integrated with the collector region 9 by being diffused into the semiconductor substrate 6 and the p-type base region 8.

Next, as shown in FIG. 7, after the diffusion mask film 14 is removed, a new diffusion mask, for example, a multilayer film of a silicon nitride film and a silicon oxide film, is formed on the surface of the semiconductor substrate 6. A diffusion mask film 15 is formed,
A region on the region which becomes the emitter region thereof is selectively removed, and n-type impurities such as arsenic (As) are diffused into the p-type base region 8 by using the diffusion mask film 15 as a diffusion mask. The emitter region 7 is formed. in this case,
By adjusting the depth of the diffusion layer of the emitter region 7 and the depth of the base region 8 from the surface, the base width can be controlled to a predetermined value.

Next, as shown in FIG. 8, after the diffusion mask film 15 is removed, a silicon oxide film 16 is newly formed on the surface of the semiconductor substrate 6 by the CVD method or the like to form each npn bipolar transistor. After selectively removing the region of the silicon oxide film 16 on the region to be the electrode of the region, the emitter electrode 17, the aluminum film is formed on the semiconductor substrate 6 and the selective etching technique thereof is used.
The base electrode 18 and the collector electrode 19 are formed.

Before or after the step of manufacturing the npn-type bipolar transistor, or in combination with each step, a semiconductor element constituting a semiconductor integrated circuit device such as a MOSFET is formed in another active region of the semiconductor substrate 6.

That is, although not shown, a gate insulating film made of silicon oxide is formed on the surface of another active region of the semiconductor substrate 6, and a gate electrode made of polycrystalline silicon is formed on the gate insulating film. The gate electrode is formed by sequentially depositing an insulating film made of a polycrystalline silicon film and a silicon oxide film on the gate insulating film on the surface of the semiconductor substrate 6 and sequentially etching these.

Next, a sidewall insulating film made of silicon oxide is formed on the sidewall of the gate electrode.

Next, using the insulating film on the gate electrode and the sidewall insulating film as a mask, the semiconductor substrate 6 is ion-implanted with an n-type impurity to serve as a source and a drain.
A type semiconductor region is formed.

Next, after forming an aluminum film on the semiconductor substrate 6, the aluminum film in an unnecessary region is removed by using a photoetching technique, and a source contact electrode, a drain contact electrode, a gate contact electrode and their respective contacts are formed. An electric wiring film connected to the electrodes is formed. The material of the electric wiring film may be, in addition to the aluminum film, any combination having electric conductivity such as a polycrystalline silicon film or a laminated film of a polycrystalline silicon film and a high melting point silicide film.

When the emitter region 7 and its emitter electrode 17 are formed, since the depth of the diffusion layer in the emitter region 7 is shallow, the base region 8 forming the emitter region 7 is formed.
A polycrystalline silicon film is formed by utilizing a polycrystalline silicon film when forming a gate electrode in a peripheral MOSFET on the surface of the polycrystalline silicon film, and the polycrystalline silicon film contains a high concentration of n-type impurities. It is possible to adopt a mode in which the emitter region 7 is formed by diffusing Pd into the base region 8 and the emitter electrode 17 is formed using a polycrystalline silicon film.

In order to form the collector regions 9 and 10 and the base region 8, it is possible to adopt a mode in which impurities are formed on the active region of the semiconductor substrate 6 by thermal diffusion or high energy ion implantation. it can.

In the npn-type bipolar transistor in the protection circuit described above, the base region 8 is the emitter region 7
Is formed in a three-dimensional shape and surrounds the base region 8, and has a three-dimensionally formed collector region 9 and 10 surrounding the base region 8. is there.

Therefore, the base region 8 and the emitter region 7
Base-emitter junction region between and and base region 8
The base-collector junction region between the collector region 9 and the collector region 9 and 10 faces the lateral collector region 10 of the emitter region 7 and the bottom collector region 9 of the emitter region 7. It is composed of areas and regions.

Therefore, in the structure of the npn-type bipolar transistor, a transistor having a sufficiently high breakdown voltage structure can be provided in a small area, and the emitter region 7 can be made as small as possible to reduce the input capacitance. be able to. As a result, even if abnormal static electricity is applied to the pad electrode 1, the npn is sufficiently
Shaped bipolar transistor can prevent this from transmitting abnormal static electricity to internal circuits. Therefore, a high-reliability and high-performance protection circuit having a high withstand voltage and a small input capacitance can be provided in a small area.

Further, the protection circuit can utilize the semiconductor substrate 6 which is an active region in the MOS type semiconductor integrated circuit device as a region of the bipolar transistor.
Moreover, since the manufacturing process of the MOSFET can be diverted, it can be formed by a simple manufacturing process.

It is needless to say that the present invention is not limited to the above-mentioned embodiment, but can be variously modified without departing from the scope of the invention. Specifically, the protection circuit or the bipolar transistor can be applied to the form of a BiMOS, CMOS or BiCMOS type semiconductor integrated circuit device. In addition, an npn-type bipolar transistor is
The structure of the np type bipolar transistor can be adopted, and it can be applied to a mode of a semiconductor integrated circuit device having a bipolar transistor having a high breakdown voltage, high reliability and high performance.

[0045]

The effects obtained by the typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the semiconductor integrated circuit device of the present invention, the base-emitter junction region between the base region and the emitter region and the base-collector junction region between the base region and the collector region in the bipolar transistor are formed. , A region facing the collector region in the lateral direction of the emitter region and a region facing the collector region in the bottom direction of the emitter region, so that the current path can be formed without increasing the occupied area of the emitter region. Since it is possible to increase the area of the opposing surface, it is possible to provide a transistor having a sufficiently high breakdown voltage structure in a small area, and it is possible to reduce the input capacitance because the emitter area can be made as small as possible. .

Further, by forming a protection circuit using the above-mentioned bipolar transistor as a part of the constituent elements, even if abnormal static electricity is applied to the pad electrode, it can be sufficiently caught by the bipolar transistor. , Abnormal static electricity will not be transmitted to the internal circuit. Therefore, a high-reliability and high-performance protection circuit having a high withstand voltage and a small input capacitance can be provided in a small area.

(2) According to the method for manufacturing a semiconductor integrated circuit device of the present invention, the above-described protection circuit can utilize the semiconductor substrate which is the active region in the MOS type semiconductor integrated circuit device as the region of the bipolar transistor. ,
Moreover, since the manufacturing process of the MOSFET can be diverted, it can be formed by a simple manufacturing process.

[Brief description of drawings]

FIG. 1 is a plan view showing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 2 is a perspective view showing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 8 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 9 is a circuit diagram showing a protection circuit in a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 10 is a perspective view showing an npn-type lateral bipolar transistor included in a possible protection circuit.

[Explanation of symbols]

 1 Pad Electrode 2 Resistor 3 Bipolar Transistor 4 Field Effect Transistor 5 Internal Circuit 6 Semiconductor Substrate 7 Emitter Region 8 Base Region 9 Collector Region 10 Collector Region 11 Field Insulation Film 12 Photoresist Film 13 Groove 14 Diffusion Mask Film 15 Diffusion Mask Film 16 Silicon oxide film 17 Emitter electrode 18 Base electrode 19 Collector electrode 20 Semiconductor substrate 21 Emitter region 22 Collector region

Claims (5)

[Claims] 1. An emitter region formed on a part of a surface of a semiconductor substrate on which a plurality of semiconductor elements are formed,
A base region formed on a side surface and a bottom surface of the emitter region, and a collector region formed on a side surface and a bottom surface of the base region, and a part of the collector region is isolated by the semiconductor substrate. And a bipolar transistor having a structure in which the base region is electrically connected to the semiconductor substrate around the collector region by the region of the semiconductor substrate in the isolated region. Integrated circuit device. 2. The semiconductor integrated circuit device according to claim 1, wherein the plurality of semiconductor elements formed on the semiconductor substrate include field effect transistors. 3. The semiconductor integrated circuit device according to claim 1, wherein the plurality of semiconductor elements formed on the semiconductor substrate include field effect transistors, and the bipolar transistor is the plurality of semiconductor elements. A semiconductor integrated circuit device, which is used as a constituent element of a protection circuit for protecting an element from an abnormal voltage. 4. A step of forming a groove in a part of a semiconductor substrate of the first conductivity type, a step of forming a collector region of the second conductivity type in a bottom surface of the groove, and a step of filling the groove with a semiconductor material. Forming a base region of one conductivity type, and then diffusing impurities of the second conductivity type from the surface of the semiconductor substrate to form a collector region of the second conductivity type electrically connected to the collector region; And a step of forming a second conductive type emitter region in a part of the first conductive type base region. 5. The method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein a plurality of field effect transistors are formed on the first conductive type semiconductor substrate, and the groove is filled with a semiconductor material. A method of manufacturing a semiconductor integrated circuit device, characterized in that a selective epitaxial technique is used to form a base region of the mold.